JPH03291960A - Substrate for semiconductor-device lamination and laminated semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the dislocation between an interconnection terminal pattern on the surface and an interconnection terminal pattern on the rear when the interconnection terminal patterns are formed on the surface and the rear of an insulating substrate and the interconnection terminal patterns are overlapped by a method wherein identical interconnection terminal patterns are formed on identical faces of one pair of substrates to be overlapped so as to be turned mutually by 180 deg.. CONSTITUTION:These are substrates for semiconductor-device lamination use in which interconnection terminal patterns 9 formed on the surface and the rear of insulating substrates 8 are overlapped and connected electrically. Identical interconnection terminal patterns are formed on identical faces of one pair of substrates for semiconductor-device lamination use to be overlapped in such a way that they are turned mutually by 180 deg.. For example, identical interconnection terminal patterns 9 are formed On identical faces of four identical frame members 8 on an insulating substrate 200 so as to be turned mutually by 180 deg.. That is to say, the identical interconnection terminal patterns 9 as they are and the interconnection terminal patterns 9 which have turned them by 180 deg. are formed alternately. on the identical faces of the individual frame members 8. This assembly is divided and cut off; the identical interconnection terminal patterns 9 formed on the identical faces of the individual frame members 8 are overlapped and connected by using a throguhhole interconnection 10.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a substrate for stacking semiconductor devices in which wiring terminal patterns formed on the front and back sides of an insulating substrate are overlapped and electrically connected;
and a laminated semiconductor device in which laminated substrates on which a plurality of semiconductor devices are mounted are stacked and electrically connected via a wiring terminal pattern and through-hole wiring, in particular when forming the laminated semiconductor device, the semiconductor device The present invention relates to a technique for reducing relative positional deviations of wiring terminal patterns on laminated substrates.

[Conventional technology]

Traditionally, TAB (T
Ape Automated Bonding) method is available.

A feature of this TAB method is that finger-shaped leads are made to protrude into the device hole, and a semiconductor chip is aligned face-up and bonded to the tip of this lead.

In this TAB method, the width of the leads has become narrower as the number of bins has increased, and its mechanical strength has become weaker. As a result, the outer leads are bent or warped, which not only impedes the bonding work of the outer leads to the wiring board, but also reduces the reliability of the bonding.

Therefore, as a countermeasure to this problem, as described in JP-A-1-217933, a frame member is attached to the tape carrier so that the outer leads do not protrude from the edge of the tape, or the outer leads are attached to the back side of the frame member. It has been proposed to bend the

[Problem to be solved by the invention]

By the way, one of the inventors of the present invention has
An attempt was made to improve the packaging density by stacking the conventional TAB type semiconductor devices described in the publication.

In other words, wiring terminal patterns are formed on the front and back sides of the insulating substrate,
Wiring terminal patterns were overlapped to electrically connect them, and semiconductor devices were stacked and mounted in multiple layers.

During this trial production, wiring terminal patterns are formed on the front and back sides of the insulating substrate, and when the wiring terminal patterns are superimposed, the seventh
As shown in Figure (a), due to mechanical precision, lens aberration, and other defects, the wiring terminal pattern on the front surface of the wiring board and the wiring terminal pattern on the back surface are misaligned, resulting in a short circuit with the adjacent wiring. I found out.

An object of the present invention is to form wiring terminal patterns on the front and back sides of an insulating substrate, and when overlapping the wiring terminal patterns, a positional shift occurs between the wiring terminal pattern on the front side of the wiring board and the wiring terminal pattern on the back side. The object of the present invention is to provide a technology that can prevent short circuits with wiring.

Another object of the present invention is to provide a technique that does not cause misalignment between the wiring terminal pattern on the front surface of the wiring board and the wiring terminal pattern on the back surface when overlapping the wiring terminal patterns provided on the front and back surfaces of the wiring board. It's about doing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) A semiconductor device stacking board for overlapping and electrically connecting wiring terminal patterns formed on the front and back surfaces of an insulating substrate, wherein the same wiring is provided on the same side of the pair of overlapping semiconductor device stacking boards. This is a substrate for stacking semiconductor devices in which terminal patterns are formed by rotating them by 180 degrees.

(2) Photolithography techniques such as glass epoxy resin and ceramic can be used for the substrate for laminating semiconductor devices!
Consisting of I materials.

(3) A through-hole electric wire is provided in the semiconductor device lamination substrate, a semiconductor chip is mounted on the semiconductor device lamination substrate, and one of the semiconductor device lamination substrates on which the semiconductor chip is mounted is provided.
A laminated semiconductor device in which one or more of the same wiring terminal patterns are stacked on top of each other, and the wiring terminals of each semiconductor device lamination substrate are electrically connected via the wiring terminal pattern and through-hole wiring. .

(4) In a method for manufacturing a laminated semiconductor device in which a semiconductor device is mounted on a substrate and the substrates are stacked to mount a plurality of semiconductor devices, photolithography is performed on the same side of an insulating substrate made of glass epoxy resin, ceramic, etc. A method for manufacturing a laminated semiconductor device in which identical wiring terminal patterns are formed by rotating them by 180 degrees using lithography technology, they are cut into sections, the identical wiring terminal patterns are superimposed on each other, and they are electrically connected by through-hole wiring. It is.

(5) The semiconductor device is specifically assumed to be of the TAB type.

[For production]

According to the above-mentioned means (1), a pair of identical wiring terminal patterns to be overlapped are formed on the same surface of the semiconductor device stacking substrate by reversing each other.

Since one of these semiconductor device stacking substrates is rotated 180 degrees and superimposed, the wiring terminal patterns of both can be superimposed without misalignment.

According to means (2), the semiconductor device stacking substrate is made of an insulating material that can be used with photolithography technology, such as glass epoxy resin or ceramic, so that the 111! Relationships are maintained.

According to means (3), since a plurality of lamination substrates on which semiconductor devices are mounted are stacked, it is possible to improve the packaging density of semiconductor devices.

According to means (4), identical wiring terminal patterns are formed on the same surface of an insulating substrate made of laminated glass epoxy resin, ceramic, etc. by photolithography, rotated by 180 degrees, and then cut into sections. Since the same wiring terminal patterns are overlapped and electrically connected by through-hole wiring, a laminated semiconductor device can be easily manufactured.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

It should be noted that throughout the explanation of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

1 is a perspective view showing the overall structure of a memory module in which a plurality of semiconductor device stacking substrates are stacked according to an embodiment of the present invention; FIG. 2 is an enlarged view of one stacked TAB shown in FIG. 1; 3 is a sectional view taken along the line A--A in FIG. 2, and FIG. 4 is an enlarged view of the wiring terminal pattern portion shown in FIG. 2.

The memory module of this embodiment, as shown in FIG.
A plurality of laminated T A B 100 are stacked and mounted on a mounting base substrate 200 . In the figure, BP is an external terminal. The mounting base board 200 has a length of 24 mm and a width of 8 mm.
It is about the size of 9mm.

Then, as shown in FIGS. 2 and 3, the laminated T A
The lead 7 of one TABl of B 100 is bonded to the gold bump 3 provided on the circuit forming surface of the semiconductor chip 6 and the inner lead 7A, and extends from there to the outer lead 7B. Further, the main surface and both side surfaces of the semiconductor chip 6 are sealed with a resin 5 such as resin.

The outer lead 7B of the lead 7 is connected to a wiring terminal pattern 9 of a frame member 8 made of glass epoxy resin.

In this way, the laminated T A B 100 is constructed by stacking four layers of TABl (■, ■, ■, ■). The leads 7 are supported by the insulating base film 4 before being bonded.

Further, the selection of each TAB1 of the laminated TAB 100 is performed by the chip select pin 2 of each TAB1, as shown in FIGS. 4A, 4B, 4C, and 4D. Chip select pin 2 is the first TA from the bottom.
Chip select pin RASO1 to select the Bl chip
Chip select pin RAS1 selects the second TABl chip from the bottom, chip select pin RAS2 selects the third TABl chip from the bottom, chip select pin RAS selects the fourth TABI chip from the bottom.
It consists of 3.

The chip select pin RASO is the first T from the bottom.
Through-hole wiring lO to wiring terminal pattern 9A of ABl
electrically connected.

The chip select pin RASI is the second TAB from the bottom.
It is electrically connected to the wiring terminal pattern 9B of 1 by a through-hole wiring 10.

Chip select pin RAS2 is the third TAB from the bottom
It is electrically connected to the wiring terminal pattern 9C of 1 by a through-hole wiring 10.

Chip select bin RAS8 is the fourth TAB from the bottom.
It is electrically connected to the wiring terminal pattern 9D of 1 by a through-hole wiring 10.

Next, the wiring terminal pattern 9 provided on the frame member 8 made of the glass epoxy resin will be explained.

FIG. 5 is an explanatory diagram for explaining the structure of the wiring terminal pattern 9 of this embodiment and the method of forming it, and is
) is a conventional wiring terminal pattern design diagram, right side (b) @ is a wiring terminal pattern design diagram of this embodiment, and (c) is an even wiring terminal pattern.

As shown in FIG. 5-(b), the wiring terminal pattern 9 is formed on the same surface (surface (or the back surface), the same wiring terminal patterns 9 are formed by photolithography by rotating each other by 180 degrees.

That is, as shown in Figure (Q), the same wiring terminal pattern 9 as it is and the wiring terminal pattern 9 rotated 180 degrees are alternately placed on the same side (front or back side) of each frame member 8. ) to form.

Then, they are cut into parts, and the same wiring terminal patterns 9 formed on the same surface (front or back surface) of each frame member 8 are overlapped and electrically connected by through-hole arrangement 110.

The method for manufacturing the wiring terminal pattern 9 and through-hole wiring 10 on the front and back surfaces of the frame member 8 is as shown in FIG. 6A. First, as shown in FIG. , steel with a thickness of about 8 μm (
Paste Cu) foil 8B and form a through hole 8C by NC processing using a drill as shown in Fig. 6B. Next, as shown in Fig. 6C, form the base for electroless steel (Cu) plating. , on which electrolytic copper (C
U) Form plating film 8D. Next, as shown in FIG. 6D, a wiring terminal pattern including through holes 8C is formed by photolithography, and a 10 to 30μ
The process is completed by forming a solder plating film 8E with a thickness of about m.

As can be seen from the above description, according to this embodiment, by overlapping the same wiring terminal patterns 9 formed on the same surface (front or back surface) of each frame member (semiconductor device stacking substrate) 8, Since the wiring terminal patterns 9 to be overlapped do not shift in position, when overlapping the wiring terminal patterns,
It is possible to prevent the wiring terminal pattern on the front surface of each frame member 8 and the wiring terminal pattern 9 on the back surface from being misaligned and short-circuiting with the adjacent wiring.

For example, if the exposure position of the wiring terminal pattern 9 deviates from the predetermined position due to a defect due to machine precision, lens aberration, etc., the surface of the frame member 81 (
When the wiring terminal pattern 9 on the top surface) and the wiring terminal pattern 9 on the back surface (bottom surface) of the frame member 82 are overlapped, the frame member 8
! However, according to this embodiment, the wiring terminal pattern 9 on the front surface (top surface) and the wiring terminal pattern 9 on the back surface (bottom surface) of the frame member 82 are misaligned, causing a short circuit with the adjacent wiring terminal pattern 9. As shown in FIG. 7(b), the wiring terminal pattern 9 on the front surface (upper surface) of the frame member 81 and the wiring terminal pattern 9 on the back surface (lower surface) of the frame member 82 do not shift.

Therefore, even if the exposure position of the wiring terminal pattern 9 deviates from a predetermined position due to a defect due to mechanical precision, lens aberration, etc., short-circuiting with the adjacent wiring terminal pattern 9 will not occur.

Further, according to this embodiment, the frame member (substrate for semiconductor device stacking) '8 is made of an insulating material that can be used with photolithography technology, such as glass epoxy resin or ceramic. The insulation between the substrates) 8 is maintained.

Furthermore, since a plurality of frame members 8 for mounting semiconductor chips (substrates for stacking semiconductor devices) 8 are stacked, the mounting density of semiconductor chips can be improved.

Further, on the same side of a frame member (substrate for semiconductor device stacking) 8 made of a plurality of glass epoxy resins, ceramics, etc., the same overlapping wiring terminal patterns 9 are alternately rotated by 180 degrees and formed by photolithography, Since they are cut into pieces, the same wiring terminal patterns 9 are overlapped, and electrically connected through the through-hole wiring 10, it is possible to easily manufacture a memory module made of laminated TAB.

In the embodiments described above, the present invention has been explained using an example of a memory module made of stacked TABs, but it is obvious that the present invention can be applied to the mounting of semiconductor devices using other packaging methods.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

A brief explanation of the effects obtained by the representative inventions disclosed in this application is as follows: (1) The wiring terminal patterns can be overlapped because there is no displacement of the wiring terminal patterns to be overlapped. At this time, it is possible to prevent the wiring terminal pattern on the front surface of the wiring board from being misaligned with the wiring terminal pattern on the back surface, thereby preventing short circuits with adjacent wirings.

(2) The semiconductor device lamination substrate is made of glass epoxy resin,
Since it is made of an insulating material that can be used with photolithography technology, such as ceramic, insulation between the semiconductor device stacking substrates is maintained.

(3) Since a plurality of laminating substrates each having a semiconductor device mounted thereon are stacked, the packaging density of the semiconductor device can be improved.

(4) Form overlapping identical wiring terminal patterns on the same surface of multiple insulating substrates by rotating them alternately by 180 degrees using photolithographic technology, cutting them into pieces, overlapping the same wiring terminal patterns, and through them. Since electrical connection is made through hole wiring, a stacked semiconductor device can be easily manufactured.

[Brief explanation of drawings]

FIG. 1 is a perspective view showing the overall structure of a memory module in which a plurality of semiconductor device stacking substrates according to an embodiment of the present invention are stacked together. FIG. 2 is an enlarged view of one stacked TAB shown in FIG. 1. , FIG. 3 is a sectional view taken along the line A-A in FIG. 2, and FIGS. 4A, 4B, 4c, and 4D are enlarged views of the wiring terminal pattern portion shown in FIG. FIG. 5 is an explanatory diagram for explaining the configuration of the wiring terminal pattern and its formation method in this embodiment, and FIGS. 6A, 6B, 6C, and 6D are
FIG. 3 is a diagram for explaining a method for manufacturing a wiring terminal pattern and through-hole wiring according to the present embodiment. FIG. 7 is an explanatory diagram for explaining the effects of this embodiment. In the figure, 1... TAB, 2... Chip select pin,
3... Gold hump, 4... Insulating base film, 6...
...For sealing, resin, 6... Semiconductor chip, 7... Lead, 7A... Inner lead, 7B... Outer lead, 8... Frame member, 9... Wiring terminal pattern,
10... Through-hole wiring, 20... Board, 100
...Laminated TAB, 20'0... Mounting base board. Figure 4A Figure 4B Figure 4C Figure 4D Figure 6A

Claims (1)

[Scope of Claims] 1. A semiconductor device lamination substrate for overlapping and electrically connecting wiring terminal patterns formed on the front and back surfaces of an insulating substrate, comprising: a pair of semiconductor device lamination substrates to be overlaid; A substrate for laminating semiconductor devices, characterized in that the same wiring terminal patterns are formed on the same surface by rotating each other by 180 degrees. 2. The substrate for stacking semiconductor devices according to claim 1, wherein the substrate for stacking semiconductor devices is made of an insulating material that can be used with photolithography technology, such as glass epoxy resin or ceramic. 3. Providing through-hole wiring in the semiconductor device stacking substrate according to claim 1, mounting a semiconductor chip on the semiconductor device stacking substrate, and one or more semiconductor device stacking substrates having the semiconductor chip mounted thereon. A laminated semiconductor device characterized in that the semiconductor devices are stacked so that the same wiring terminal patterns are overlapped, and the wiring terminals of each semiconductor device lamination substrate are electrically connected via the wiring terminal pattern and through-hole wiring. . 4. In a method for manufacturing a laminated semiconductor device in which a semiconductor device is mounted on a substrate and a plurality of semiconductor devices are mounted by stacking the substrates, photolithography is performed on the same surface of an insulating substrate made of a laminated number of glass epoxy resins, ceramics, etc. A laminated semiconductor characterized by forming identical wiring terminal patterns by rotating them by 180 degrees using technology, cutting them into parts, overlapping the same wiring terminal patterns, and electrically connecting them with through-hole wiring. Method of manufacturing the device. 5. The semiconductor device according to claim 3 or 4 is any package applicable to this method, and a stacked semiconductor device using the same or a method for manufacturing the same.