JPH05216964A - Wiring modification system on printed circuit board - Google Patents

Wiring modification system on printed circuit board

Info

Publication number
JPH05216964A
JPH05216964A JP4019085A JP1908592A JPH05216964A JP H05216964 A JPH05216964 A JP H05216964A JP 4019085 A JP4019085 A JP 4019085A JP 1908592 A JP1908592 A JP 1908592A JP H05216964 A JPH05216964 A JP H05216964A
Authority
JP
Japan
Prior art keywords
wiring
section
wirings
electrical
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4019085A
Other languages
Japanese (ja)
Inventor
Satoshi Takada
聡 高田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Solution Innovators Ltd
Original Assignee
NEC Software Hokuriku Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Software Hokuriku Ltd filed Critical NEC Software Hokuriku Ltd
Priority to JP4019085A priority Critical patent/JPH05216964A/en
Publication of JPH05216964A publication Critical patent/JPH05216964A/en
Withdrawn legal-status Critical Current

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Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To provide a wiring modification system which is capable of easily modifying wiring, which require quite short time for the modification of the wiring, and by which such an error section can be found in all case. CONSTITUTION:A wiring route search means 1 follows up a wiring route of each circuit from plural circuits by means of a computer. An electric influence calculation means 2 calculates in a numeric value and seeks various kinds of adverse electrical influences of the respective wiring routes searched by the wiring route search means 1 on the other adjacent wirings. A shield pattern insertion means 3 inserts a shield wiring which is electrically stable, has an ability of blocking the electrical influence and which does not have an external effect into the clearance between the wiring sections in which a preliminarily set allowance value is exceeded by the value obtained by the electrical influence calculation means 2.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、プリント基板上の回路
設計において、隣接した配線同士が電気的影響を及ぼす
場合の配線修正方式に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring correction method when adjacent wirings electrically affect each other in a circuit design on a printed circuit board.

【0002】[0002]

【従来の技術】一般に、プリント基板上の複雑な回路設
計はコンピュータの画面上で行われる。従来、多数の回
路パターンから一の回路を特定する配線経路探索により
回路の配線経路中に、他の配線に対して電気的な悪影響
を与えている配線区間(以下エラー区間という)が発見
された場合、探索処理を終了した後、コンピュータの画
面上で逐次回路パターンや配線の位置を修正している。
2. Description of the Related Art Generally, a complicated circuit design on a printed circuit board is performed on a computer screen. Conventionally, a wiring section (hereinafter referred to as an error section) that has an electrical adverse effect on another wiring is found in the wiring path of the circuit by searching the wiring path for identifying one circuit from a large number of circuit patterns. In this case, after the search process is completed, the positions of the circuit patterns and wirings are corrected on the screen of the computer.

【0003】[0003]

【発明が解決しようとする課題】上記従来の方式におい
ては、配線の修正が容易でなく、配線の修正に時間がか
かり、かつ、そのようなエラー区間を発見することがで
きない場合があるという問題がある。
In the above-mentioned conventional method, it is not easy to correct the wiring, it takes time to correct the wiring, and it may be impossible to find such an error section. There is.

【0004】そこで、本発明の課題は、配線の修正が容
易であり、配線の修正に時間がかからず、かつ、そのよ
うなエラー区間を発見することができない場合がない配
線修正方式を提供することにある。
Therefore, an object of the present invention is to provide a wiring correction method in which the wiring can be easily corrected, the wiring can be corrected in a short time, and such an error section cannot be found. To do.

【0005】[0005]

【課題を解決するための手段】本発明によれば、多数の
配線中から隣接する配線に電気的影響を与えている配線
区間を探索し、この区間の配線相互間に、電気的影響を
遮断するシールド用の配線を挿入することを特徴とする
プリント基板上の配線修正方式が得られる。
According to the present invention, a wiring section that electrically affects adjacent wirings is searched from a large number of wirings, and the electrical effect is cut off between the wirings in this section. It is possible to obtain a wiring correction method on a printed circuit board, which is characterized in that a wiring for a shield is inserted.

【0006】また、本発明によれば、全回路について配
線の経路を追い、各経路について隣設する配線相互間の
電気的影響を計算して、予め設定した許容値を越える配
線間に、電気的に安定して電気的影響を遮断する以外に
機能しないシールド用の配線を挿入することを特徴とす
るプリント基板上の配線修正方式が得られる。
Further, according to the present invention, the route of the wiring is traced for all the circuits, and the electrical influence between the wirings adjacent to each route is calculated, and the electrical influence between the wirings exceeding the preset allowable value is calculated. A wiring correction method on a printed circuit board is obtained, which is characterized in that a wiring for a shield that does not function except for stably blocking the electrical influence is inserted.

【0007】また、本発明によれば、全回路について配
線の経路を探索し、各経路について隣設する配線相互間
の電気的影響を計算して、予め設定した許容値を越える
電気的影響を有する配線区間を見つけ出し、その中の一
の配線区間を抽出して、その区間の配線相互の間隔が電
気的に安定して電気的影響を遮断する以外に機能しない
シールド用の配線を挿入可能か否かを判断し、可能であ
ればシールド用の配線を挿入するが、不可能であればそ
の配線区間内の相互の間隔を部分的に広げてシールド用
の配線を挿入することにより前記許容値以下にすること
を特徴とするプリント基板上の配線修正方式が得られ
る。
Further, according to the present invention, the route of the wiring is searched for all the circuits, and the electrical influence between the adjacent wirings is calculated for each route, and the electrical influence exceeding the preset allowable value is calculated. Is it possible to find out the wiring section that has it, extract one wiring section from it, and insert a shield wiring that does not function except that the spacing between the wiring in that section is electrically stable and cuts off the electrical influence? Whether or not it is possible, insert the shield wiring, but if it is not possible, partially widen the mutual intervals in the wiring section and insert the shield wiring. A wiring correction method on a printed circuit board characterized by the following is obtained.

【0008】[0008]

【実施例】本発明の一実施例を図面について説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings.

【0009】図1は、本実施例の電気回路の配線方法の
ブロック図である。図1において、符号1は配線経路探
索手段であり、従来と同様にしてコンピュータを用いて
多数の回路から各回路の配線経路を追っていく。電気的
影響計算手段2は、前記配線経路探索手段1で探索され
た各配線経路について、隣設した他の配線に与える種々
の電気的な悪影響を数値として計算し導き出す。シール
ドパターン挿入手段3は、前記電気的影響計算手段2で
算出された数値が予め設定された許容値を越えている配
線区間相互の隙間に、電気的に安定しており、上記電気
的影響を遮断する機能を有し、かつ、他に外的作用を及
ぼすことがないシールド用の配線(以下シールドパター
ンという)を挿入する。
FIG. 1 is a block diagram of a wiring method for an electric circuit according to this embodiment. In FIG. 1, reference numeral 1 is a wiring route searching means, which follows a wiring route of each circuit from a large number of circuits by using a computer as in the conventional case. The electrical effect calculation means 2 calculates and derives various electrical adverse effects on other wirings adjacent to each wiring path searched by the wiring path searching means 1 as numerical values. The shield pattern inserting means 3 is electrically stable in the gap between the wiring sections where the numerical value calculated by the electric influence calculating means 2 exceeds a preset allowable value, and the electric influence is A shield wiring (hereinafter referred to as a shield pattern) that has a function of blocking and does not exert any external action is inserted.

【0010】図2は、本実施例の電気回路の配線方式の
フローチャートである。図2において、ステップ10で
は、全回路の配線経路を探索する。ステップ11では、
探索されたすべての配線経路について他の回路に与える
電気的影響を計算する。ステップ12では、エラー区間
が有るか否かを判断し、エラー区間がない場合には全体
の処理を終了する。エラー区間の判別は、ステップ12
で計算した電気的影響が予め設定した許容値と比較し
て、これを越えているか否かにより行う。
FIG. 2 is a flow chart of the wiring method of the electric circuit of this embodiment. In FIG. 2, in step 10, the wiring paths of all circuits are searched. In step 11,
The electrical influence on other circuits is calculated for all the searched wiring paths. In step 12, it is judged whether or not there is an error section, and if there is no error section, the entire processing is ended. Step 12 is to determine the error section.
The electrical influence calculated in step 1 is compared with a preset allowable value, and it is determined whether or not it exceeds this.

【0011】ステップ13では、エラー区間の全てにつ
いて修正処理したか否かを判断し、処理している場合に
は全体の処理を終了する。ステップ14では、確認され
たエラー区間のうちから一のエラー区間を修正処理の対
象として抽出する。ステップ15では、抽出した一のエ
ラー区間とこの区間から電気的影響を受けている他の配
線区間との間にシールドパターンを挿入するのに必要な
間隔があるか否かを判断する。
At step 13, it is judged whether or not the correction processing has been performed for all the error sections, and if the correction processing has been performed, the entire processing is ended. In step 14, one error section is extracted from the confirmed error sections as a target of the correction process. In step 15, it is determined whether or not there is an interval required to insert the shield pattern between the extracted one error section and another wiring section which is electrically affected by this section.

【0012】ステップ15でシールドパターンを挿入す
る間隔が有ると判断された場合にステップ16では一の
エラー区間と他の配線区間との間にシールドパターンを
挿入する。ステップ15でシールドパターンの挿入間隔
がないと判断された場合に、ステップ17ではエラー区
間及び他の配線区間の押し分け配線を行う。ステップ1
7での押し分け配線により形成した挿入スペースにステ
ップ18でシールドパターンを挿入する。ステップ18
での押し分け配線により移動した配線についてステップ
19で電気的影響を再度計算する。この後、ステップ1
3に戻り、エラー区間の修正処理の要否を判断し、以後
全エラー区間が修正されるまで上記手順が繰り返され
る。
When it is determined in step 15 that there is an interval for inserting the shield pattern, in step 16 the shield pattern is inserted between one error section and another wiring section. When it is determined in step 15 that there is no shield pattern insertion interval, in step 17, wiring is performed separately for the error section and other wiring sections. Step 1
In step 18, the shield pattern is inserted into the insertion space formed by the pressed wiring in 7. Step 18
In step 19, the electrical influence is recalculated for the wiring moved by the pressed wiring in. After this, step 1
Returning to step 3, it is judged whether the correction processing of the error section is necessary, and thereafter, the above procedure is repeated until all the error sections are corrected.

【0013】シールドパターンの挿入に当たっては、図
3(A)に示すように、間隔をおいて互いに対向する配
線禁止領域20,21の間に、配線22,23が通され
ており、両者の間隔が比較的広い場合には、同図(B)
に示すように、配線22,23間にシールドパターン2
4が挿入される。しかし、図4(A)に示すように、配
線禁止領域25,26間に多数の配線が通っているなど
のために、その中の配線25,26の間隔が比較的狭く
なっている場合には、同図(B)に示すように、配線2
5,26を周りの配線と共に位置をずらして押し分け配
線を行うことにより挿入スペースを確保する。即ち、挿
入スペースは必ずしもエラー区間の全範囲にわたって空
ける必要はなく、電気的影響が許容値以下になる範囲で
足りる。
When inserting the shield pattern, as shown in FIG. 3 (A), wirings 22 and 23 are provided between the wiring prohibiting regions 20 and 21 facing each other with a space therebetween, and the space between the two is provided. Is relatively wide, the same figure (B)
As shown in FIG.
4 is inserted. However, as shown in FIG. 4 (A), when a large number of wirings pass between the wiring prohibited areas 25 and 26, the distance between the wirings 25 and 26 therein is relatively small. Is the wiring 2 as shown in FIG.
The insertion space is secured by shifting the positions of the wirings 5 and 26 together with the surrounding wiring and pushing them separately. That is, the insertion space does not necessarily have to be vacant over the entire range of the error section, and it is sufficient if the electrical influence is within the allowable value.

【0014】[0014]

【発明の効果】以上のように、本発明は、多数の配線中
から隣設する配線に電気的影響を与えている配線区間を
探索し、この区間の配線相互間に、電気的に安定して電
気的影響を遮断する以外に機能しないシールド用の配線
を挿入する方式を採用したため、シールドパターンによ
って配線間に生じる電気的な悪影響を遮断することがで
きるから、他の回路に悪影響を及ぼすことがなく、エラ
ー区間を完全に発見して修正され、プリント基板の品質
を向上させることができ、かつ、エラー区間を修正する
のに配線位置の変更がないから実質的な回路パターンの
変更がないので作業を容易に行うことができ、これに要
する時間を短縮することができる。
As described above, according to the present invention, a wiring section that electrically influences an adjacent wiring is searched from a large number of wirings, and the wirings in this section are electrically stable. Since a method for inserting a shield wiring that does not function other than blocking the electrical effect is adopted, it is possible to block the electrical adverse effect that occurs between the wirings by the shield pattern, which may adversely affect other circuits. There is no error, the error section can be completely found and corrected, the quality of the printed circuit board can be improved, and there is no change in the wiring position to correct the error section, so there is no substantial change in the circuit pattern. Therefore, the work can be easily performed, and the time required for this can be shortened.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係るプリント基板上の配線修正方式を
示すブロック図である。
FIG. 1 is a block diagram showing a wiring correction method on a printed circuit board according to the present invention.

【図2】本発明に係るプリント基板上の配線修正方式を
説明するためのフローチャートである。
FIG. 2 is a flow chart for explaining a wiring correction method on a printed circuit board according to the present invention.

【図3】(A)は本発明の1実施例に係る修正前の配線
状態を示す概略図であり、かつ、(B)は本発明の1実
施例に係る修正後の配線状態を示す概略図である。
FIG. 3A is a schematic view showing a wiring state before correction according to one embodiment of the present invention, and FIG. 3B is a schematic view showing a wiring state after correction according to one embodiment of the present invention. It is a figure.

【図4】(A)は本発明の他の実施例に係る修正前の配
線状態を示す概略図であり、かつ、(B)は本発明の他
の実施例に係る修正後の配線状態を示す概略図である。
FIG. 4A is a schematic view showing a wiring state before correction according to another embodiment of the present invention, and FIG. 4B shows a wiring state after correction according to another embodiment of the present invention. It is a schematic diagram showing.

【符号の説明】[Explanation of symbols]

1 配線経路探索手段 2 電気的影響計算手段 3 シールドパタ−ン挿入手段 20 配線禁止領域 21 配線禁止領域 22 配線 23 配線 24 シールドパターン 25 配線禁止領域 26 配線禁止領域 27 配線 28 配線 29 シールドパターン DESCRIPTION OF SYMBOLS 1 Wiring route searching means 2 Electric effect calculation means 3 Shield pattern inserting means 20 Wiring prohibited area 21 Wiring prohibited area 22 Wiring 23 Wiring 24 Shield pattern 25 Wiring prohibited area 26 Wiring prohibited area 27 Wiring 28 Wiring 29 Shield pattern

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 多数の配線中から隣接する配線に電気的
影響を与えている配線区間を探索し、この区間の配線相
互間に、電気的影響を遮断するシールド用の配線を挿入
することを特徴とするプリント基板上の配線修正方式。
1. A search is made for a wiring section that electrically affects adjacent wirings from a large number of wirings, and a wiring for shielding that blocks the electrical effect is inserted between the wirings in this section. A characteristic wiring correction method on the printed circuit board.
【請求項2】 全回路について配線の経路を追い、各経
路について隣設する配線相互間の電気的影響を計算し
て、予め設定した許容値を越える配線間に、電気的に安
定して電気的影響を遮断する以外に機能しないシールド
用の配線を挿入することを特徴とするプリント基板上の
配線修正方式。
2. A wiring route is traced for all circuits, and an electrical influence between adjacent wiring lines is calculated for each route to electrically stabilize the wiring between wiring lines exceeding a preset allowable value. A wiring correction method on a printed circuit board, which inserts a wiring for a shield that does not function except for blocking the physical influence.
【請求項3】 全回路について配線の経路を探索し、各
経路について隣設する配線相互間の電気的影響を計算し
て、予め設定した許容値を越える電気的影響を有する配
線区間を見つけ出し、その中の一の配線区間を抽出し
て、その区間の配線相互の間隔が電気的に安定して電気
的影響を遮断する以外に機能しないシールド用の配線を
挿入可能か否かを判断し、可能であればシールド用の配
線を挿入するが、不可能であればその配線区間内の相互
の間隔を部分的に広げてシールド用の配線を挿入するこ
とにより前記許容値以下にすることを特徴とするプリン
ト基板上の配線修正方式。
3. A wiring route is searched for for all circuits, an electrical influence between adjacent wirings is calculated for each route, and a wiring section having an electrical influence exceeding a preset allowable value is found, Extract one wiring section in it, and judge whether it is possible to insert a shield wiring that does not function except that the distance between the wirings in that section is electrically stable and cuts off the electrical influence, If possible, insert the wiring for shielding, but if not possible, partially widen the mutual distance in the wiring section and insert the wiring for shielding to make it less than the allowable value. Wiring correction method on the printed circuit board.
JP4019085A 1992-02-04 1992-02-04 Wiring modification system on printed circuit board Withdrawn JPH05216964A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4019085A JPH05216964A (en) 1992-02-04 1992-02-04 Wiring modification system on printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4019085A JPH05216964A (en) 1992-02-04 1992-02-04 Wiring modification system on printed circuit board

Publications (1)

Publication Number Publication Date
JPH05216964A true JPH05216964A (en) 1993-08-27

Family

ID=11989618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4019085A Withdrawn JPH05216964A (en) 1992-02-04 1992-02-04 Wiring modification system on printed circuit board

Country Status (1)

Country Link
JP (1) JPH05216964A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08123851A (en) * 1994-10-28 1996-05-17 Nec Corp Automatic method for deciding wiring path

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08123851A (en) * 1994-10-28 1996-05-17 Nec Corp Automatic method for deciding wiring path
JP2877003B2 (en) * 1994-10-28 1999-03-31 日本電気株式会社 Automatic wiring route determination method

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