JPH04251382A - Method for performing wiring processing on printed bard - Google Patents

Abstract

PURPOSE:To improve the manufacturing quality of a printed board by improving the wiring ratio of automatic wiring on the printed board and, at the same time, suppressing the occurrence of unnecessary via holes. CONSTITUTION:Firstly, whether or not a pin to be positioned in a V/G area is contained in a pin pair which is the object of a printed board wiring process (Step S3) and, when the pin is contained, the pin pair is wired without regarding the V/G area as a fault area (Steps S4 and S5). When wiring is completed on all pins, clearances are secured between the wiring pattern in the V/G area and V/G area (Step S7) and the overlapping state of the clearances, cutting of the V/G area into parts by the clearances, etc., are checked and the shapes of the V/G area and clearances are suitably shaped in compliance with a design rule or manufacturing rule.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a printed circuit board CAD (computer-aided design) system used for pattern design of printed circuit boards (printed wiring boards), and particularly for printed circuit boards with power supply/ground areas (V/G areas). The present invention relates to a printed circuit board wiring processing method suitable for automatic pattern wiring on a board.

0002

2. Description of the Related Art One of the design processes performed using a CAD system is an automatic wiring process that automatically generates a pattern to be wired on a printed circuit board. This automatic wiring process calculates the route to be routed based on net pin pair information (information on pin pairs to be connected), prohibited areas where wiring cannot be done, and fault information such as different nets and general conductors. was common. If a required pattern cannot be generated in a wiring layer due to the presence of a failure, a method has been used in which the layer to be wired is changed using a via hole and wiring is performed.

0003

As described above, according to the conventional wiring processing method, fault information created in pre-processing of wiring processing is always treated as a fault in subsequent pattern generation. With this method, if the board is a multilayer board, switching the wiring layers will not cause a big problem, but it is a double-sided board and the power/ground (volt/ground) area, the so-called V/G area, is large on the board. In the case of a so-called mixed negative and positive substrate that occupies a large area, there is a problem in that the wiring area is limited and an improvement in the wiring rate cannot be expected. For this reason, in the past, it was necessary to connect the V/G signal by manual wiring before automatic wiring, and there was a problem that the application rate of automatic wiring could not be improved.

The present invention was made in view of the above circumstances, and its purpose is to improve the wiring rate of automatic wiring, especially on a board containing negative and positive substrates, and to improve manufacturing quality by suppressing the generation of unnecessary via holes. An object of the present invention is to provide a printed circuit board wiring processing method.

[0005]

[Means for Solving the Problems] This invention provides that for pin pairs having pins existing in the V/G area,
Perform wiring without considering the area as a failure area, that is, as if there is no V/G area, and in post-processing after wiring, ensure clearance between the V/G area and the wiring pattern on the same area, Furthermore, if necessary, the shape of the V/G area and the clearance can be shaped.

[0006]

[Operation] In the wiring processing method with the above configuration, first the V/G
When the information (fault information) of all fault areas on the printed circuit board including the fault area is created, the information of the net that is the target of the printed circuit board wiring is extracted. Then, it is checked whether the pin pairs indicated by the net information include pins located in the V/G area, and for pin pairs that have pins located in the V/G area,
Wiring is performed with the G area removed from the fault area, that is, assuming that the V/G area does not exist. When wiring processing for all pin pairs is completed, V/
Clearance is ensured between the G area and the wiring pattern on the same area. Then, the overlap of the secured clearances, the division of the V/G area by the clearance, etc. are checked, and the shapes of the V/G area and the clearance are appropriately shaped to match the design rules and manufacturing rules.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a flow chart for explaining the steps of a printed circuit board wiring processing method applied in a printed circuit board CAD system according to an embodiment of the present invention. In the figure, S1 is a step for creating fault information for the printed circuit board (fault information creation step), and S2 is a step for extracting information about a net to be wired (net information extraction step). S3 examines the position of the pin pair indicated by the net information extracted in step S2,
Step S4 is a step for detecting a pin existing in the V/G area (pin position determination step), and step S4 is a step for temporarily removing the V/G area from fault information according to the determination (detection) result in step S3. (V/G area release step).

S5 is a step for wiring the pin pair indicated by the net information extracted in step S2 while checking prohibited areas and fault information (net wiring processing step), and S6 is for determining whether the wiring processing for all nets has been completed. This is a step for S7 is a step for creating a clearance between the wiring pattern and the V/G area (clearance creation step), and S8 is a step for shaping the V/G area and clearance shape (clearance shaping step).

FIG. 2 is a diagram for explaining a specific example of board wiring according to the processing procedure shown in the flowchart of FIG. In the figure, 1 is a printed circuit board, and 2 is a V/G area on the board 1. 3, 4 and 5 are pin pairs; 6 and 7 are pins that constitute pin pair 3; 8 and 9 are pins that constitute pin pair 4; and 10 and 11 are pins that constitute pin pair 5. 12 is a wiring pattern (for pin pair 3) for connecting pins 6 and 7, and 13 is a wiring pattern (for pin pair 3) for connecting pins 8 and 9.
A wiring pattern 14 (of pin pair 4) is a wiring pattern (of pin pair 5) for connecting pins 10 and 11.

Next, the operation of one embodiment of the present invention will be explained with reference to FIGS. 1 and 2 as appropriate. First, Figure 2 (a
) When the automatic wiring function of the printed circuit board CAD system (not shown) is started for automatic wiring targeting the printed circuit board 1 in the initial state as shown in FIG. 1, the printed circuit board wiring process according to the flowchart of FIG. . As a result, all fault information in the printed circuit board 1 is created in the first step S1. Subsequently, information on the net to be wired (connected) is extracted (step S2). Since the processes in steps S1 and S2 above are the same as those in the prior art, the details thereof will be omitted.

Next, it is checked whether the pins constituting the pin pair indicated by the net information extracted in step S2 are within the V/G area (step S3). If there is a pin located within the V/G area, its V/G
The G area is temporarily removed from the fault (step 4). That is, the corresponding V/G area is temporarily excluded from the fault information created in step S1. Then, in this state (with the V/G area cleared from the fault), net wiring processing is performed (step S5). On the other hand, V/
If there is no pin located within the G area, the process directly advances to step S5, and net wiring processing is performed in the same manner as before.

From the above, in the example of FIG. 2(a), the following net wiring processing is performed. First, since pin 6 for pin pair 3 and pin 8 for pin pair 4 are both within V/G area 2, the above step S4 is performed and V/G area 2 is temporarily removed from the fault. . Therefore, as a result of the net wiring in the next step S5, pin pair 3 has pins 6 and 7 as shown in FIG. 2(b).
The wiring pattern 12 (of pin pair 3) that connects the V/G
Automatically routed without avoiding area 2. Similarly, for pin pair 4, the wiring pattern 13 (of pin pair 4) connecting pins 8 and 9 is automatically routed without avoiding the V/G area 2.

Next, regarding pin pair 5, pins 10,
11 is not within the V/G area 2, step S4 is skipped and the net wiring process of step S5 is performed. As a result, for pin pair 5, V/G
Area 2 is treated as a failure, and the wiring pattern 14 (of pin pair 5) connecting pins 10 and 11 is automatically routed avoiding V/G area 2, as shown in FIG. 2(b).

Now, when the net wiring process in step S5 is completed, it is checked whether the wiring process for all nets has been completed (step S6). If there is an unwired net, the process returns to step S2 and information on the next net to be wired is extracted, and the series of processes up to step S5 described above are performed for this net.

As described above, as shown in FIG. 2(b), when the wiring process for all the nets on the printed circuit board 1 is completed and the determination in step S6 is YES, step S7 is performed.
Proceed to the clearance creation process. In this step S7, as shown in FIG. A clearance is created (secured) between the

When step S7 is completed, the process finally proceeds to step S8, a clearance shaping process. In this step S8, a process is performed to detect areas that do not match the design rules and manufacturing rules by checking whether the clearances created in step S7 overlap or if the V/G area 2 is divided, etc. As shown in d), the shape of the corresponding location (V/G area 2 and clearance) is shaped (corrected).

FIG. 3 shows the difference between printed circuit board wiring according to the printed circuit board wiring processing method according to the embodiment of the present invention described above and printed circuit board wiring according to the conventional method. First, FIG. 3(a) shows an example of printed circuit board wiring according to the printed circuit board wiring processing method according to the embodiment of the present invention.
(b) shows an example of printed circuit board wiring according to the conventional method. In the figure, 31, 32 are the front surfaces of the printed circuit boards, 33,
34 is the back surface as well. 35 and 36 are the V/G areas on the front surfaces 31 and 32, 37 and 38 are the back surface 3
Prohibited area on 3, 34 (wiring prohibited area), 39, 4
0 is a pin pair including pins located on the V/G areas 35 and 36. 41 is the wiring pattern of the pin pair 39 created on the front surface 31 by temporarily removing the V/G area 35 from the fault area, 42 and 43 are the wiring patterns of the front surface 32 and the back surface in order to avoid the V/G area 36. 34
The wiring pattern 44 created by dividing the upper part is a via hole for connecting the wiring patterns 42 and 43.

As is clear from FIGS. 3(a) and 3(b),
The substrate wiring according to the method of the embodiment of the present invention has the advantage that a larger wiring area can be taken than the conventional method, and there is no need to create unnecessary via holes.

[0019]

[Effects of the Invention] As detailed above, according to the present invention,
If a pin pair with a pin in the V/G area is detected, wiring is performed for that pin pair in the same way as if the V/G area does not exist, and post-processing after wiring is performed to connect the V/G area and pattern. Since the configuration is such that clearance is secured between the printed circuit board and shaping, etc., the wiring rate of automatic wiring is increased especially in a negative/positive mixed board, and the rate of application of automatic wiring in printed circuit board design is improved. Furthermore, the number of man-hours required for pre-wiring can be reduced, resulting in a significant reduction in the number of design man-hours. Furthermore, since the number of via holes used can be reduced compared to conventional methods, manufacturing quality is also improved.

[Brief explanation of the drawing]

FIG. 1 is a flowchart for explaining the procedure of a printed circuit board wiring processing method according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a specific example of board wiring in the same embodiment.

FIG. 3 is a diagram for explaining the difference between printed circuit board wiring in the same embodiment and printed circuit board wiring according to the conventional method.

[Explanation of symbols]

S3...Pin position determination step (first step), S4
...V/G area release step (second step), S5
...Net wiring processing step (third step), S7...
Clearance creation step (fourth step), S8...
Clearance shaping step (fifth step), 1...Printed circuit board, 2, 35, 36...V/G area, 3-5,
39, 40...Pin pair, 12-14, 41-43...Wiring pattern.

Claims (1)

[Claims] [Claim 1] A first method for determining whether or not a pin located in a power supply/ground area indicated as a fault area by fault information is included in a pin pair of a net to be subjected to printed circuit board wiring processing. step, and in this first step, if it is determined that the pin pair includes a pin located in the power supply/ground area, the power supply/ground area is temporarily set to the fault information. a second step of wiring the pin pair while checking the fault information, etc., and a third step of wiring the pin pair while checking the fault information, etc., and a third step of wiring the pin pair while checking the fault information, etc. / a fourth step of securing a clearance between the ground area and the power supply/ground area, and a fifth step of shaping the clearance secured in the fourth step and the shape of the power supply/ground area. A printed circuit board wiring processing method.