JPH052162A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To suppress the peeling of a sealing material and to improve a yield and reliability by using nearly the same materials for the constituting materials of the sealing material and the protective films of color filters. CONSTITUTION:The sealing material SL is formed over the entire circumference at the edges of transparent glass substrates SUB1, SUB2 exclusive of a liquid crystal sealing port and is so constituted as to adhere the upper and lower transparent glass substrates SUB1, SUB2 and to seal the liquid crystal LC between the two substrates. The protective film PSV2 is provided to prevent the leakage of the dyes selectively dyeing the color filters FIL to different colors to the liquid crystal LC. The protective film PSV2 of the color filters FIL consists of, for example, a thermosetting type phenol novolak epoxy resin and the sealing material SL consists of the compsn. formed by adding an inorg. filler, such as alumina or silicon dioxide, to the thermosetting type phenol novolak epoxy resin which is the same constituting material as the constituting material of the protective film PSV2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
In particular, it relates to a color liquid crystal display device having a color filter.

[0002]

2. Description of the Related Art For example, an active matrix type liquid crystal display device is provided with a non-linear element (switching element) corresponding to each of a plurality of pixel electrodes arranged in a matrix. Since the liquid crystal in each pixel is theoretically always driven (duty ratio 1.0), the active system has better contrast than the so-called simple matrix system, which employs the time-division driving system, and especially the color liquid crystal display device. Then it is becoming an indispensable technology. A typical example of the switching element is a thin film transistor (TFT).

An active matrix type liquid crystal display device using thin film transistors is disclosed in, for example, "12.5 type active matrix type color liquid crystal display employing a redundant configuration", Nikkei Electronics, p.
~ 210, known on December 15, 1986, published by Nikkei McGraw-Hill Inc.

In the liquid crystal display unit (liquid crystal display panel), a thin film transistor, a transparent pixel electrode, a protective film for the thin film transistor, and a lower alignment film for setting the orientation of liquid crystal molecules are sequentially provided on a lower transparent glass substrate with a liquid crystal layer as a reference. The lower transparent substrate and the upper transparent substrate on which the black matrix, the color filter, the protective film for the color filter, the common transparent pixel electrode, and the upper alignment film are sequentially provided on the upper transparent glass substrate so that the alignment films face each other. Then, the two substrates are adhered to each other by a sealing material arranged around the edges of the substrates and the liquid crystal is sealed between the two substrates. A backlight is arranged on one of the substrates.

As the conventional sealant, a thermosetting resin and an ultraviolet curing resin are mainly used. In order to bond both transparent substrates with a sealing material, a sealing material is provided on the protective film of the color filter on the upper transparent substrate side to bond both substrates.

[0006]

Conventionally, no consideration has been given to the adhesive strength of the sealing material, and the sealing material is subjected to mechanical stress in the manufacturing process of the liquid crystal display part or during use, and under the environment of temperature and humidity. There is a problem that peeling mainly occurs between the sealing material and the protective film of the color filter due to a difference in thermal expansion and contraction between the protective film and the protective film of the color filter.

An object of the present invention is to provide a liquid crystal display device which suppresses peeling between the sealing material and the protective film of the color filter, resulting in high yield and high reliability.

[0008]

In order to achieve the above object, the present invention provides a first transparent pixel electrode, a first transparent substrate on which a first alignment film is formed, a color filter, and the above color filter. The protective film, the second transparent pixel electrode, and the second transparent substrate on which the second alignment film is formed at a predetermined interval so that the alignment films face each other. In a liquid crystal display device in which both substrates are adhered to each other by a sealing material provided around an edge between them, and a liquid crystal is sealed between the both substrates, constituent materials (component, molecular weight) of the sealing material and the protective film of the color filter are used. ) Are almost the same (including the same).

[0009]

[Function] By making the sealing material and the protective film of the color filter, which are easily peeled off, substantially the same in material, the difference in thermal expansion and contraction at the interface between the sealing material and the protective film of the color filter is eliminated. Since the adhesive strength can be increased, peeling of the sealing material can be suppressed.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An active matrix type color liquid crystal display device to which the present invention should be applied will be described below.

In all the drawings for explaining the liquid crystal display device, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

The structure of the present invention will be described below together with an embodiment in which the present invention is applied to an active matrix type color liquid crystal display device.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a block diagram of an active system according to an embodiment of the present invention.
(TFT part (: 1-1 cutting line part in FIG. 3) of the liquid crystal display part (liquid crystal display element) of the matrix type color liquid crystal display device)
And (a sealing portion).

FIG. 2 is a plan view showing one pixel and its periphery of the liquid crystal display device to which the present invention is applied, and FIG. 3 is a sectional view taken along the line 3-3 in FIG. In addition, FIG. 4 (plan view of the main part)
2 shows a plan view when a plurality of pixels shown in FIG. 2 are arranged.

(Pixel Arrangement) As shown in FIG. 2, each pixel has two adjacent scanning signal lines (gate signal lines or horizontal signal lines) GL and two adjacent video signal lines (drain signal lines or drain signal lines). The signal line is arranged in a crossing region with the vertical signal line DL (in a region surrounded by four signal lines). Each pixel includes a thin film transistor TFT, a transparent pixel electrode ITO1 and a storage capacitor element Cadd. The scanning signal lines GL extend in the column direction, and a plurality of scanning signal lines GL are arranged in the row direction. Video signal line DL
Extend in the row direction and are arranged in the column direction.

(Overall Structure of Display Section) As shown in FIG. 1, a thin film transistor TFT and a transparent pixel electrode ITO1 are provided on the lower transparent glass substrate SUB1 side based on the liquid crystal LC.
And a color filter FIL and a light blocking film BM forming a black matrix pattern for light blocking are formed on the upper transparent glass substrate SUB2 side. The lower transparent glass substrate SUB1 has a thickness of, for example, about 1.1 [mm]. Further, a silicon oxide film SIO formed by dipping or the like is provided on both surfaces of the transparent glass substrates SUB1 and SUB2. Therefore, even if there are sharp scratches on the surfaces of the transparent glass substrates SUB1 and SUB2,
Since the sharp scratch can be covered with the silicon oxide film SIO, it is possible to effectively prevent the scanning signal line GL and the color filter FIL from being damaged.

1 shows the cross section of one pixel portion, the left side shows the cross section of the left edge portion of the transparent glass substrates SUB1 and SUB2 where the external lead wiring exists, and the right side is transparent. The cross section of the right edge portion of the glass substrates SUB1 and SUB2 where no external lead-out wiring is present is shown.

Alignment films ORI1 and ORI2, transparent pixel electrode ITO1, common transparent pixel electrode ITO2, protective film PSV
The respective layers of 1, PSV2, and the insulating film GI are formed inside the sealing material SL. The polarizing plates POL1 and POL2 are formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.

The liquid crystal LC is enclosed between a lower alignment film ORI1 and an upper alignment film ORI2 that set the orientation of liquid crystal molecules, and is sealed by a sealing material SL.

The lower alignment film ORI1 is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.

On the inner surface (liquid crystal LC side) of the upper transparent glass substrate SUB2, a light shielding film BM and a color filter FI are provided.
L, a color filter protective film PSV2, a common transparent pixel electrode ITO2 (COM), and an upper alignment film ORI2 are sequentially stacked.

This liquid crystal display device has a lower transparent glass substrate S.
The layers on the UB1 side and the upper transparent glass substrate SUB2 side are separately formed, and then the upper and lower transparent glass substrates SUB are formed.
1 and SUB2 are superposed on each other, and a liquid crystal LC is sealed between them to assemble.

(Light-shielding film BM) Upper transparent glass substrate SUB
A light-shielding film BM is provided on the second side so that external light (light from above in FIG. 1) does not enter the i-type semiconductor layer AS used as a channel formation region.
The pattern is as shown by the hatching. Incidentally, FIG. 7 shows the third conductive film d made of the ITO film in FIG.
FIG. 3 is a plan view illustrating only the color filter FIL and the light shielding film BM. The light-shielding film BM is formed of, for example, an aluminum film or a chrome film having a high light-shielding property,
In this liquid crystal display device, the chromium film is 1300 by sputtering.
It is formed to a film thickness of about [Å].

Therefore, the thin film transistors TFT1,
The i-type semiconductor layer AS of the TFT 2 is sandwiched by the upper and lower light-shielding films BM and the large gate electrode GT, and that portion is not exposed to external natural light or backlight light. The light-shielding film BM is formed around the pixel as shown by the hatched portion in FIG. 7, that is, the light-shielding film BM is formed in a grid shape (black matrix), and the effective display area of one pixel is partitioned by this grid. . Therefore, the contour of each pixel is made clear by the light shielding film BM, and the contrast is improved. That is, the light-shielding film BM is the i-type semiconductor layer A.
It has two functions of blocking light for S and a black matrix.

A portion facing the edge portion of the transparent pixel electrode ITO1 on the base side in the rubbing direction (lower right portion in FIG. 2).
Since the light is shielded by the light shielding film BM, even if a domain is generated in the above portion, the domain cannot be seen, so that the display characteristics are not deteriorated.

The backlight may be attached to the upper transparent glass substrate SUB2 side and the lower transparent glass substrate SUB1 may be the observation side (externally exposed side).

(Common Transparent Pixel Electrode ITO2) The common transparent pixel electrode ITO2 faces the transparent pixel electrode ITO1 provided for each pixel on the lower transparent glass substrate SUB1 side, and the optical state of the liquid crystal LC is the pixel electrode ITO1. And the common transparent pixel electrode ITO2 change in response to a potential difference (electric field). A common voltage Vcom is applied to the common transparent pixel electrode ITO2. The common voltage Vcom is an intermediate potential between the low level drive voltage Vdmin and the high level drive voltage Vdmax applied to the video signal line DL.

The common transparent pixel electrode ITO2 on the upper transparent glass substrate SUB2 side is connected to the external lead wiring formed on the lower transparent glass substrate SUB1 side by the silver paste material SIL at at least one place. The external lead-out wiring is formed in the same manufacturing process as that of the gate electrode GT, the source electrode SD1 and the drain electrode SD2.

(Color Filter FIL) The color filter FIL is formed by coloring a dyeing base material made of a resin material such as acrylic resin with a dye. Color filter F
ILs are formed in stripes at positions facing the pixels (FIG. 8) and are dyed separately (FIG. 8 shows only the third conductive film layer d3, the light shielding film BM and the color filter FIL in FIG. 4, B, R, G color filters FI
L is 45 °, 135 °, and has a cross hatch). As shown in FIG. 7, the color filter FIL is formed to have a large size so as to cover the entire transparent pixel electrode ITO1, and the light-shielding film BM overlaps the edge portions of the color filter FIL and the transparent pixel electrode ITO1.
It is formed inside the peripheral portion of TO1.

The color filter FIL can be formed as follows. First, a dyeing base material is formed on the surface of the upper transparent glass substrate SUB2, and the dyeing base material other than the red filter forming region is removed by a photolithography technique. After that, the dyed substrate is dyed with a red dye and a fixing process is performed to form a red filter R. Next, the green filter G and the blue filter B are sequentially formed by performing the same process.

(Sealing material SL and protective film PSV2) The sealing material SL shown on the left side and the right side of FIG. 1 is a transparent glass substrate SUB1 excluding a liquid crystal filling port (not shown),
It is formed along the entire periphery of the edge of SUB2, and the upper and lower transparent glass substrates SUB1 and SUB2 are bonded together, and
The liquid crystal LC is sealed between both substrates.
The protective film PSV2 is provided to prevent the dyes, which are obtained by dyeing the color filters FIL in different colors, from leaking to the liquid crystal LC. Color filter protective film PSV2
Is a thermosetting phenol novolac epoxy resin, for example. Further, the sealing material SL has a composition in which an inorganic filler such as alumina or silicon dioxide is added to a thermosetting phenol novolac epoxy resin which is the same constituent material as the protective film PSV2. In the liquid crystal display unit having such a configuration, the peeling of the sealing material SL did not occur during the manufacturing process. Further, when a temperature / humidity cycle test was carried out, no defects were found. As described above, the seal material SL and the protective film PS of the color filter, which are easily peeled off,
By making the constituent materials (components and molecular weights) of V2 substantially the same (including the same), the difference in thermal expansion and contraction at the interface between the seal material SL and the protective film PSV2 of the color filter is eliminated, and the adhesive strength is improved. Since it can be made larger, peeling of the sealing material SL can be suppressed. Therefore, a liquid crystal display device with high yield and high reliability can be provided.

(Thin Film Transistor TFT) The thin film transistor TFT operates so that when a positive bias is applied to the gate electrode GT, the channel resistance between the source and the drain becomes small, and when the bias is zero, the channel resistance becomes large.

The thin film transistor TFT of each pixel is divided into two (plural) in the pixel and is composed of thin film transistors (divided thin film transistors) TFT1 and TFT2. Each of the thin film transistors TFT1 and TFT2 has substantially the same size (channel length and channel width are the same). Each of the divided thin film transistors TFT1 and TFT2 mainly includes a gate electrode GT, a gate insulating film GI, and i-type amorphous silicon (S).
i-type semiconductor layer AS consisting of i), a pair of source electrodes SD
1 and the drain electrode SD2. It should be understood that the source and drain are originally determined by the bias polarity between them, and the polarity is inverted during operation in the circuit of this liquid crystal display device, so it should be understood that the source and drain are switched during operation. However, also in the following description, for convenience, one is fixed as the source and the other is fixed as the drain.

(Gate Electrode GT) The gate electrode GT is shown in FIG.
As shown in detail in (a plan view illustrating only the first conductive film g1, the second conductive film g2, and the i-type semiconductor layer AS in FIG. 2),
The scanning signal line GL is configured to project in the vertical direction (upward in FIGS. 2 and 5) (branched into a T shape). The gate electrode GT is configured to project to the respective formation regions of the thin film transistors TFT1 and TFT2. Thin film transistor TFT1, T
The respective gate electrodes GT of the FT2 are integrally configured (as a common gate electrode) and are formed continuously with the scanning signal line GL. The gate electrode GT is composed of the single-layer first conductive film g1 so as not to make a large step in the formation region of the thin film transistor TFT. The first conductive film g1 is, for example, a chromium (Cr) film formed by sputtering, and is formed to have a film thickness of about 1000 [Å].

As shown in FIGS. 2, 1 and 5, this gate electrode GT is formed larger than it so as to completely cover the i-type semiconductor layer AS (as viewed from below).
Therefore, when the backlight BL such as a fluorescent lamp is attached below the lower transparent glass substrate SUB1, the gate electrode GT made of opaque chrome becomes a shadow, and the i-type semiconductor layer AS is not exposed to the backlight light. The conduction phenomenon due to the light irradiation, that is, the deterioration of the off-characteristics of the thin film transistor TFT is less likely to occur. The original size of the gate electrode GT is the minimum required to extend between the source electrode SD1 and the drain electrode SD2 (including the alignment margin between the gate electrode GT, the source electrode SD1 and the drain electrode SD2). ) Has a width and its depth length that determines the channel width W is the ratio of the distance (channel length) L between the source electrode SD1 and the drain electrode SD2, that is, the factor W / L that determines the mutual conductance gm. It depends on what you do.

Gate electrode GT in this liquid crystal display device
Of course is made larger than the original size described above.

Note that the gate electrode GT and the scanning signal line GL may be integrally formed of a single layer, in which case the silicon is used as the opaque conductive material, in view of only the gate of the gate electrode GT and the function of shielding light. Containing aluminum (Al), pure aluminum, palladium (Pd)
It is possible to select aluminum or the like containing.

(Scanning Signal Line GL) The scanning signal line GL is the first
Conductive film g1 and second conductive film g2 provided on the conductive film g1
It is composed of a composite membrane. This scanning signal line GL
The first conductive film g1 is formed in the same manufacturing process as the first conductive film g1 of the gate electrode GT, and is integrally formed.
The second conductive film g2 is, for example, an aluminum film formed by sputtering, and is formed with a film thickness of about 1000 to 5500 [Å]. The second conductive film g2 is configured so that the resistance value of the scanning signal line GL can be reduced and the signal transmission speed can be increased (improvement of writing characteristics of pixel information).

Further, the scanning signal line GL is configured such that the width dimension of the second conductive film g2 is smaller than the width dimension of the first conductive film g1. That is, the scanning signal line GL has a gentle side wall step.

(Insulating Film GI) The insulating film GI is used as each gate insulating film of the thin film transistors TFT1 and TFT2. The insulating film GI is formed on the gate electrode GT and the scanning signal line GL. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is used,
It is formed with a film thickness of about 3000 [Å].

(I-type semiconductor layer AS) i-type semiconductor layer AS
Is used as a channel forming region of each of the thin film transistors TFT1 and TFT2 divided into a plurality of parts, as shown in FIG. The i-type semiconductor layer AS is formed of an amorphous silicon film or a polycrystalline silicon film and has a film thickness of about 1800 [Å].

This i-type semiconductor layer AS is continuously formed by the same plasma CVD apparatus and the same plasma as the formation of the insulating film GI used as a gate insulating film made of Si ₃ N ₄ by changing the composition of the supply gas. It is formed without being exposed to the outside from the CVD device. Further, the P-doped N (+) type semiconductor layer d0 (FIG. 1) for ohmic contact is also continuously formed to a thickness of about 400 [Å]. After that, the lower transparent glass substrate SUB1 is taken out from the CVD apparatus, and the N (+) type semiconductor layer d is formed by the photo processing technique.
The 0 and i-type semiconductor layers AS are patterned into independent islands as shown in FIGS. 1, 2 and 5.

As shown in detail in FIGS. 2 and 5, the i-type semiconductor layer AS is also provided between both the intersections (crossover portions) of the scanning signal lines GL and the video signal lines DL. The i-type semiconductor layer AS at the intersection is configured to reduce the short circuit between the scanning signal line GL and the video signal line DL at the intersection.

(Source electrode SD1, drain electrode SD
2) Thin film transistors TFT1, TF divided into a plurality of parts
Source electrode SD1 and drain electrode SD of T2
2 is separated from each other on the i-type semiconductor layer AS, as shown in detail in FIG. 1, FIG. 2 and FIG. 6 (plan views showing only the first to third conductive films d1 to d3 of FIG. 2). Are provided.

Each of the source electrode SD1 and the drain electrode SD2 is, from the lower layer side in contact with the N (+) type semiconductor layer d0, a first conductive film d1, a second conductive film d2, and a third conductive film d.
3 are sequentially stacked. Source electrode SD
The first conductive film d1, the second conductive film d2, and the third conductive film d3 are formed in the same manufacturing process as the first conductive film d1, the second conductive film d2, and the third conductive film d3 of the drain electrode SD2. ..

The first conductive film d1 is a chromium film formed by sputtering and is formed to have a film thickness of 500 to 1000 [Å] (about 600 [Å] in this liquid crystal display device). If the chrome film is made thicker, the stress will increase.
It is formed within a range not exceeding the film thickness of [Å]. The chromium film has good contact with the N (+) type semiconductor layer d0. In the chromium film, the aluminum of the second conductive film d2 described later is N (+).
A so-called barrier layer that prevents diffusion into the type semiconductor layer d0 is formed. As the first conductive film d1, a refractory metal (Mo, Ti, Ta, W) film, a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , W) other than the chromium film.
It may be formed of a Si ₂ ) film.

After patterning the first conductive film d1 by photographic processing, using the same photographic processing mask, or
The N (+) type semiconductor layer d0 is removed using the conductive film d1 as a mask. That is, in the N (+) type semiconductor layer d0 remaining on the i type semiconductor layer AS, the portion other than the first conductive film d1 is removed by self-alignment. At this time, since the N (+) type semiconductor layer d0 is etched so that the entire thickness thereof is removed, the i type semiconductor layer AS is also slightly etched on its surface portion, but the degree is controlled by the etching time. do it.

After that, the second conductive film d2 is formed by sputtering aluminum to a film thickness of 3000 to 5500 [Å] (in this liquid crystal display device, a film thickness of about 3500 [Å]). The aluminum film has less stress than the chromium film, can be formed to have a thick film thickness, and is configured to reduce the resistance values of the source electrode SD1, the drain electrode SD2, and the video signal line DL. The second conductive film d2 may be formed of an aluminum film containing silicon or copper (Cu) as an additive in addition to the aluminum film.

After patterning the second conductive film d2 by the photo processing technique, the third conductive film d3 is formed. The third conductive film d3 is a transparent conductive film (In
dium-Tin-Oxide ITO: Nesa film), 1000-20
It is formed with a film thickness of 00 [Å] (in this liquid crystal display device, a film thickness of about 1200 [Å]). The third conductive film d3 constitutes the source electrode SD1, the drain electrode SD2 and the video signal line DL, and also constitutes the transparent pixel electrode ITO1.

The first conductive film d1 of the source electrode SD1 and the first conductive film d1 of the drain electrode SD2 are inside (in the channel region) of the second conductive film d2 and the third conductive film d3 which are upper layers. It is very involved. That is,
The first conductive film d1 in these portions is the second conductive film d.
2, regardless of the third conductive film d3, the thin film transistor TF
It is configured so that the channel length L of T can be defined.

The source electrode SD1 is the transparent pixel electrode ITO1.
It is connected to the. The source electrode SD1 corresponds to the step shape of the i-type semiconductor layer AS (the film thickness of the first conductive film g1, the film thickness of the N (+)-type semiconductor layer d0, and the film thickness of the i-type semiconductor layer AS are added. It is configured along a step. Specifically, the source electrode SD1 includes a first conductive film d1 formed along the step shape of the i-type semiconductor layer AS, and the first conductive film d1.
The transparent pixel electrode ITO1 is formed above the conductive film d1.
The second conductive film d having a small size on the side connected to
2 and the first conductive film d1 exposed from the second conductive film d2
And a third conductive film d3 connected to. The second conductive film d2 of the source electrode SD1 cannot be formed thick because the chromium film of the first conductive film d1 cannot be formed due to the increased stress, and cannot overcome the step shape of the i-type semiconductor layer AS. Is configured for. That is, the second conductive film d2 is formed thick to improve step coverage. Since the second conductive film d2 can be formed thick, the resistance value of the source electrode SD1 (the drain electrode SD
2 and the video signal line DL are also the same). Since the third conductive film d3 cannot overcome the stepped shape of the second conductive film d2 due to the i-type semiconductor layer AS, the size of the second conductive film d2 is reduced, so that the exposed first conductive film d1 is not exposed. Is configured to connect. The first conductive film d1 and the third conductive film d3 not only have good adhesiveness, but also the step shape of the connecting portion between them is small, so that the source electrode SD1 and the transparent pixel electrode ITO1 can be reliably connected. it can.

The source electrode SD1 is the transparent pixel electrode ITO1.
It is connected to the. The source electrode SD1 corresponds to the step shape of the i-type semiconductor layer AS (the film thickness of the first conductive film g1, the film thickness of the N (+)-type semiconductor layer d0, and the film thickness of the i-type semiconductor layer AS are added. It is configured along a step. Specifically, the source electrode SD1 includes a first conductive film d1 formed along the step shape of the i-type semiconductor layer AS, and the first conductive film d1.
The transparent pixel electrode ITO1 is formed above the conductive film d1.
The second conductive film d having a small size on the side connected to
2 and the first conductive film d1 exposed from the second conductive film d2
And a third conductive film d3 connected to. The second conductive film d2 of the source electrode SD1 cannot be formed thick because the chromium film of the first conductive film d1 cannot be formed due to the increased stress, and cannot overcome the step shape of the i-type semiconductor layer AS. Is configured for. That is, the second conductive film d2 is formed thick to improve step coverage. Since the second conductive film d2 can be formed thick, the resistance value of the source electrode SD1 (the drain electrode SD
2 and the video signal line DL are also the same). Since the third conductive film d3 cannot overcome the stepped shape of the second conductive film d2 due to the i-type semiconductor layer AS, the size of the second conductive film d2 is reduced, so that the exposed first conductive film d1 is not exposed. Is configured to connect. The first conductive film d1 and the third conductive film d3 not only have good adhesiveness, but also the step shape of the connecting portion between them is small, so that the source electrode SD1 and the transparent pixel electrode ITO1 can be reliably connected. it can.

(Transparent pixel electrode ITO1) Transparent pixel electrode I
TO1 constitutes one of the pixel electrodes of the liquid crystal display section.

The transparent pixel electrode ITO1 is the source electrode SD1 of the thin film transistor TFT1 and the thin film transistor T.
It is connected to the source electrode SD1 of FT2. Therefore, when a defect occurs in one of the thin film transistors TFT1 and TFT2, for example, the thin film transistor TFT1, the thin film transistor TFT1 and the video signal line DL are separated from each other by a laser beam or the like in the manufacturing process, and the thin film transistor TFT1 and the transparent pixel electrode ITO1 are separated.
If and are separated, point defects and line defects do not occur, and
Since the two thin film transistors TFT1 and TFT2 rarely have defects at the same time, the probability of point defects occurring can be made extremely small.

(Protective film PSV1) Thin film transistor TF
A protective film PSV1 is provided on the T and the transparent pixel electrode ITO1. The protective film PSV1 is formed mainly for protecting the thin film transistor TFT from moisture and the like,
Use one with high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD device.
It is formed with a film thickness of about [Å].

(Equivalent Circuit of Entire Display) FIG. 9 shows a connection diagram of the equivalent circuit of the display matrix portion and its peripheral circuits. Although the figure is a circuit diagram, it is drawn corresponding to the actual geometrical arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X means a video signal line DL, and subscripts G, B and R are added corresponding to green, blue and red pixels, respectively. Y represents the scanning signal line GL, and subscripts 1, 2, 3, ..., End are added according to the order of scanning timing.

The video signal lines X (subscripts omitted) are alternately connected to the upper (or odd) video signal drive circuit He and the lower (or even) video signal drive circuit Ho.

The SUP is a TFT liquid crystal display device for displaying information for a CRT (cathode ray tube) from a power supply circuit or a host (upper processing unit) for obtaining a stabilized voltage source obtained by dividing a plurality of voltages from one voltage source. It is a circuit including a circuit for exchanging information for use.

(Structure of Storage Capacitance Element Cadd) The transparent pixel electrode ITO1 is formed so as to overlap the adjacent scanning signal line GL at the end opposite to the end connected to the thin film transistor TFT. In this superposition, as is clear from FIG. 3, the transparent pixel electrode ITO1 is used as one electrode PL2 and the adjacent scanning signal line GL is used as the other electrode PL.
A holding capacitance element (electrostatic capacitance element) Cadd which is 1 is configured. The dielectric film of the storage capacitor Cadd is an insulating film G used as a gate insulating film of the thin film transistor TFT.
It is composed of the same layer as I.

As is apparent from FIG. 5, the storage capacitor element Cadd is formed in a portion where the width of the first conductive film g1 of the scanning signal line GL is widened. The portion of the first conductive film g1 that intersects the video signal line DL is thinned to reduce the probability of short circuit with the video signal line DL.

Similar to the source electrode SD1, the transparent pixel electrode ITO1 is broken at a portion between the transparent pixel electrode ITO1 and the electrode PL1 which are overlapped to form the storage capacitor element Cadd when the stepped shape is overcome. So as not to,
An island region including the first conductive film d1 and the second conductive film d2 is provided. This island region is a transparent pixel electrode IT
The area of O1 (aperture ratio) is made as small as possible so as not to decrease.

(Equivalent Circuit of Retaining Capacitance Element Cadd and Its Operation) FIG. 10 shows an equivalent circuit of the pixel shown in FIG. In FIG. 10, Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SD1 of the thin film transistor TFT. The dielectric film having the parasitic capacitance Cgs is the insulating film GI. Cpix is a liquid crystal capacitance formed between the transparent pixel electrode ITO1 (PIX) and the common transparent pixel electrode ITO2 (COM). The dielectric film of the liquid crystal capacitance Cpix is the liquid crystal LC, the protective film PSV1, and the alignment films ORI1 and ORI2.
Vlc is the midpoint potential.

The storage capacitor element Cadd functions to reduce the influence of the gate potential change ΔVg on the midpoint potential (pixel electrode potential) Vlc when the thin film transistor TFT switches. This can be expressed by the following equation.

ΔVlc = {Cgs / (Cgs + Cadd + Cpix)} × ΔVg Here, ΔVlc represents the change amount of the midpoint potential due to ΔVg. The variation ΔVlc causes a direct current component applied to the liquid crystal LC, and the value can be reduced as the holding capacitance Cadd is increased. In addition, the storage capacitor element C
add also has the effect of lengthening the discharge time, and accumulates image information for a long time after the thin film transistor TFT is turned off. The reduction of the DC component applied to the liquid crystal LC can improve the life of the liquid crystal LC and reduce so-called burn-in in which the previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large enough to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 is increased, and thus the parasitic capacitance Cgs is increased. The midpoint potential Vlc has the adverse effect of being easily influenced by the gate (scanning) signal Vg. However, the storage capacitor Cadd
By providing the above, this demerit can be eliminated.

The storage capacitance of the storage capacitor Cadd is 4 to 8 times (4.times.) The liquid crystal capacitance Cpix due to the writing characteristics of the pixel.
Cpix <Cadd <8 · Cpix), 8 to parasitic capacitance Cgs
Set to a value about 32 times (8 · Cgs <Cadd <32 · Cgs).

(Method of connecting the storage capacitor element Cadd electrode wire)
The first-stage scanning signal line GL (Y ₀ ) used only as the storage capacitor electrode line is connected to the common transparent pixel electrode ITO2 (Vcom) as shown in FIG. Common transparent pixel electrode IT
As shown in FIG. 1, O2 is connected to the external lead wiring by the silver paste material SL at the peripheral portion of the liquid crystal display device. Moreover, a part of the conductive film (g
1 and g2) are formed in the same manufacturing process as the scanning signal line GL. As a result, the storage capacitor electrode line GL at the final stage
Can be easily connected to the common transparent pixel electrode ITO2.

The storage capacitor electrode line Y ₀ in the first stage is connected to the scanning signal line Yend in the final stage, is connected to a DC potential point (AC ground point) other than Vcom, or an extra scanning pulse Y is added from the vertical path circuit V. You may connect to receive ₀ .

As described above, the invention made by the present inventor is
Although the specific description has been given based on the above-mentioned embodiment, the present invention is not limited to the above-mentioned embodiment, and needless to say, various modifications can be made without departing from the scope of the invention.

For example, although the active matrix type liquid crystal display device has been described in the above embodiment, it goes without saying that the present invention can also be applied to a simple matrix type liquid crystal display device.

Although the thermosetting phenol novolac epoxy resin is used as the material for the seal material SL and the protective film PSV2, other materials may be used.

Further, in the above-mentioned embodiment, the inverted staggered structure of gate electrode formation → gate insulating film formation → semiconductor layer formation → source / drain electrode formation is shown, but a staggered structure having a vertical relationship or a manufacturing order opposite thereto is also possible. The present invention is effective.

[0075]

As described above, in the liquid crystal display device of the present invention, peeling of the sealing material can be suppressed by making the constituent materials of the sealing material and the protective film of the color filter substantially the same. As a result, a liquid crystal display device with high yield and high reliability can be provided.

[Brief description of drawings]

FIG. 1 is a schematic diagram of a TFT part (:
FIG. 3 is a cross-sectional view taken along line 1-1 of FIG. 2) and a seal portion.

FIG. 2 is a main part plan view showing one pixel of a liquid crystal display portion of an active matrix type color liquid crystal display device to which the present invention is applied.

3 is a cross-sectional view taken along the line 3-3 in FIG.

4 is a plan view of a main part of a liquid crystal display unit in which a plurality of pixels shown in FIG. 2 are arranged.

5 is a plan view showing only a predetermined layer of the pixel shown in FIG.

FIG. 6 is a plan view illustrating only a predetermined layer of the pixel shown in FIG.

FIG. 7 is a plan view illustrating only a predetermined layer of the pixel shown in FIG.

FIG. 8 is a plan view of relevant parts showing only the pixel electrode layer, the light-shielding film, and the color filter layer shown in FIG.

FIG. 9 is an equivalent circuit diagram showing a liquid crystal display portion of an active matrix type color liquid crystal display device.

FIG. 10 is an equivalent circuit diagram of the pixel shown in FIG.

[Explanation of symbols]

SUB1 ... Lower transparent glass substrate, ITO1 ... Transparent pixel electrode, ORI1 ... Lower alignment film, LC ... Liquid crystal, SUB2 ... Upper transparent glass substrate, FIL ... Color filter, PSV2
... Color filter protective film, ITO2 ... Common transparent pixel electrode, ORI2 ... Upper alignment film, SL ... Seal part.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenichi Shimada, 3681 Hayano, Mobara, Chiba Prefecture, Hitachi Device Engineering Co., Ltd. (72) Inventor, Shigeru Matsuyama, 3300, Hayano, Mobara, Chiba, Hitachi Ltd. ) Inventor Aoki Aoki 3300 Hayano, Mobara-shi, Chiba Hitachi Ltd. Mobara factory

Claims (1)

Claim: What is claimed is: 1. A first transparent substrate having a first transparent pixel electrode and a first alignment film, a color filter, a protective film for the color filter, and a second transparent pixel electrode. , A second transparent substrate having a second alignment film formed thereon is superposed at a predetermined interval such that the alignment films face each other, and a sealing material is provided around the edge between the two substrates. In a liquid crystal display device in which the both substrates are adhered and liquid crystal is sealed between the both substrates, a constituent material of the sealing material and the protective film of the color filter is substantially the same.