JPH0521614A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the efficiency of a semiconductor device by bringing the contact resistance value of each element within a fixed value. CONSTITUTION:In the semiconductor manufacturing method wherein a semiconductor substrate 10 and a wiring layer are brought into contact with each other through the intermediary of the aperture part of an insulating film 103, an amorphous silicon film 106 is formed on the aperture part of the insulating film 103 formed on the semiconductor substrate 101, then, a natural oxide film 102 is reduced in an amorphous silicon film 106 by conducting a heat treatment, and the natural oxide film 102 is removed.

Description

Detailed Description of the Invention

[Object of the Invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art A method of manufacturing a semiconductor device in which a semiconductor substrate and a polycrystalline silicon wiring layer are brought into contact with each other through an opening in an insulating film,

First, after forming the insulating film 203 on the semiconductor substrate 201, the insulating film 203 is patterned to open a predetermined portion of the insulating film 203, and thereafter, the ion is formed from the opening of the insulating film 203. Impurities such as arsenic As 204
Is introduced to reach FIG. 11. Here, as shown in FIG. 12, the impurity diffusion layer 205 is formed. Subsequently, a step of reducing the amount of oxygen taken into the low pressure CVD apparatus and thinly forming the polycrystalline silicon film 206 on the insulating film 203 and the impurity diffusion layer 205 of the exposed semiconductor substrate 201 is used, as shown in FIG. Leading to. Here, the natural oxide film 202 is formed as shown in FIG. 12 before the polycrystalline silicon film 206 is formed. In particular, there is a chemical property that the natural oxide film 202 grows more easily on the N-type impurity diffusion layer than on the P-type impurity diffusion layer. Therefore, as shown in FIG. 14, for example, arsenic As207 of the same type as the impurity 204 taken in the impurity diffusion layer 205 is implanted into the impurity diffusion layer 205 of the semiconductor substrate 201 by the ion implantation method to form the natural oxide film 202. A step of removing is used. Subsequently, a step of forming a polycrystalline silicon film 208 by the low pressure CVD method and introducing impurities into the polycrystalline silicon film 208 by thermal diffusion or an ion implantation method to lower the resistance value of the wiring layer is used. 15 is reached. Next, after forming a passivation film 210 such as a PSG film on the polycrystalline silicon film 209, the passivation film 21 is selectively formed.
0 is etched to form a contact hole, an aluminum-silicon film 211 is formed, and the aluminum-silicon film 211 is patterned to form an electrode,
16 is reached.

However, by reducing the amount of oxygen taken into the low pressure CVD apparatus, the formation of a natural oxide film is suppressed, and after the polycrystalline silicon film is thinly formed,
Although the same type of impurities as those taken into the impurity diffusion layer is implanted into the impurity diffusion layer by the ion implantation method to destroy the natural oxide film, the natural oxide film cannot be completely removed. In addition, since it is necessary to consider the extent of the diffusion of the impurity diffusion layer into the semiconductor substrate, there is a great problem as a method for removing the natural oxide film.

[0005]

As described above, the formation of the natural oxide film naturally increases the contact resistance value between the impurity diffusion layer in the semiconductor substrate and the polycrystalline silicon film used as the wiring layer. In addition, since the thickness of the native oxide film is not uniform among the semiconductor elements in the semiconductor substrate, the contact resistance value is not constant and the performance of the semiconductor device is significantly reduced. [Constitution of Invention]

[0006]

According to the present invention, an insulating film is first formed on a semiconductor substrate, an opening portion is formed by patterning this insulating film, and then impurities are introduced from the opening portion. After performing the step of forming the impurity diffusion layer in the semiconductor substrate, an amorphous silicon film is formed on the insulating film and in the openings of the insulating film, and the natural oxide film is reduced to the amorphous silicon film during the heat treatment step. , A step of recrystallizing the amorphous silicon film to form a polycrystalline silicon film, and a step of etching the polycrystalline silicon film using a CDE method.

[0007]

Function: An amorphous silicon film is formed on the natural oxide film formed on the impurity diffusion layer of the semiconductor substrate, and a heat treatment process is performed. Here, the amorphous silicon film and the natural oxide film which are in contact with each other act. That is, the silicon in the natural oxide film exists in the state of the amorphous silicon film linked with the amorphous silicon film, and the oxygen is separated. From this state, the amorphous silicon film is recrystallized into polycrystalline silicon because it is undergoing a heat treatment process. After that, if the entire silicon film is etched by the CDE method, the natural oxide film will be removed. Thus, the present invention solves the problems in the prior art and improves the performance of semiconductor devices.

[0008]

Embodiments of the present invention will be described with reference to FIGS.

First, an insulating film 103 having a thickness of 1000 angstrom is formed on the surface of a semiconductor substrate 101 by thermal oxidation.
At this point, during the thermal oxidation process, the semiconductor substrate 101 and the insulating film 10 are
There is a native oxide film 102 of about 20 angstrom formed between 3 and 3. After that, patterning is performed using a lithography technique to open a part of the insulating film 103 to expose the semiconductor substrate 101, and the insulating film 103 left unremoved is used as a mask. Using the ion implantation method from the hole portion into the semiconductor substrate 101, As
To 5 × 10 ¹⁵ / cm ³ Introduced to some extent and led to Figure 1.

Here, as shown in FIG. 2, the N-type impurity diffusion layer 105 is formed. Then, using a low pressure CVD apparatus, the silane gas is thermally decomposed under the conditions of a reaction temperature of 510 ° C. and a reaction pressure of 0.5 Torr to form an amorphous silicon film.
106 is formed on the insulating film 103 and on the newly formed natural oxide film 102 in the low pressure CVD apparatus, which leads to FIG. Subsequently, following this step, the amorphous silicon film 106 formed in the previous step is subjected to N ₂ at 800 ° C. in the same CVD apparatus.
Heat treatment is performed for about 40 minutes in a hot atmosphere (here, the amorphous silicon film 106 is recrystallized into a polycrystalline silicon film 107 during the heat treatment step). After that, the polycrystalline silicon film 107 is continuously removed by chlorine trifluoride gas (ClF ₃ ) 108 in the same CVD apparatus as shown in FIG. Here, if the removal of the natural oxide film 102 is insufficient, this step is repeated.

Next, the reaction temperature is set in the same CVD apparatus.
Silane gas is thermally decomposed at 510 ° C. and a reaction pressure of 0.5 Torr to form an amorphous silicon film 109 again on the insulating film 102 and the semiconductor substrate 101. After that, as shown in FIG. Phosphorus P as 110
5 × 10 ²⁰ ~ ²¹ / cm ³ And the amorphous silicon film 109 is recrystallized into the polycrystalline silicon film 111 by performing the heat treatment in the N ₂ atmosphere at 900 ° C. for about 40 to 60 minutes. The phosphorus P, which is the impurity 110 introduced by using it, is activated, and the result is shown in FIG. Here, the impurities 110 introduced by the ion implantation method are used.
The resistance value of the polycrystalline silicon film 111 can be lowered by activating phosphorus P which is

Next, after forming a passivation film 112 such as a PSG film on the polycrystalline silicon film 111, selectively,
The passivation film 112 is etched to form a contact hole, an aluminum-silicon film 113 is formed, and the aluminum-silicon film 113 is patterned to form an electrode, as shown in FIG. The results of using the embodiments of the present invention will be described below while comparing the embodiments of the present invention with the prior art.

A semiconductor device manufactured according to an embodiment;
FIG. 9 shows an electrically evaluated contact resistance between a semiconductor substrate and a polycrystalline silicon film in a semiconductor device manufactured by a conventional technique, and a transmission electron microscope is used to show a cross section of the impurity diffusion layer and the polycrystalline silicon film. FIG. 10 shows the result of in-plane calculation of the thickness of the natural oxide film formed on the boundary surface.

As shown in FIG. 9, the result of the embodiment of the present invention is that the contact resistance value between the wafer-shaped semiconductor substrate and the polycrystalline silicon film is kept within a substantially constant value, which is much smaller than that of the prior art. Stable to. Further, as shown in FIG. 10, the thickness of the natural oxide film at the boundary surface between the semiconductor substrate and the polycrystalline silicon film is almost 0, which means that the natural oxide film is almost completely removed. As a result, the contact resistance value between the semiconductor conductor substrate and the polycrystalline silicon film of the natural oxide film is much suppressed as compared with the conventional technique, and the comparison result of the contact resistance value of each element is within a substantially constant value. The electric characteristics of the semiconductor device are improved without adversely affecting the impurity diffusion layer.

Further, the effect of a series of steps for removing the natural oxide film and forming the wiring layer in this embodiment will be described. In order to remove the amorphous silicon and the polycrystalline silicon film deposited in the low pressure CVD apparatus. The process of forming an amorphous silicon film by using chlorine trifluoride gas (ClF ₃ ) used for the above, performing a heat treatment to remove the natural oxide film, and further forming an amorphous silicon film is performed by the same low pressure CVD apparatus. Could be done within. Therefore, in the conventional technique, the step of forming the polycrystalline silicon film, the step of removing the natural oxide film by the ion implantation method, and the step of further forming the polycrystalline silicon film were performed in separate devices. The manufacturing process can be simplified by continuously performing the process in the same low pressure CVD apparatus as in the embodiment of the invention.

In this embodiment, the impurity diffusion layer is N-type. As described in the prior art, considering the chemical nature that a natural oxide film is more easily formed when the impurity diffusion layer is the N type than when the impurity diffusion layer is the P type,
It is obvious that the same effect can be obtained even when the impurity diffusion layer is P-type. Further, although the amorphous silicon film is formed by using silane (SiH ₄ ), the same result can be obtained by using other gas such as disilane (Si ₂ H ₆ ). Further, in this embodiment, the heat treatment is performed at 800 ° C. in the same CVD apparatus when forming the amorphous silicon film, but the same result can be obtained by performing the heat treatment at a temperature in the range of 630 ° C. to 800 ° C. Obtainable.

[0017]

According to the present invention, the performance of the semiconductor device can be improved by removing the natural oxide film and keeping the contact resistance value of each element within a certain value.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor device in an example.

FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor device in an example.

FIG. 3 is a cross-sectional view showing a manufacturing process of a semiconductor device in an example.

FIG. 4 is a cross-sectional view showing a manufacturing process of a semiconductor device in an example.

FIG. 5 is a cross-sectional view showing a manufacturing process of a semiconductor device in an example.

FIG. 6 is a cross-sectional view showing a manufacturing process of a semiconductor device in an example.

FIG. 7 is a cross-sectional view showing a manufacturing process of a semiconductor device in an example.

FIG. 8 is a cross-sectional view showing a manufacturing process of a semiconductor device in an example.

FIG. 9 is a diagram showing a result of a manufacturing process of a semiconductor device in an example.

FIG. 10 is a diagram showing the result of the manufacturing process of the semiconductor device in the example.

FIG. 11 is a cross-sectional view showing a manufacturing process of a semiconductor device in a conventional technique.

FIG. 12 is a cross-sectional view showing a manufacturing process of a semiconductor device in a conventional technique.

FIG. 13 is a cross-sectional view showing a manufacturing process of a semiconductor device in a conventional technique.

FIG. 14 is a cross-sectional view showing a manufacturing process of a semiconductor device in the related art.

FIG. 15 is a cross-sectional view showing a manufacturing process of a semiconductor device in the related art.

FIG. 16 is a cross-sectional view showing a manufacturing process of a semiconductor device in the related art.

[Explanation of symbols]

102,202 …… Natural oxide film, 103,203 …… Insulating film, 104,204 ...... impurities, 105,205 ・ ・ ・ Impurity diffusion layer, 106 …… Amorphous silicon film, 107,209 ・ ・ ・ Polycrystalline silicon film, 108 …… Chlorine trifluoride gas, 207 ...... Arsenic As, 109,208 …… Amorphous silicon film, 110 …… impurities, 111,206 ・ ・ ・ Polycrystalline silicon film after impurity introduction, 112,210 ...... Passivation film, 113,211 ...... Aluminum-silicon film.

Claims (4)

[Claims] 1. A method for manufacturing a semiconductor in which a semiconductor substrate and a wiring layer are brought into contact with each other through an opening in an insulating film, the method comprising: forming an insulating film on the semiconductor substrate; and patterning the insulating film. A step of forming an opening, a step of forming an amorphous silicon film in the opening, a step of heat-treating the amorphous silicon film to recrystallize it into polycrystalline silicon, and And a step of etching using a method, and a method for manufacturing a semiconductor device, comprising: 2. The method of manufacturing a semiconductor device according to claim 1, wherein chlorine trifluoride gas (ClF ₃ ) is used in the CDE method. 3. The same CVD apparatus includes a step of forming an amorphous silicon film in the opening, a step of applying a heat treatment to the amorphous silicon film, and a step of etching the polycrystalline silicon using the CDE method. The method of manufacturing a semiconductor device according to claim 1, wherein 4. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of implanting an impurity into the semiconductor substrate through an opening of the insulating film to form an impurity diffusion layer. .