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JPH0521538A - Film carrier device - Google Patents

Film carrier device

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Publication number
JPH0521538A
JPH0521538A JP17660191A JP17660191A JPH0521538A JP H0521538 A JPH0521538 A JP H0521538A JP 17660191 A JP17660191 A JP 17660191A JP 17660191 A JP17660191 A JP 17660191A JP H0521538 A JPH0521538 A JP H0521538A
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JP
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Prior art keywords
via
layer
solder
hole
operation
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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JP17660191A
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Japanese (ja)
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JP2757594B2 (en )
Inventor
Yoshihiro Nakada
Mamoru Onda
Masaharu Takagi
Hiroki Tanaka
Kenji Yamaguchi
田 義 弘 仲
口 健 司 山
田 護 御
中 浩 樹 田
城 正 治 高
Original Assignee
Hitachi Cable Ltd
日立電線株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections or via connections

Abstract

PURPOSE:To simplify the working operation of the title device and to increase the reliability of an electric connection via a via hole by a method wherein the via hole is filled substantially with a solder by heating and melting a solder ball or a solder wire. CONSTITUTION:A copper-foil sheet 1 is pasted; by using an epoxy-based adhesive 27 on an insulating layer (a polyimide) 3 in which a via hole has been formed. Then, a solder (80% Sn-20% Pb alloy) wire is inserted into the via hole; it is cut; after that it is heated at about 210 deg.C. Then, a copper layer 11 is formed by a vacuum evaporation method, on the surface of the insulating layer 3 and a solder layer 10; after that, a resist-coating operation, a patterning operation and the etching operation of the copper layer are executed; the two-layer structure of a fine interconnection is formed. Thereby, a solder ball or the solder wire is filled into the via hole. Thereby, since a first conductive layer can be connected to a second conductive layer via the via hole, the reliability of the title device against a thermal stress is enhanced.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明はバイアホールを有するフィルムキャリア装置に関する。 The present invention relates to a film carrier device having a via hole.

【0002】 [0002]

【従来の技術】最近ICの薄型高密度実装化に対応して、ICチップをフィルムキャリアに取り付けて実装するTAB(テープキャリア方式)が用いられている。 Corresponding to the ART thin high density mounting of the recent IC, TAB implementing attach the IC chip on the film carrier (tape carrier method) is used. このようなTABにおいては、例えばポリイミドフィルムなどの絶縁層の上面に信号層、下面に電源層を有しているが、下面の電源層から配線をとるためなどの目的でバイアホールが設けられる。 In such TAB, for example, a signal layer on the upper surface of the insulating layer such as a polyimide film, has the power layer to the lower surface, via holes are provided for the purpose of for taking the wiring from the lower surface of the power supply layer.

【0003】フィルムキャリア装置に形成されたバイアホールを接続する手段として、従来例えば図5に示すようにスパッタ法で銅をコートして銅膜層5を形成する方法がある。 As a means for connecting the film via holes formed in the carrier device, there is a method of forming a copper film layer 5 by coating the copper by sputtering as shown in the conventional example, FIG. 5. すなわち例えば厚さ25μmの銅箔1、厚さ75μmの絶縁層3に形成されたバイアホール4をスパッタ法による厚さ4μmの銅膜層5により接続している。 Thus, for example having a thickness of 25μm copper foil 1, it is connected by a copper film layer 5 having a thickness of 4μm by sputtering via holes 4 formed in the insulating layer 3 having a thickness of 75 [mu] m. また、図6には例えば厚さ75μmのポリイミド絶縁層3の両面に厚さ25μmの銅箔1、7をエポキシ系接着剤2、6により張り合わせた後、径0.2〜0.6 Further, after laminating the copper foil 1,7 thick 25μm by epoxy adhesive 2 and 6 on both sides of the polyimide insulating layer 3 having a thickness of 75μm, for example, in FIG. 6, diameter 0.2 to 0.6
mmのスルーホール8を形成したものであるが、その接続法として、銅の電気めっき法や無電解めっき法によりめっき層9を形成したものである。 It is obtained by forming a mm of the through hole 8, but as a connection method, is obtained by forming a plating layer 9 by electroplating or electroless plating of copper. いずれの方法も、バイアホールを形成する壁面を介して電気的に接続するものである。 Either method is intended to electrically connect via a wall surface forming the via hole.

【0004】前記スパッタ法による接続では、ポリイミド絶縁層が発熱し、熱変形するうえ、用いるポリイミドの種類(例えば商品名カプトンH、ユーピレックスS [0004] In the connection by the sputtering method, the polyimide insulating layer is heated, after which the thermal deformation, the type of polyimide used (e.g. trade name Kapton H, Upilex S
等)によっては、形成される銅膜層の密着力が30g/ Depending etc.), adhesion of the copper film layer to be formed is 30 g /
cm以下と弱く、密着力向上のためにはスパッタの後、 cm or less and weaker, after sputtering for adhesion improvement,
特殊なプラズマ処理が必要であった。 Special plasma treatment was required. まためっき法は、 The plating method,
一般に密着力が良いものの、やはり用いるポリイミドの種類(例えば商品名カプトンD、ユーピレックスS等) Although generally the adhesion is good, also used the type of polyimide (for example, under the trade name Kapton D, Upilex S, etc.)
によってはめっきの密着性が悪く、熱ストレスに対する信頼性に乏しいという問題がある。 Poor adhesion of the plating by a problem of poor reliability against thermal stress. さらに銅の電気めっきでは5〜10分、無電解めっきでは1〜2時間とめっきに時間がかかること、湿式で行なわれるためイオン性物質がバイアホールや層間に残留して、マイグレーションや配線腐食原因となることなどの問題もある。 Furthermore 5-10 minutes in the electroplating of copper, that the time to the plating and 1-2 hours in the electroless plating is applied, ionic substances because they are performed in wet is remaining in the via holes and the interlayer, migration and wiring corrosion caused there is also a problem, such as to become.

【0005】 [0005]

【発明が解決しようとする課題】フィルムキャリア装置の絶縁層の両面に有する導電層間をバイアホールを介して電気的に接続する上記従来技術の課題に鑑み、信頼性が高く、容易に接続できる方法が求められていた。 In view of the above prior art problems to be electrically connected through a via hole conductive layers having on both sides of the insulating layer THE INVENTION to be solved INVENTION film carrier device, reliable method that can be easily connected It has been demanded. 本発明は、このような要望に応えるものである。 The present invention addresses this demand.

【0006】本発明は導電層間の電気的接続を半田ボール等の溶融によるバイアホールの埋め込みを行なった後、例えば蒸着法などにより他の導電層を形成することにより実現するものであり、加工作業が極めて簡単で、 The present invention after performing embedding of the via-hole electrical connections between the conductive layers due to melting of the solder balls or the like, which realizes by forming another conductive layer by a vapor deposition method for example, processing operations There is very simple,
バイアホールを介しての電気的接続の信頼性の高いフィルムキャリア装置を提供するものである。 There is provided a high film carrier device reliable electrical connection through a via hole.

【0007】 [0007]

【課題を解決するための手段】上記目的を達成するために本発明によれば、絶縁層の両面に第1および第2導電層を有し、これらの導電層間がバイアホールを介して電気的に接続されてなるフィルムキャリア装置であって、 Means for Solving the Problems] According to the present invention in order to achieve the above object, comprises a first and a second conductive layer on both surfaces of the insulating layer, electrically these conducting layers through the via hole a film carrier device which are connected to,
バイアホールは半田ボールまたは半田線の加熱溶解によって半田により実質的に充填されていることを特徴とするフィルムキャリア装置が提供される。 Via hole is a film carrier device which is characterized by being substantially filled with solder by heating and melting the solder balls or solder lines are provided. 以下図面に基づき、本発明をさらに詳細に説明する。 The following reference to the drawings, a more detailed explanation of the present invention.

【0008】本発明において第1導電シート層としては銅箔シート、銅合金(Cu−Zr,Cu−Sn合金)箔シート、42系合金(Fe−42%Ni合金、Fe−4 [0008] As the first conductive sheet layer copper foil sheet in the present invention, a copper alloy (Cu-Zr, Cu-Sn alloy) foil sheet, 42 alloy (Fe-42% Ni alloy, Fe-4
2%Ni−3%Co合金)箔シートなどが挙げられる。 Such as 2% Ni-3% Co alloy) foil sheets.
第1導電シート層の厚さは通常4〜35μmである。 The thickness of the first conductive sheet layer is usually 4~35Myuemu. また、絶縁層3は商品名カプトンD、カプトンH、ユーピレックスSなどで知られるポリイミドフィルム、ガラスエポキシ、BTレジンポリエステルフィルム等が挙げられるが、通常ポリイミドフィルムが好んで用いられる。 The insulating layer 3 is the trade name Kapton D, Kapton H, polyimide film known for Upilex S, glass epoxy, and BT resin polyester film and the like, is preferably used is typically a polyimide film.
絶縁層の厚さは通常25〜150μmである。 The thickness of the insulating layer is usually 25 to 150.

【0009】バイアホールは、通常絶縁層にフォトレジスト層を形成し、それをマスクとしてヒドラジン等の液中でフィルムシートの一部の領域をエッチングすることにより形成することができる。 [0009] via holes, the normally insulating layer to form a photoresist layer, it can be formed by etching a part of the area of ​​the film sheet in a liquid such as hydrazine as a mask. バイアホールの直径は通常0.05mmから0.6mmの範囲にあることが好ましい。 The diameter of the via hole is preferably in the normal 0.05mm in the range of 0.6 mm. その理由としては、多層配線でしかも配線ピッチが140μmと狭くなる傾向にあるので0.6mmを越えるスペースを確保するのが困難である。 The reason is that it is difficult to even wiring pitch only in multi-layer wiring to secure a space in excess of 0.6mm because the narrow trend and 140 .mu.m. また直径が0.05mmよりも小さくなると本発明で使用する半田ボールや半田線の挿入が実際上困難となる。 The insertion of the solder balls or solder wire to be used in the present invention if the diameter is smaller than 0.05mm is difficult in practice.

【0010】本発明におけるバイアホール内の埋め込みは、例えば図1に示すように半田ボール若しくは半田線を加熱溶融して絶縁層の上面高さ付近まで半田10により埋め込む。 [0010] embedding the via hole in the present invention, for example, solder balls or solder wire, as shown in FIG. 1 heated and melted to embed the solder 10 to the vicinity of the upper surface height of the insulating layer. 半田の埋め込み高さは絶縁層の上面高さになるべく合わせることが好ましい。 Embedding height of the solder is preferably matched as possible to the upper surface height of the insulating layer. 半田の組成としてはSnが通常100〜5%の範囲にあるものが好んで使用される。 The composition of the solder used prefer those in the range Sn is usually from 100 to 5%. 半田ボールは常法により通常直径35〜400 Solder balls are usually diameter by a conventional method 35-400
μmの半田線(ワイヤ)を加熱して製造する。 Prepared by heating μm solder wire (wire). 半田線はバイアホールに挿入し長さ55〜700μmに切断する。 The solder wire is cut to a length 55~700μm inserted into the via hole.

【0011】図7に半田ボールの埋め込み工程(装置) [0011] of the solder ball in Figure 7 embedding process (apparatus)
の一例を示した。 It shows an example of. キャピラリー22の孔に通した半田ワイヤ23の先端を、ライン26からのAr+10%H2 The tip of the solder wire 23 through the bore of the capillary 22, from line 26 Ar + 10% H2
等の雰囲気中でアーク放電により熔解し、ボール24を形成する。 It was melted by arc discharge in an atmosphere of equal to form a ball 24. この時ボールの径はワイヤーの3倍の径迄作ることができるのでバイアホールに1回の埋め込みで完全に充填する事ができる。 The diameter of the time the ball can be completely filled with the embedding of once a via hole since it is possible to make three times the 径迄 of wire. ボールのバイアホールへの接合は超音波併用型の熱圧着法により行なうことができる。 Bonding to the via-hole of the ball can be carried out by thermocompression bonding ultrasonic combination type. キャピラリーを垂直方向に移動させながら、クランパーを閉じボールの切断を行なう。 While moving the capillary in the vertical direction, for cutting the ball to close the clamper. この方法により、均一な大きさのボールを再現性良く埋め込むことができる。 By this method, it is possible to embed a ball uniform size with good reproducibility.

【0012】第2の導電層11は埋め込まれた半田層1 [0012] The solder layer was the second conductive layer 11 are embedded 1
0と共に絶縁層3の上面に形成され、これによりバイアホールを介して電気的に接続される。 0 with is formed on the upper surface of the insulating layer 3, thereby being electrically connected through a via hole. 第2導電層11は真空蒸着法、イオンプレーティングにより形成されることが好ましい。 Second conductive layer 11 is a vacuum deposition method, it is preferably formed by ion plating. 第2導電層に用いる金属としては銅、N The metal used for the second conductive layer of copper, N
i下地銅であるが銅であることが好ましい。 It is preferred, but i is the underlying copper is copper. 第2導電層11が形成されたあとは常法によりレジスト塗布、パターンニング、導電層のエッチングを行い、微細配線の多層構造のフィルムキャリア装置を得ることができる。 After the second conductive layer 11 is formed is usual manner resist coating, etching of the patterned conductive layer, it is possible to obtain a film carrier device with a multilayer structure of fine wiring.

【0013】本発明の別の態様を図4に示す。 [0013] Another aspect of the present invention shown in FIG. 図のように、半田ボールあるいは半田線の熔解物10と共に絶縁層3の上面に銅層7を設けているが、その層にはバイアホールの径よりも小さい穴を開けている。 As shown, although with melted material 10 of the solder balls or solder wire has a copper layer 7 provided on the upper surface of the insulating layer 3, and its layer has drilled a small hole than the diameter of the via hole. こうすることによって、半田の熔解の際に発生するガスの放出が容易となり、更に半田10が銅層7の上面に流出するのを防止し、第1導電シート層をバイアホールを介して銅層7 By so doing, it is easy to release a gas generated during solder melting, further solder 10 is prevented from flowing out to the upper surface of the copper layer 7, the copper layer through the via hole of the first conductive sheet layer 7
と確実に接続される。 It is securely connected to the.

【0014】 [0014]

【実施例】以下、本発明を実施例に基づき具体的に説明する。 EXAMPLES The following specifically described on the basis of the present invention embodiment.

【0015】(実施例1)直径300μmのバイアホールが形成された厚さ100μmの絶縁層(ポリイミド: [0015] (Example 1) insulating layer having a thickness of 100μm to via holes having a diameter of 300μm were formed (Polyimide:
宇部興産社製、商品名ユーピレックスS)3にエポキシ系接着剤2で厚さ25μmの銅箔シート1を貼り合わせた。 Manufactured by Ube Industries, Ltd., was bonded to a copper foil sheet 1 having a thickness of 25μm under the trade name Upilex S) 3 in the epoxy-based adhesive 2. 次いで径が300μmの半田(80%Sn−20% Solder diameter of 300μm and then (80% Sn-20%
Pb合金)線を80個のバイアホールに挿入切断後、約210℃で加熱した。 After inserting cut Pb alloy) line 80 of the via holes, was heated at about 210 ° C.. この段階の構造を図1に断面図として示す。 The structure of this stage is illustrated as a sectional view in FIG. 次いでこの構造の絶縁層3および半田層10 Then the insulating layer of the structure 3 and the solder layer 10
の上面に真空蒸着法で厚さ4μmの銅層11を形成し、 A copper layer 11 having a thickness of 4μm by vacuum deposition is formed on the upper surface of,
その後レジスト塗布、パターンニング、銅層のエッチングを行い、微細配線の2層構造のフィルムキャリア装置を作成した。 Thereafter the resist coating, patterning, etching of the copper layer to form a film carrier device having a two-layer structure of the fine wiring. 銅箔シート1と銅層11が接続された構造を図2に示す。 The structure foil sheet 1 and the copper layer 11 is connected is shown in FIG. 比較のため、同じ構成のバイアホールに、スパッタ法で厚さ4μmの銅膜5を形成した(図5 For comparison, the via holes of the same configuration, to form a copper film 5 having a thickness of 4μm by sputtering (FIG. 5
参照)。 reference).

【0016】両者の初期抵抗のばらつきを調べたところ、実施例1では初期抵抗のばらつきは0.1〜0.2 [0016] Examination of variations of both the initial resistance of the variation in the initial resistance Example 1 0.1 to 0.2
Ω、比較例1のものは0.2〜1.0Ωであり、本発明のものはばらつきも小さく安定していた。 Omega, those of Comparative Example 1 was 0.2~1.0Omu, those of the present invention is the variation was also smaller stable. また、このフィルムキャリア装置を−50℃〜+150℃の温度サイクル試験を実施しながら接続抵抗の推移を調べたところ、比較例1のフィルムキャリア装置よりも導通不可(バイアホールでの膜はがれによる断線)になる時間が2000時間と10倍長く、熱ストレスに対する信頼性が大幅に向上した。 We also examined the change in the film carrier device connection resistance while performing a temperature cycle test of -50 ℃ ~ + 150 ℃ a film in the conducting disabled (via hole than the film carrier device of Comparative Example 1 is broken by peeling time to be) is 2000 hours and 10 times longer, reliability against heat stress has been greatly improved.

【0017】(実施例2)厚さ25μmの銅箔シート1 [0017] (Example 2) having a thickness of 25μm copper foil sheet 1
にエポキシ系接着剤層2を介してポリイミド絶縁層(厚さ75μm、バイアホール径200μmで他面に銅箔キャスティング材12を有する)3を貼り合わせた。 Bonding the epoxy through the adhesive layer 2 of polyimide insulating layer (thickness 75 [mu] m, with a copper casting material 12 on the other surface in the via hole diameter 200 [mu] m) 3 in. 次いで直径180μmの半田(80%Sn−20%Pb合金)線を80個のバイアホールに挿入切断後、約200 Then after inserting cutting the solder (80% Sn-20% Pb alloy) wire having a diameter of 180μm to 80 of the via hole, about 200
℃で加熱しバイアホールを充満させた。 It was heated at ℃ and filled the via holes. その上にイオンプレーティングにより、厚さ5μmの銅層11を形成した(図3参照)。 An ion plating thereon to form a copper layer 11 having a thickness of 5 [mu] m (see FIG. 3). さらにレジスト塗布、パターンニングを行い、銅層をエッチングし、2層微細配線構造のフィルムキャリア装置を製作した。 The resist coating, subjected to patterning, a copper layer was etched to fabricate a film carrier device having a two-layer fine wiring structure. このフィルムキャリア装置を−50℃〜+150℃の温度サイクル試験(30分保持)を実施しながら接続抵抗の推移を調べたところ、 When the film carrier device was examined changes in connection resistance while performing a temperature cycle test of -50 ℃ ~ + 150 ℃ (30 min hold),
従来のめっきによる銅箔シートとの接続をしたものと比較して初期抵抗のばらつきも小さく導通不可(バイアホールあるいはスルーホールでの銅の電気めっき膜のはがれによる断線またはイオンプレーティングによる銅膜のはがれによる)になる時間が2000時間と5倍長く、 Variation in comparison to the initial resistance to those connected to a copper foil sheet by conventional plating is small conduction Call (copper film by open or ion plating by peeling the copper electroplating films on the via hole or through hole 2000 hours time to become due) to the peeling and 5 times longer,
熱ストレスに対する信頼性が大幅に向上した。 Reliability with respect to heat stress has been greatly improved.

【0018】温度サイクル(熱ストレス)試験法:バイアホールを介して電気的に接続したフィルムキャリア装置をEIAJ(Electronic Industries Association of The temperature cycle (thermal stress) Test Method: a film carrier device which is electrically connected through a via hole EIAJ (Electronic Industries Association of
Japan:社団法人日本電子機械工業会)の規格に準拠し、 Japan: conforms to the Japan standard of the Electronic Industries Association),
二葉科学製、冷熱サイクルの試験機を用い、−50℃に30分間保った後、昇温速度120℃/分で150℃に昇温し、30分間保つ。 Futaba Kagaku, using a test machine of thermal cycle, and retained for 30 minutes to -50 ° C., the temperature was raised to 0.99 ° C. at a heating rate of 120 ° C. / min and held for 30 minutes. 次いで降温速度−30℃/分で−50℃とする。 Then a -50 ° C. at a cooling rate of -30 ° C. / min. このサイクルを繰り返し、導通が不可になる時間を調べた。 Repeat this cycle, we examined the time that conduction becomes impossible. なお試験数48個の平均値で求めた。 Note determined in test number 48 average.

【0019】 [0019]

【発明の効果】本発明は以上説明したように構成されているので、本発明によって提供されるフィルムキャリア装置は半田ボール若しくは半田線がバイアホールに埋め込まれ、それによってバイアホールを介して第1および第2導電層の接続ができるため、熱ストレスに対する信頼性が向上した。 Since the present invention is constructed as described above, according to the present invention, a film carrier device provided by the present invention is embedded in the via hole solder balls or solder wire, whereby the through via-hole 1 and since it is connected to the second conductive layer, the reliability against thermal stress is improved. また、バイアホールが0.6mmより小径のもの程第1半田溶融層で確実にバイアホールを介しての接続ができる。 Furthermore, via holes can be connected via a reliable via hole in the first molten solder layer as those of smaller diameter than 0.6 mm. さらに本発明のフィルムキャリア装置は効率の良い接続法によるものであり、工業的な量産性にも優れている。 Furthermore the film carrier device of the present invention is by efficient connection method, is excellent in industrial mass production.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の実施例1の半田線を熔融した段階の構造を示す断面図である。 1 is a cross-sectional view showing the structure of a molten stage solder wire of Example 1 of the present invention.

【図2】本発明の実施例1の電気的接続を終えた段階の構造を示す断面図である。 2 is a sectional view showing a structure of a step of completing the electrical connection of the first embodiment of the present invention.

【図3】本発明の実施例2の電気的接続を終えた段階の構造を示す断面図である。 3 is a cross-sectional view showing a structure of a step of completing the electrical connection of the second embodiment of the present invention.

【図4】本発明の装置の別の態様を示す断面図である。 It is a sectional view showing another embodiment of the apparatus of the present invention; FIG.

【図5】従来のスパッタ法により電気的に接続した構造を示す断面図である。 5 is a cross-sectional view showing an electrical connection structure by a conventional sputtering method.

【図6】従来のめっき法により電気的に接続した構造を示す断面図である。 6 is a sectional view showing an electrical connection structure by a conventional plating method.

【図7】半田ボールの埋め込み工程(装置)の一例を示す断面図である。 7 is a sectional view showing an example of a solder ball of embedding step (device).

【符号の説明】 DESCRIPTION OF SYMBOLS

1 銅箔シート(第1導電シート層) 2 接着剤層 3 絶縁層 4 バイアホール 5 銅膜層 6 接着剤層 7 銅箔シート層 8 スルーホール 9 めっき層 10 半田層 11 銅層(第2導電層) 21 クランパー 22 キャピラリーティップ 23 半田ワイヤー 24 埋め込み前の半田ボール 25 印加電極 26 雰囲気ガス供給ライン 1 copper foil sheet (first conductive sheet layer) 2 adhesive layer 3 insulating layer 4 via hole 5 Domakuso 6 adhesive layer 7 copper foil sheet layer 8 through hole 9 plating layer 10 a solder layer 11 of copper layer (second conductive layer) 21 clamper 22 capillary tip 23 solder wire 24 buried before the solder balls 25 applied electrode 26 atmospheric gas supply line

フロントページの続き (72)発明者 御 田 護 茨城県日立市助川町3丁目1番1号 日立 電線株式会社電線工場内 (72)発明者 高 城 正 治 茨城県日立市助川町3丁目1番1号 日立 電線株式会社電線工場内 Of the front page Continued (72) invention's your field protect Hitachi City, Ibaraki Prefecture Sukegawa-cho 3-chome No. 1 Hitachi Electric Cable Co., Ltd. wire in the factory (72) inventor high Tadashi Jo jig Hitachi City, Ibaraki Prefecture Sukegawa-cho 3-chome No. 1 Hitachi Electric cable Co., Ltd. wire in the factory

Claims (1)

  1. 【特許請求の範囲】 【請求項1】 絶縁層の両面に第1および第2導電層を有し、これらの導電層間がバイアホールを介して電気的に接続されてなるフィルムキャリア装置であって、バイアホールは半田ボールまたは半田線の加熱溶解によって半田により実質的に充填されていることを特徴とするフィルムキャリア装置。 [Claims 1, further comprising a first and second conductive layers on both surfaces of the insulating layer, these conductive layers is a film carrier device made are electrically connected via a via hole , via holes film carrier device which is characterized by being substantially filled with solder by heating and melting the solder balls or solder wire.
JP17660191A 1991-07-17 1991-07-17 Film carrier device Expired - Lifetime JP2757594B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5679978A (en) * 1993-12-06 1997-10-21 Fujitsu Limited Semiconductor device having resin gate hole through substrate for resin encapsulation
US6111306A (en) * 1993-12-06 2000-08-29 Fujitsu Limited Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59232491A (en) * 1983-06-15 1984-12-27 Matsushita Electric Works Ltd Method of producing multilayer printed circuit board
JPS6236900A (en) * 1984-08-06 1987-02-17 Ibiden Co Ltd Manufacture of compound printed wiring board
JPH0311646A (en) * 1989-06-08 1991-01-18 Shinko Electric Ind Co Ltd Film carrier for tab use

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59232491A (en) * 1983-06-15 1984-12-27 Matsushita Electric Works Ltd Method of producing multilayer printed circuit board
JPS6236900A (en) * 1984-08-06 1987-02-17 Ibiden Co Ltd Manufacture of compound printed wiring board
JPH0311646A (en) * 1989-06-08 1991-01-18 Shinko Electric Ind Co Ltd Film carrier for tab use

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5679978A (en) * 1993-12-06 1997-10-21 Fujitsu Limited Semiconductor device having resin gate hole through substrate for resin encapsulation
US5804467A (en) * 1993-12-06 1998-09-08 Fujistsu Limited Semiconductor device and method of producing the same
US6111306A (en) * 1993-12-06 2000-08-29 Fujitsu Limited Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same
US6379997B1 (en) 1993-12-06 2002-04-30 Fujitsu Limited Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same

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