JPH0521538A - Film carrier device - Google Patents
Film carrier deviceInfo
- Publication number
- JPH0521538A JPH0521538A JP3176601A JP17660191A JPH0521538A JP H0521538 A JPH0521538 A JP H0521538A JP 3176601 A JP3176601 A JP 3176601A JP 17660191 A JP17660191 A JP 17660191A JP H0521538 A JPH0521538 A JP H0521538A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- solder
- via hole
- copper
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はバイアホールを有するフ
ィルムキャリア装置に関する。FIELD OF THE INVENTION The present invention relates to a film carrier device having a via hole.
【０００２】[0002]
【従来の技術】最近ＩＣの薄型高密度実装化に対応し
て、ＩＣチップをフィルムキャリアに取り付けて実装す
るＴＡＢ（テープキャリア方式）が用いられている。こ
のようなＴＡＢにおいては、例えばポリイミドフィルム
などの絶縁層の上面に信号層、下面に電源層を有してい
るが、下面の電源層から配線をとるためなどの目的でバ
イアホールが設けられる。2. Description of the Related Art Recently, a TAB (tape carrier system) has been used in which an IC chip is mounted and mounted on a film carrier in response to thinning and high density mounting of ICs. In such a TAB, a signal layer is provided on the upper surface of an insulating layer such as a polyimide film and a power supply layer is provided on the lower surface, but a via hole is provided for the purpose of wiring from the power supply layer on the lower surface.
【０００３】フィルムキャリア装置に形成されたバイア
ホールを接続する手段として、従来例えば図５に示すよ
うにスパッタ法で銅をコートして銅膜層５を形成する方
法がある。すなわち例えば厚さ２５μｍの銅箔１、厚さ
７５μｍの絶縁層３に形成されたバイアホール４をスパ
ッタ法による厚さ４μｍの銅膜層５により接続してい
る。また、図６には例えば厚さ７５μｍのポリイミド絶
縁層３の両面に厚さ２５μｍの銅箔１、７をエポキシ系
接着剤２、６により張り合わせた後、径０．２〜０．６
ｍｍのスルーホール８を形成したものであるが、その接
続法として、銅の電気めっき法や無電解めっき法により
めっき層９を形成したものである。いずれの方法も、バ
イアホールを形成する壁面を介して電気的に接続するも
のである。As a means for connecting via holes formed in a film carrier device, there is conventionally a method of forming copper film layer 5 by coating copper by a sputtering method as shown in FIG. 5, for example. That is, for example, a copper foil 1 having a thickness of 25 μm and a via hole 4 formed in an insulating layer 3 having a thickness of 75 μm are connected by a copper film layer 5 having a thickness of 4 μm formed by a sputtering method. Further, in FIG. 6, for example, copper foils 1 and 7 having a thickness of 25 μm are adhered to both surfaces of a polyimide insulating layer 3 having a thickness of 75 μm with epoxy adhesives 2 and 6, and the diameter is 0.2 to 0.6.
Although the through hole 8 of mm is formed, the plating layer 9 is formed by a copper electroplating method or an electroless plating method as the connection method. Both methods are electrically connected via the wall surface forming the via hole.
【０００４】前記スパッタ法による接続では、ポリイミ
ド絶縁層が発熱し、熱変形するうえ、用いるポリイミド
の種類（例えば商品名カプトンＨ、ユーピレックスＳ
等）によっては、形成される銅膜層の密着力が３０ｇ／
ｃｍ以下と弱く、密着力向上のためにはスパッタの後、
特殊なプラズマ処理が必要であった。まためっき法は、
一般に密着力が良いものの、やはり用いるポリイミドの
種類（例えば商品名カプトンＤ、ユーピレックスＳ等）
によってはめっきの密着性が悪く、熱ストレスに対する
信頼性に乏しいという問題がある。さらに銅の電気めっ
きでは５〜１０分、無電解めっきでは１〜２時間とめっ
きに時間がかかること、湿式で行なわれるためイオン性
物質がバイアホールや層間に残留して、マイグレーショ
ンや配線腐食原因となることなどの問題もある。In the connection by the sputtering method, the polyimide insulating layer generates heat and is thermally deformed, and the type of polyimide used (eg, Kapton H, trade name, Upilex S).
Etc.), the adhesion of the formed copper film layer is 30 g /
It is weak as cm or less. To improve the adhesion, after sputtering,
Special plasma treatment was required. The plating method is
In general, the adhesion is good, but the type of polyimide still used (eg Kapton D, Upilex S, etc.)
However, there is a problem that the adhesion of plating is poor and the reliability against heat stress is poor. Furthermore, copper electroplating takes 5 to 10 minutes, electroless plating takes 1 to 2 hours, and since it is wet, ionic substances remain in via holes and layers, causing migration and wiring corrosion. There are also problems such as
【０００５】[0005]
【発明が解決しようとする課題】フィルムキャリア装置
の絶縁層の両面に有する導電層間をバイアホールを介し
て電気的に接続する上記従来技術の課題に鑑み、信頼性
が高く、容易に接続できる方法が求められていた。本発
明は、このような要望に応えるものである。SUMMARY OF THE INVENTION In view of the above problems of the prior art of electrically connecting conductive layers on both sides of an insulating layer of a film carrier device through via holes, a reliable and easily connectable method. Was required. The present invention meets these needs.
【０００６】本発明は導電層間の電気的接続を半田ボー
ル等の溶融によるバイアホールの埋め込みを行なった
後、例えば蒸着法などにより他の導電層を形成すること
により実現するものであり、加工作業が極めて簡単で、
バイアホールを介しての電気的接続の信頼性の高いフィ
ルムキャリア装置を提供するものである。The present invention realizes electrical connection between conductive layers by filling a via hole by melting a solder ball or the like and then forming another conductive layer by, for example, a vapor deposition method. Is extremely easy,
It is intended to provide a film carrier device having high reliability of electrical connection through a via hole.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に本発明によれば、絶縁層の両面に第１および第２導電
層を有し、これらの導電層間がバイアホールを介して電
気的に接続されてなるフィルムキャリア装置であって、
バイアホールは半田ボールまたは半田線の加熱溶解によ
って半田により実質的に充填されていることを特徴とす
るフィルムキャリア装置が提供される。以下図面に基づ
き、本発明をさらに詳細に説明する。To achieve the above object, according to the present invention, first and second conductive layers are provided on both surfaces of an insulating layer, and these conductive layers are electrically connected via a via hole. A film carrier device connected to
There is provided a film carrier device, wherein the via hole is substantially filled with solder by heating and melting a solder ball or a solder wire. Hereinafter, the present invention will be described in more detail with reference to the drawings.
【０００８】本発明において第１導電シート層としては
銅箔シート、銅合金（Ｃｕ−Ｚｒ，Ｃｕ−Ｓｎ合金）箔
シート、４２系合金（Ｆｅ−４２％Ｎｉ合金、Ｆｅ−４
２％Ｎｉ−３％Ｃｏ合金）箔シートなどが挙げられる。
第１導電シート層の厚さは通常４〜３５μｍである。ま
た、絶縁層３は商品名カプトンＤ、カプトンＨ、ユーピ
レックスＳなどで知られるポリイミドフィルム、ガラス
エポキシ、ＢＴレジンポリエステルフィルム等が挙げら
れるが、通常ポリイミドフィルムが好んで用いられる。
絶縁層の厚さは通常２５〜１５０μｍである。In the present invention, as the first conductive sheet layer, a copper foil sheet, a copper alloy (Cu-Zr, Cu-Sn alloy) foil sheet, a 42 series alloy (Fe-42% Ni alloy, Fe-4) is used.
2% Ni-3% Co alloy) foil sheet and the like.
The thickness of the first conductive sheet layer is usually 4 to 35 μm. Examples of the insulating layer 3 include polyimide films known by trade names Kapton D, Kapton H, and Upilex S, glass epoxy, BT resin polyester film, and the like, and normally polyimide film is preferably used.
The thickness of the insulating layer is usually 25 to 150 μm.
【０００９】バイアホールは、通常絶縁層にフォトレジ
スト層を形成し、それをマスクとしてヒドラジン等の液
中でフィルムシートの一部の領域をエッチングすること
により形成することができる。バイアホールの直径は通
常０．０５ｍｍから０．６ｍｍの範囲にあることが好ま
しい。その理由としては、多層配線でしかも配線ピッチ
が１４０μｍと狭くなる傾向にあるので０．６ｍｍを越
えるスペースを確保するのが困難である。また直径が
０．０５ｍｍよりも小さくなると本発明で使用する半田
ボールや半田線の挿入が実際上困難となる。The via hole can be formed by forming a photoresist layer on the insulating layer and etching a part of the film sheet in a liquid such as hydrazine using the photoresist layer as a mask. The diameter of the via hole is preferably in the range of usually 0.05 mm to 0.6 mm. The reason is that it is a multilayer wiring and the wiring pitch tends to be narrow as 140 μm, so that it is difficult to secure a space exceeding 0.6 mm. If the diameter is smaller than 0.05 mm, it becomes practically difficult to insert the solder balls and the solder wires used in the present invention.
【００１０】本発明におけるバイアホール内の埋め込み
は、例えば図１に示すように半田ボール若しくは半田線
を加熱溶融して絶縁層の上面高さ付近まで半田１０によ
り埋め込む。半田の埋め込み高さは絶縁層の上面高さに
なるべく合わせることが好ましい。半田の組成としては
Ｓｎが通常１００〜５％の範囲にあるものが好んで使用
される。半田ボールは常法により通常直径３５〜４００
μｍの半田線（ワイヤ）を加熱して製造する。半田線は
バイアホールに挿入し長さ５５〜７００μｍに切断す
る。In the embedding in the via hole in the present invention, for example, as shown in FIG. 1, a solder ball or a solder wire is heated and melted to be embedded by solder 10 up to the height of the upper surface of the insulating layer. It is preferable that the height of embedding the solder is as high as the height of the upper surface of the insulating layer. As the composition of the solder, one having Sn in the range of 100 to 5% is preferably used. Solder balls usually have a diameter of 35 to 400 by the conventional method.
It is manufactured by heating a solder wire (wire) of μm. The solder wire is inserted into the via hole and cut to a length of 55 to 700 μm.
【００１１】図７に半田ボールの埋め込み工程（装置）
の一例を示した。キャピラリー２２の孔に通した半田ワ
イヤ２３の先端を、ライン２６からのＡｒ＋１０％Ｈ2
等の雰囲気中でアーク放電により熔解し、ボール２４を
形成する。この時ボールの径はワイヤーの３倍の径迄作
ることができるのでバイアホールに１回の埋め込みで完
全に充填する事ができる。ボールのバイアホールへの接
合は超音波併用型の熱圧着法により行なうことができ
る。キャピラリーを垂直方向に移動させながら、クラン
パーを閉じボールの切断を行なう。この方法により、均
一な大きさのボールを再現性良く埋め込むことができ
る。FIG. 7 shows a solder ball embedding process (apparatus).
An example is shown. The tip of the solder wire 23 passed through the hole of the capillary 22 is set to Ar + 10% H2 from the line 26.
The balls 24 are formed by melting in an atmosphere such as arc discharge. At this time, the diameter of the ball can be made up to three times the diameter of the wire, so that the via hole can be completely filled by embedding it once. The ball can be joined to the via hole by a thermocompression bonding method using ultrasonic waves. While moving the capillary vertically, close the clamper and cut the ball. By this method, balls having a uniform size can be embedded with good reproducibility.
【００１２】第２の導電層１１は埋め込まれた半田層１
０と共に絶縁層３の上面に形成され、これによりバイア
ホールを介して電気的に接続される。第２導電層１１は
真空蒸着法、イオンプレーティングにより形成されるこ
とが好ましい。第２導電層に用いる金属としては銅、Ｎ
ｉ下地銅であるが銅であることが好ましい。第２導電層
１１が形成されたあとは常法によりレジスト塗布、パタ
ーンニング、導電層のエッチングを行い、微細配線の多
層構造のフィルムキャリア装置を得ることができる。The second conductive layer 11 is an embedded solder layer 1
It is formed on the upper surface of the insulating layer 3 together with 0, and is thereby electrically connected through the via hole. The second conductive layer 11 is preferably formed by a vacuum vapor deposition method or ion plating. The metal used for the second conductive layer is copper, N
i The base copper, but preferably copper. After the second conductive layer 11 is formed, resist coating, patterning, and etching of the conductive layer are performed by a conventional method to obtain a film carrier device having a multilayered structure of fine wiring.
【００１３】本発明の別の態様を図４に示す。図のよう
に、半田ボールあるいは半田線の熔解物１０と共に絶縁
層３の上面に銅層７を設けているが、その層にはバイア
ホールの径よりも小さい穴を開けている。こうすること
によって、半田の熔解の際に発生するガスの放出が容易
となり、更に半田１０が銅層７の上面に流出するのを防
止し、第１導電シート層をバイアホールを介して銅層７
と確実に接続される。Another aspect of the invention is shown in FIG. As shown in the figure, the copper layer 7 is provided on the upper surface of the insulating layer 3 together with the melted material 10 of the solder ball or the solder wire, and a hole smaller than the diameter of the via hole is formed in this layer. This facilitates the release of gas generated during melting of the solder, prevents the solder 10 from flowing out to the upper surface of the copper layer 7, and connects the first conductive sheet layer to the copper layer via the via hole. 7
Is connected securely.
【００１４】[0014]
【実施例】以下、本発明を実施例に基づき具体的に説明
する。EXAMPLES The present invention will be specifically described below based on examples.
【００１５】（実施例１）直径３００μｍのバイアホー
ルが形成された厚さ１００μｍの絶縁層（ポリイミド：
宇部興産社製、商品名ユーピレックスＳ）３にエポキシ
系接着剤２で厚さ２５μｍの銅箔シート１を貼り合わせ
た。次いで径が３００μｍの半田（８０％Ｓｎ−２０％
Ｐｂ合金）線を８０個のバイアホールに挿入切断後、約
２１０℃で加熱した。この段階の構造を図１に断面図と
して示す。次いでこの構造の絶縁層３および半田層１０
の上面に真空蒸着法で厚さ４μｍの銅層１１を形成し、
その後レジスト塗布、パターンニング、銅層のエッチン
グを行い、微細配線の２層構造のフィルムキャリア装置
を作成した。銅箔シート１と銅層１１が接続された構造
を図２に示す。比較のため、同じ構成のバイアホール
に、スパッタ法で厚さ４μｍの銅膜５を形成した（図５
参照）。(Embodiment 1) An insulating layer (polyimide: 100 μm thick) in which a via hole having a diameter of 300 μm is formed.
A copper foil sheet 1 having a thickness of 25 μm was attached to an Ube Industries, Ltd. product name Upilex S) 3 with an epoxy adhesive 2. Next, solder with a diameter of 300 μm (80% Sn-20%
The Pb alloy) wire was inserted into 80 via holes and cut, and then heated at about 210 ° C. The structure at this stage is shown in a sectional view in FIG. Next, the insulating layer 3 and the solder layer 10 of this structure
Forming a copper layer 11 having a thickness of 4 μm on the upper surface of
After that, resist coating, patterning, and etching of the copper layer were performed to prepare a film carrier device having a two-layer structure of fine wiring. A structure in which the copper foil sheet 1 and the copper layer 11 are connected is shown in FIG. For comparison, a copper film 5 having a thickness of 4 μm was formed in the via hole having the same structure by the sputtering method (FIG. 5).
reference).
【００１６】両者の初期抵抗のばらつきを調べたとこ
ろ、実施例１では初期抵抗のばらつきは０．１〜０．２
Ω、比較例１のものは０．２〜１．０Ωであり、本発明
のものはばらつきも小さく安定していた。また、このフ
ィルムキャリア装置を−５０℃〜＋１５０℃の温度サイ
クル試験を実施しながら接続抵抗の推移を調べたとこ
ろ、比較例１のフィルムキャリア装置よりも導通不可
（バイアホールでの膜はがれによる断線）になる時間が
２０００時間と１０倍長く、熱ストレスに対する信頼性
が大幅に向上した。When the variation in the initial resistance of both is examined, the variation in the initial resistance in Example 1 is 0.1 to 0.2.
.OMEGA., That of Comparative Example 1 was 0.2 to 1.0 .OMEGA., And that of the present invention was stable with little variation. Further, when the transition of the connection resistance was examined while carrying out a temperature cycle test of -50 ° C to + 150 ° C on this film carrier device, conduction was impossible as compared with the film carrier device of Comparative Example 1 (breakage due to film peeling in via hole). ) Is 2000 hours, which is 10 times longer, and the reliability against heat stress is significantly improved.
【００１７】（実施例２）厚さ２５μｍの銅箔シート１
にエポキシ系接着剤層２を介してポリイミド絶縁層（厚
さ７５μｍ、バイアホール径２００μｍで他面に銅箔キ
ャスティング材１２を有する）３を貼り合わせた。次い
で直径１８０μｍの半田（８０％Ｓｎ−２０％Ｐｂ合
金）線を８０個のバイアホールに挿入切断後、約２００
℃で加熱しバイアホールを充満させた。その上にイオン
プレーティングにより、厚さ５μｍの銅層１１を形成し
た（図３参照）。さらにレジスト塗布、パターンニング
を行い、銅層をエッチングし、２層微細配線構造のフィ
ルムキャリア装置を製作した。このフィルムキャリア装
置を−５０℃〜＋１５０℃の温度サイクル試験（３０分
保持）を実施しながら接続抵抗の推移を調べたところ、
従来のめっきによる銅箔シートとの接続をしたものと比
較して初期抵抗のばらつきも小さく導通不可（バイアホ
ールあるいはスルーホールでの銅の電気めっき膜のはが
れによる断線またはイオンプレーティングによる銅膜の
はがれによる）になる時間が２０００時間と５倍長く、
熱ストレスに対する信頼性が大幅に向上した。(Example 2) Copper foil sheet 1 having a thickness of 25 μm
Then, a polyimide insulating layer (thickness: 75 μm, via hole diameter: 200 μm, and copper foil casting material 12 on the other surface) 3 was attached via an epoxy adhesive layer 2. Then, after inserting a solder (80% Sn-20% Pb alloy) wire with a diameter of 180 μm into 80 via holes and cutting it, about 200
The via holes were filled by heating at ℃. A copper layer 11 having a thickness of 5 μm was formed thereon by ion plating (see FIG. 3). Further, resist coating and patterning were performed, the copper layer was etched, and a film carrier device having a two-layer fine wiring structure was manufactured. This film carrier device was subjected to a temperature cycle test (holding for 30 minutes) at -50 ° C to + 150 ° C, and the transition of the connection resistance was examined.
Compared to the conventional one that is connected to the copper foil sheet by plating, the variation in the initial resistance is small and it is not possible to conduct (breakage due to peeling of the copper electroplated film in the via hole or through hole or the copper film due to ion plating). The time it takes to peel off is 2000 hours, five times longer,
The reliability against heat stress is significantly improved.
【００１８】温度サイクル（熱ストレス）試験法：バイ
アホールを介して電気的に接続したフィルムキャリア装
置をＥＩＡＪ(Electronic Industries Association of
Japan:社団法人日本電子機械工業会）の規格に準拠し、
二葉科学製、冷熱サイクルの試験機を用い、−５０℃に
３０分間保った後、昇温速度１２０℃／分で１５０℃に
昇温し、３０分間保つ。次いで降温速度−３０℃／分で
−５０℃とする。このサイクルを繰り返し、導通が不可
になる時間を調べた。なお試験数４８個の平均値で求め
た。Temperature cycle (heat stress) test method: EIAJ (Electronic Industries Association of Electronic Film Association) of film carrier device electrically connected through a via hole.
Japan: Japan Electronic Machinery Manufacturers Association) standard,
Using a tester of a cooling and heating cycle manufactured by Futaba Kagaku, the temperature was kept at -50 ° C for 30 minutes, then the temperature was raised to 150 ° C at a temperature rising rate of 120 ° C / minute and kept for 30 minutes. Then, the temperature is lowered to -50 ° C at a rate of -30 ° C / minute. This cycle was repeated and the time when conduction was disabled was investigated. The average value of 48 tests was calculated.
【００１９】[0019]
【発明の効果】本発明は以上説明したように構成されて
いるので、本発明によって提供されるフィルムキャリア
装置は半田ボール若しくは半田線がバイアホールに埋め
込まれ、それによってバイアホールを介して第１および
第２導電層の接続ができるため、熱ストレスに対する信
頼性が向上した。また、バイアホールが０．６ｍｍより
小径のもの程第１半田溶融層で確実にバイアホールを介
しての接続ができる。さらに本発明のフィルムキャリア
装置は効率の良い接続法によるものであり、工業的な量
産性にも優れている。Since the present invention is constructed as described above, in the film carrier device provided by the present invention, the solder balls or the solder wires are embedded in the via holes, whereby the first through the via holes. Since the second conductive layer can be connected, the reliability against heat stress is improved. In addition, the smaller the via hole diameter is less than 0.6 mm, the more reliable the connection can be via the via hole in the first solder melting layer. Further, the film carrier device of the present invention is based on an efficient connection method and is excellent in industrial mass productivity.
【図１】本発明の実施例１の半田線を熔融した段階の構
造を示す断面図である。FIG. 1 is a cross-sectional view showing a structure at a stage of melting a solder wire according to a first embodiment of the present invention.
【図２】本発明の実施例１の電気的接続を終えた段階の
構造を示す断面図である。FIG. 2 is a cross-sectional view showing a structure at a stage where electrical connection is finished according to the first embodiment of the present invention.
【図３】本発明の実施例２の電気的接続を終えた段階の
構造を示す断面図である。FIG. 3 is a cross-sectional view showing a structure of a second embodiment of the present invention at a stage where electrical connection is completed.
【図４】本発明の装置の別の態様を示す断面図である。FIG. 4 is a cross-sectional view showing another aspect of the device of the present invention.
【図５】従来のスパッタ法により電気的に接続した構造
を示す断面図である。FIG. 5 is a cross-sectional view showing a structure electrically connected by a conventional sputtering method.
【図６】従来のめっき法により電気的に接続した構造を
示す断面図である。FIG. 6 is a cross-sectional view showing a structure electrically connected by a conventional plating method.
【図７】半田ボールの埋め込み工程（装置）の一例を示
す断面図である。FIG. 7 is a cross-sectional view showing an example of a solder ball embedding step (apparatus).
１ 銅箔シート（第１導電シート層） ２ 接着剤層 ３ 絶縁層 ４ バイアホール ５ 銅膜層 ６ 接着剤層 ７ 銅箔シート層 ８ スルーホール ９ めっき層 １０ 半田層 １１ 銅層（第２導電層） ２１ クランパー ２２ キャピラリーティップ ２３ 半田ワイヤー ２４ 埋め込み前の半田ボール ２５ 印加電極 ２６ 雰囲気ガス供給ライン 1 Copper Foil Sheet (First Conductive Sheet Layer) 2 Adhesive Layer 3 Insulating Layer 4 Via Hole 5 Copper Film Layer 6 Adhesive Layer 7 Copper Foil Sheet Layer 8 Through Hole 9 Plating Layer 10 Solder Layer 11 Copper Layer (Second Conductive Layer) Layer) 21 Clamper 22 Capillary tip 23 Solder wire 24 Solder ball before embedding 25 Applied electrode 26 Atmosphere gas supply line
フロントページの続き (72)発明者 御 田 護 茨城県日立市助川町３丁目１番１号 日立 電線株式会社電線工場内 (72)発明者 高 城 正 治 茨城県日立市助川町３丁目１番１号 日立 電線株式会社電線工場内Front page continuation (72) Inventor Mamoru Ota 3-1-1 Sukegawa-cho, Hitachi City, Ibaraki Hitachi Cable Company Ltd. (72) Inventor Masaharu Takashiro 3-1-1 Sukegawa-cho, Ibaraki Prefecture No. 1 in the electric wire factory of Hitachi Cable, Ltd.
Claims (1)
有し、これらの導電層間がバイアホールを介して電気的
に接続されてなるフィルムキャリア装置であって、バイ
アホールは半田ボールまたは半田線の加熱溶解によって
半田により実質的に充填されていることを特徴とするフ
ィルムキャリア装置。Claim: What is claimed is: 1. A film carrier device comprising first and second conductive layers on both sides of an insulating layer, the conductive layers being electrically connected through via holes. A film carrier device, wherein the via hole is substantially filled with solder by heating and melting a solder ball or a solder wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3176601A JP2757594B2 (en) | 1991-07-17 | 1991-07-17 | Film carrier equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3176601A JP2757594B2 (en) | 1991-07-17 | 1991-07-17 | Film carrier equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0521538A true JPH0521538A (en) | 1993-01-29 |
| JP2757594B2 JP2757594B2 (en) | 1998-05-25 |
Family
ID=16016424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3176601A Expired - Lifetime JP2757594B2 (en) | 1991-07-17 | 1991-07-17 | Film carrier equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2757594B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5679978A (en) * | 1993-12-06 | 1997-10-21 | Fujitsu Limited | Semiconductor device having resin gate hole through substrate for resin encapsulation |
| US6111306A (en) * | 1993-12-06 | 2000-08-29 | Fujitsu Limited | Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59232491A (en) * | 1983-06-15 | 1984-12-27 | 松下電工株式会社 | Method of producing multilayer printed circuit board |
| JPS6236900A (en) * | 1984-08-06 | 1987-02-17 | イビデン株式会社 | Manufacture of compound printed wiring board |
| JPH0311646A (en) * | 1989-06-08 | 1991-01-18 | Shinko Electric Ind Co Ltd | Film carrier for tab use |
-
1991
- 1991-07-17 JP JP3176601A patent/JP2757594B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59232491A (en) * | 1983-06-15 | 1984-12-27 | 松下電工株式会社 | Method of producing multilayer printed circuit board |
| JPS6236900A (en) * | 1984-08-06 | 1987-02-17 | イビデン株式会社 | Manufacture of compound printed wiring board |
| JPH0311646A (en) * | 1989-06-08 | 1991-01-18 | Shinko Electric Ind Co Ltd | Film carrier for tab use |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5679978A (en) * | 1993-12-06 | 1997-10-21 | Fujitsu Limited | Semiconductor device having resin gate hole through substrate for resin encapsulation |
| US5804467A (en) * | 1993-12-06 | 1998-09-08 | Fujistsu Limited | Semiconductor device and method of producing the same |
| US6111306A (en) * | 1993-12-06 | 2000-08-29 | Fujitsu Limited | Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same |
| US6379997B1 (en) | 1993-12-06 | 2002-04-30 | Fujitsu Limited | Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2757594B2 (en) | 1998-05-25 |
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