JP2757593B2 - Manufacturing method of film carrier device - Google Patents
Manufacturing method of film carrier deviceInfo
- Publication number
- JP2757593B2 JP2757593B2 JP3176598A JP17659891A JP2757593B2 JP 2757593 B2 JP2757593 B2 JP 2757593B2 JP 3176598 A JP3176598 A JP 3176598A JP 17659891 A JP17659891 A JP 17659891A JP 2757593 B2 JP2757593 B2 JP 2757593B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- copper
- insulating layer
- carrier device
- film carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4084—Through-connections; Vertical interconnect access [VIA] connections by deforming at least one of the conductive layers
Landscapes
- Wire Bonding (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明はバイアホールを有するフ
ィルムキャリア装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a film carrier device having a via hole.
【0002】[0002]
【従来の技術】最近ICの薄型高密度実装化に対応し
て、ICチップをフィルムキャリアに取り付けて実装す
るTAB(テープキャリア方式)が用いられている。こ
のようなTABにおいては、例えばポリイミドフィルム
などの絶縁層の上面に信号層、下面に電源層を有してい
るが、下面の電源層から配線をとるためなどの目的でバ
イアホールが設けられる。2. Description of the Related Art In recent years, TAB (tape carrier type), in which an IC chip is mounted on a film carrier and mounted, has been used in response to the trend toward thinner and higher density mounting of ICs. In such a TAB, for example, a signal layer is provided on the upper surface of an insulating layer such as a polyimide film, and a power supply layer is provided on the lower surface. However, via holes are provided for the purpose of wiring from the power supply layer on the lower surface.
【0003】フィルムキャリア装置に形成されたバイア
ホールを接続する手段として、従来例えば図7に示すよ
うにスパッタ法で銅をコートして銅膜層5を形成する方
法がある。すなわち例えば厚さ25μmの銅箔1、接着
剤層2、厚さ75μmの絶縁層3に形成されたバイアホ
ール4をスパッタ法による厚さ4μmの銅膜層5により
接続している。また、図8には例えば厚さ75μmのポ
リイミド絶縁層3の両面に厚さ35μmの銅箔1、7を
エポキシ系接着剤2、6により張り合わせた後、径0.
2〜0.6mmのスルーホール8を形成したものである
が、その接続法として、銅の電気めっき法や無電解めっ
き法によりめっき層9を形成したものである。As a means for connecting via holes formed in a film carrier device, there is a conventional method of forming a copper film layer 5 by coating copper by sputtering as shown in FIG. That is, for example, a copper foil 1 having a thickness of 25 μm, an adhesive layer 2, and a via hole 4 formed in an insulating layer 3 having a thickness of 75 μm are connected by a copper film layer 5 having a thickness of 4 μm by a sputtering method. In FIG. 8, for example, copper foils 1 and 7 each having a thickness of 35 μm are attached to both surfaces of a polyimide insulating layer 3 having a thickness of 75 μm with epoxy adhesives 2 and 6, respectively.
A through hole 8 of 2 to 0.6 mm is formed, and as a connection method, a plating layer 9 is formed by a copper electroplating method or an electroless plating method.
【0004】前記スパッタ法による接続では、ポリイミ
ド絶縁層が発熱し、熱変形するうえ、用いるポリイミド
の種類(例えば商品名カプトンH、ユーピレックスS
等)によっては、形成される銅膜層の密着力が30g/
cm以下と弱く、密着力向上のためにはスパッタの後、
特殊なプラズマ処理が必要であった。まためっき法は、
一般に密着力が良いものの、やはり用いるポリイミドの
種類(例えば商品名カプトンD、ユーピレックスS等)
によってはめっきの密着性が悪く、熱ストレスに対する
信頼性に乏しいという問題がある。さらに銅の電気めっ
きでは5〜10分、無電解めっきでは1〜2時間とめっ
きに時間がかかること、湿式で行なわれるためイオン性
物質がバイアホールや層間に残留して、マイグレーショ
ンや配線腐食原因となることなどの問題もある。[0004] In the connection by the sputtering method, the polyimide insulating layer generates heat and is thermally deformed. In addition, the kind of polyimide used (for example, Kapton H, Upilex S, trade name) is used.
And the like, the adhesion of the formed copper film layer is 30 g /
cm or less, and after sputtering to improve adhesion,
Special plasma treatment was required. The plating method is
In general, although the adhesive strength is good, the kind of polyimide to be used (for example, Kapton D, Upilex S, etc.)
In some cases, there is a problem that the adhesion of the plating is poor and the reliability against thermal stress is poor. In addition, electroplating of copper takes 5 to 10 minutes, and electroless plating takes 1 to 2 hours. It takes place in a wet process, and ionic substances remain between via holes and layers, causing migration and wiring corrosion. There are also problems such as becoming.
【0005】[0005]
【発明が解決しようとする課題】フィルムキャリア装置
の絶縁層の両面に有する導電層間をバイアホールを介し
て電気的に接続する上記従来技術の課題に鑑み、信頼性
が高く、容易に接続できる方法が求められていた。本発
明は、このような要望に応えるものである。In view of the above-mentioned problem of the prior art in which conductive layers provided on both sides of an insulating layer of a film carrier device are electrically connected through via holes, a highly reliable and easily connectable method. Was required. The present invention addresses such a need.
【0006】本発明は導電層間の電気的接続を一方の導
電層の突き出し加工を行なった後、蒸着法により他の導
電層を形成することにより実現するものであり、加工作
業が極めて簡単で、バイアホールを介しての電気的接続
の信頼性の高いフィルムキャリア装置の製造方法を提供
するものである。According to the present invention, the electrical connection between the conductive layers is realized by forming the other conductive layer by a vapor deposition method after the protruding process of one conductive layer is performed. An object of the present invention is to provide a method of manufacturing a film carrier device having high reliability of electrical connection via via holes.
【0007】[0007]
【課題を解決するための手段】上記目的を達成するため
に本発明によれば、絶縁層の両面に第1および第2導電
層を有し、これらの導電層間がバイアホールを介して電
気的に接続されてなるフィルムキャリア装置の製造方法
であって、前記第1導電層を、前記絶縁層の一方の面に
銅箔を貼り付けた後、前記バイアホール内を当該絶縁層
の他方の面の高さ付近まで突き出し加工して形成すると
共に、前記バイアホール内に突き出した第1導電層の突
出方向の表面および前記絶縁層の他方の面に真空蒸着法
により銅層からなる第2導電層を形成することを特徴と
するフィルムキャリア装置の製造方法が提供される。以
下図面に基づき、本発明をさらに詳細に説明する。According to the present invention, there is provided, in accordance with the present invention, first and second conductive layers on both surfaces of an insulating layer, and these conductive layers are electrically connected via via holes. A method for manufacturing a film carrier device connected to a first conductive layer , wherein the first conductive layer is formed on one surface of the insulating layer.
After attaching the copper foil, the inside of the via hole is covered with the insulating layer.
When it is formed by protruding to near the height of the other surface of
Both of the protrusions of the first conductive layer protruding into the via hole.
Vacuum evaporation method on the surface in the outgoing direction and the other surface of the insulating layer
Forming a second conductive layer made of a copper layer by the method described above. Hereinafter, the present invention will be described in more detail with reference to the drawings.
【0008】本発明において第1導電シート層としては
銅箔シート、銅合金(Cu−Zr、Cu−Sn合金等)
箔シート、42合金(Fe−42%Ni合金)箔シート
などが挙げられる。第1導電シート層の厚さは通常10
〜150μmである。また、絶縁層3は商品名カプトン
D、カプトンH、ユーピレックスSなどで知られるポリ
イミドフィルム、ガラスエポキシ、BTレジンポリエス
テルフィルム等が挙げられるが、通常ポリイミドフィル
ムが好んで用いられる。絶縁層の厚さは通常15〜15
0μmである。In the present invention, a copper foil sheet, a copper alloy (Cu-Zr, Cu-Sn alloy, etc.) is used as the first conductive sheet layer.
Foil sheets, 42 alloy (Fe-42% Ni alloy) foil sheets, and the like. The thickness of the first conductive sheet layer is usually 10
150150 μm. The insulating layer 3 may be a polyimide film known as Kapton D, Kapton H, Iupirex S, or the like, a glass epoxy, a BT resin polyester film, or the like. Usually, a polyimide film is preferably used. The thickness of the insulating layer is usually 15 to 15
0 μm.
【0009】バイアホールは、通常絶縁層にフォトレジ
スト層を形成し、それをマスクとしてヒドラジン等の液
中でフィルムシートの一部の領域をエッチングすること
により形成することができる。バイアホールの直径は通
常0.05mmから2.0mmの範囲にあることが好ま
しい。その理由としては、多層配線でしかも配線ピッチ
が狭くなる傾向にあるので2.0mmを越えるスペース
を確保するのが困難である。また直径が0.05mmよ
りも小さくなると本発明で使用する突き出し加工が実際
上困難となる。[0009] The via hole can be usually formed by forming a photoresist layer on an insulating layer, and etching a part of the film sheet in a liquid such as hydrazine using the photoresist layer as a mask. Preferably, the diameter of the via hole is usually in the range of 0.05 mm to 2.0 mm. The reason is that it is difficult to secure a space exceeding 2.0 mm because of the multilayer wiring and the tendency for the wiring pitch to be narrow. If the diameter is smaller than 0.05 mm, the protrusion used in the present invention becomes practically difficult.
【0010】本発明においては、例えば突き出し加工に
より、第1導電シート層を絶縁層の上面高さ付近まで突
き出す。突き出し高さは絶縁層の上面高さになるべく合
わせることが好ましい。突き出し加工は金属パンチ、刃
の無い回転ドリル押し付け、絞り加工、吸引成形等から
選ばれる手段により行なうことができるが、金属パンチ
あるいは金型による絞り加工によることが、突き出し加
工の作業能率と突き出し加工の信頼性の点で好ましい。[0010] In the present invention, the first conductive sheet layer is protruded to a vicinity of the upper surface of the insulating layer by, for example, a protruding process. It is preferable that the protruding height be adjusted to the height of the upper surface of the insulating layer as much as possible. The protruding process can be performed by means selected from a metal punch, a rotary drill without a blade, a drawing process, a suction forming process, and the like. It is preferable in terms of reliability.
【0011】第2の導電層は突き出した第1導電シート
層と共に絶縁層の上面に形成され、バイアホールを介し
て電気的に接続される。第2導電層は真空蒸着法により
形成される。蒸着金属としては銅、Ni下地銅、Ti下
地銅であるが銅であることが好ましい。なお、図5、6
の構造に示すように、バイアホールの側壁に沿った突き
出し加工により、突き出された銅箔シート1と真空蒸着
による銅層10の密着安定性を向上させることも可能で
ある。第2導電層が形成された後は常法によりレジスト
塗布、パターンニング、導電層のエッチングを行い、微
細配線の多層構造のフィルムキャリア装置を得ることが
できる。The second conductive layer is formed on the upper surface of the insulating layer together with the protruding first conductive sheet layer, and is electrically connected via via holes. The second conductive layer is formed by a vacuum deposition method.
It is formed. The metal deposited is copper, copper under Ni, or copper under Ti, but copper is preferred. 5 and 6
As shown in the above structure, it is also possible to improve the adhesion stability between the protruded copper foil sheet 1 and the copper layer 10 by vacuum deposition by protruding along the side wall of the via hole. After the second conductive layer is formed, resist coating, patterning, and etching of the conductive layer are performed by a conventional method to obtain a film carrier device having a multilayer structure of fine wiring.
【0012】[0012]
【実施例】以下、本発明を実施例に基づき具体的に説明
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on embodiments.
【0013】(実施例1)直径300μmのバイアホー
ルが形成された厚さ100μmの絶縁層(ポリイミド:
宇部興産社製、商品名ユーピレックスS)3にエポキシ
系接着剤2で厚さ25μmの銅箔シート1を貼り合わせ
た。次いで金属パンチ(パンチ径200μm)でバイア
ホール80個の突き出し加工を行ない、銅箔シート層1
を絶縁層3の上面高さまで突き出した。図1は突き出し
加工された構造を示す。次いでこの構造の絶縁層3の上
面に真空蒸着法で厚さ4μmの銅層10を形成し、その
後レジスト塗布、パターンニング、銅層のエッチングを
行い、微細配線の2層構造のフィルムキャリア装置を作
成した。銅箔シート1と銅層10とが接続された構造を
図2に示す。比較のため、同じ構成のバイアホールに、
スパッタ法で厚さ4μmの銅膜5を形成した(図7参
照)。両者の初期抵抗のばらつきを調べたところ、実施
例1では初期抵抗のばらつきは±0.1Ω、比較例1の
ものは±1Ωであり、本発明のものはばらつきも小さく
安定していた。また、このフィルムキャリア装置を−5
0℃〜+150℃の温度サイクル試験を実施しながら接
続抵抗の推移を調べたところ、比較例1のフィルムキャ
リア装置よりも導通不可(バイアホールでの膜はがれに
よる断線)になる時間が2000時間と5倍長く、熱ス
トレスに対する信頼性が大幅に向上した。(Example 1) An insulating layer (polyimide: 100 μm thick) in which a via hole having a diameter of 300 μm was formed.
A copper foil sheet 1 having a thickness of 25 μm was bonded to an Ube Industries product, trade name IUPIREX S) 3 with an epoxy adhesive 2. Next, 80 via holes are protruded with a metal punch (punch diameter: 200 μm) to form a copper foil sheet layer 1.
To the upper surface of the insulating layer 3. FIG. 1 shows the structure that has been protruded. Next, a copper layer 10 having a thickness of 4 μm is formed on the upper surface of the insulating layer 3 having this structure by a vacuum evaporation method, and thereafter, a resist coating, patterning, and etching of the copper layer are performed. Created. FIG. 2 shows a structure in which the copper foil sheet 1 and the copper layer 10 are connected. For comparison, in the via hole of the same configuration,
A copper film 5 having a thickness of 4 μm was formed by a sputtering method (see FIG. 7). When the variation in the initial resistance was examined, the variation in the initial resistance in Example 1 was ± 0.1Ω, the variation in Comparative Example 1 was ± 1Ω, and the variation of the present invention was small and stable. In addition, this film carrier device is -5
When the transition of the connection resistance was examined while performing a temperature cycle test from 0 ° C. to + 150 ° C., it took 2,000 hours to conduct without conduction (disconnection due to film peeling at the via hole) than the film carrier device of Comparative Example 1. Five times longer, the reliability against thermal stress has been greatly improved.
【0014】(実施例2)厚さ25μmの銅箔シート7
にエポキシ系接着剤層6を介して厚さ75μmのポリイ
ミド絶縁層(商品名:ユーピレックスS)3を貼り合わ
せた後、径200μmのスルーホールを打ち抜いた。次
いで他方の面にエポキシ系接着剤層2を介して厚さ25
μmの銅箔シート1を貼り合わせ、金属パンチで該銅箔
シート1をスルーホールの上面まで突き出し加工を同時
に80箇所行なった。図3は突き出しを終えた構造の断
面図を示す。次いで、突き出し加工した銅箔シート1と
反対側の銅箔シート7の上に真空蒸着法により、厚さ2
5μmの銅層10を形成した。さらにレジスト塗布、パ
ターンニングを行い、銅層をエッチングし、2層微細配
線構造のフィルムキャリア装置を製作した。この場合ス
ルーホール構造と異なりバイアホールのため他面の裏止
めレジストが表面に流れることがないため、作業効率が
向上した。このフィルムキャリア装置を−50℃〜+1
50℃の温度サイクル試験(30分保持)を実施しなが
ら接続抵抗の推移を調べたところ、比較例1のものと比
較して初期抵抗のばらつきも小さく導通不可になる時間
が2000時間と10倍長く、熱ストレスに対する信頼
性が大幅に向上した。Example 2 Copper foil sheet 7 having a thickness of 25 μm
A polyimide insulating layer (trade name: Upilex S) 3 having a thickness of 75 μm was bonded thereto via an epoxy-based adhesive layer 6, and then a through-hole having a diameter of 200 μm was punched. Then, on the other surface, a thickness of 25
The copper foil sheet 1 having a thickness of μm was attached thereto, and the copper foil sheet 1 was protruded to the upper surface of the through hole by a metal punch, and 80 places were simultaneously processed. FIG. 3 shows a cross-sectional view of the structure after the protrusion. Next, the copper foil sheet 7 on the opposite side of the protruded copper foil sheet 1 is vacuum-evaporated to a thickness of 2 mm.
A 5 μm copper layer 10 was formed. Further, resist coating and patterning were performed, and the copper layer was etched to produce a film carrier device having a two-layer fine wiring structure. In this case, unlike the through hole structure, the backing resist on the other surface does not flow to the surface due to the via hole, so that the working efficiency is improved. This film carrier device is set at -50 ° C to +1
The transition of the connection resistance was examined while performing a temperature cycle test at 50 ° C. (holding for 30 minutes). Longer, significantly improved reliability against thermal stress.
【0015】温度サイクル(熱ストレス)試験法:バイ
アホールを介して電気的に接続したフィルムキャリア装
置をEIAJ(Electronic Industries Association of
Japan :社団法人日本電子機械工業会)の規格に準拠
し、二葉科学製冷熱サイクルの試験機を用い、−50℃
に30分間保った後、昇温速度120℃/分で150℃
に昇温し、30分間保つ。次いで降温速度−30℃/分
で−50℃とする。このサイクルを繰り返し、導通が不
可になる時間を調べた。なお試験数48の平均値で求め
た。Temperature cycle (heat stress) test method: A film carrier device electrically connected through a via hole is connected to an EIAJ (Electronic Industries Association of
Japan: -50 ° C using a Futaba Scientific Cooling / Heat Cycle Tester in accordance with the standards of the Japan Electronic Machinery Manufacturers Association.
After 30 minutes at 150 ° C at a rate of 120 ° C / min.
And keep for 30 minutes. Next, the temperature is lowered to -50 ° C at a temperature lowering rate of -30 ° C / min. This cycle was repeated to determine the time at which conduction was disabled. In addition, it calculated | required by the average value of 48 tests.
【0016】[0016]
【発明の効果】本発明は以上説明したように構成されて
いるので、本発明によって提供されるフィルムキャリア
装置は突き出し部で確実にバイアホールを介して第1お
よび第2導電層の接続ができるため、熱ストレスに対す
る信頼性が向上した。また、バイアホールが2.0mm
より小径のもの程第1導電シート層(銅箔層)も薄くで
き、本発明による突き出し加工が容易で、確実にバイア
ホールを介しての接続ができる。さらに、工業的な量産
性にも優れている。Since the present invention is configured as described above, the film carrier device provided by the present invention can reliably connect the first and second conductive layers via the via holes at the protruding portions. Therefore, reliability against heat stress has been improved. Also, the via hole is 2.0mm
The smaller the diameter, the thinner the first conductive sheet layer (copper foil layer), the easier the protruding process according to the present invention, and the more reliable the connection via the via hole. Furthermore, it is excellent in industrial mass productivity.
【図1】本発明の実施例1の導電層を突き出した段階の
構造を示す断面図である。FIG. 1 is a cross-sectional view showing a structure at a stage where a conductive layer is protruded according to a first embodiment of the present invention.
【図2】本発明の実施例1の電気的接続を終えた段階の
構造を示す断面図である。FIG. 2 is a cross-sectional view illustrating a structure at a stage after the electrical connection according to the first embodiment of the present invention is completed.
【図3】本発明の実施例2の導電層を突き出した段階の
構造を示す断面図である。FIG. 3 is a cross-sectional view showing a structure at a stage where a conductive layer is protruded according to a second embodiment of the present invention.
【図4】本発明の実施例2の電気的接続を終えた段階の
構造を示す断面図である。FIG. 4 is a cross-sectional view showing a structure at a stage after an electrical connection according to a second embodiment of the present invention has been completed.
【図5】本発明の別の突き出し加工の実施態様を示す断
面図である。FIG. 5 is a cross-sectional view showing another embodiment of the protrusion processing of the present invention.
【図6】本発明の別の実施態様であり、図5の突き出し
た構造に電気的接続を終えた段階の構造を示す断面図で
ある。FIG. 6 is a cross-sectional view of another embodiment of the present invention, showing the structure at the stage when electrical connection to the protruding structure of FIG. 5 has been completed.
【図7】従来のスパッタ法により電気的に接続した構造
を示す断面図である。FIG. 7 is a cross-sectional view showing a structure electrically connected by a conventional sputtering method.
【図8】従来のめっき法により電気的に接続した構造を
示す断面図である。FIG. 8 is a cross-sectional view showing a structure electrically connected by a conventional plating method.
1 銅箔シート(第1導電シート層) 2 接着剤層 3 絶縁層 4 バイアホール 5 銅膜層 6 接着剤層 7 銅箔シート層 8 スルーホール 9 めっき層 10 銅層(第2導電層) REFERENCE SIGNS LIST 1 Copper foil sheet (first conductive sheet layer) 2 Adhesive layer 3 Insulating layer 4 Via hole 5 Copper film layer 6 Adhesive layer 7 Copper foil sheet layer 8 Through hole 9 Plating layer 10 Copper layer (second conductive layer)
───────────────────────────────────────────────────── フロントページの続き (72)発明者 御 田 護 茨城県日立市助川町3丁目1番1号 日 立電線株式会社 電線工場内 (72)発明者 高 城 正 治 茨城県日立市助川町3丁目1番1号 日 立電線株式会社 電線工場内 (72)発明者 村 上 富 男 茨城県日立市助川町3丁目1番1号 日 立電線株式会社 電線工場内 (56)参考文献 特開 平3−95947(JP,A) 特開 平4−10552(JP,A) 特開 平2−180041(JP,A) 特開 平5−21538(JP,A) (58)調査した分野(Int.Cl.6,DB名) H01L 21/60 311──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor: Mamoru Mita 3-1-1, Sukekawa-cho, Hitachi-shi, Ibaraki Pref. Inside the cable plant at Hitachi Cable Co., Ltd. (72) Inventor: Masaharu Takagi, Sukegawa-cho, Hitachi-shi, Ibaraki 3-1-1, Hitachi Cable Co., Ltd. Wire Plant (72) Inventor Tomio Murakami 3-1-1, Sukekawa-cho, Hitachi City, Ibaraki Prefecture Hitachi Cable Corporation Wire Plant, (56) References JP JP-A-3-95947 (JP, A) JP-A-4-10552 (JP, A) JP-A-2-180041 (JP, A) JP-A-5-21538 (JP, A) (58) Fields studied (Int) .Cl. 6 , DB name) H01L 21/60 311
Claims (1)
し、これらの導電層間がバイアホールを介して電気的に
接続されてなるフィルムキャリア装置の製造方法であっ
て、前記第1導電層を、前記絶縁層の一方の面に銅箔を貼り
付けた後、前記 バイアホール内を当該絶縁層の他方の面
の高さ付近まで突き出し加工して形成すると共に、 前記バイアホール内に突き出した第1導電層の突出方向
の表面および前記絶縁層の他方の面に真空蒸着法により
銅層からなる第2導電層を形成する ことを特徴とするフ
ィルムキャリア装置の製造方法。1. A method for manufacturing a film carrier device comprising: a first and a second conductive layer on both surfaces of an insulating layer, wherein the conductive layers are electrically connected via via holes . (1) a conductive layer, and a copper foil on one surface of the insulating layer
After attaching, the inside of the via hole is covered with the other surface of the insulating layer.
And a protrusion direction of the first conductive layer protruding into the via hole.
By vacuum evaporation on the surface of
A method for manufacturing a film carrier device , comprising forming a second conductive layer made of a copper layer .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3176598A JP2757593B2 (en) | 1991-07-17 | 1991-07-17 | Manufacturing method of film carrier device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3176598A JP2757593B2 (en) | 1991-07-17 | 1991-07-17 | Manufacturing method of film carrier device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0521537A JPH0521537A (en) | 1993-01-29 |
JP2757593B2 true JP2757593B2 (en) | 1998-05-25 |
Family
ID=16016373
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3176598A Expired - Lifetime JP2757593B2 (en) | 1991-07-17 | 1991-07-17 | Manufacturing method of film carrier device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2757593B2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0154994B1 (en) * | 1993-11-22 | 1998-12-01 | 세끼자와 다다시 | Semiconductor device and its manufacture |
US6111306A (en) | 1993-12-06 | 2000-08-29 | Fujitsu Limited | Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same |
US5679978A (en) * | 1993-12-06 | 1997-10-21 | Fujitsu Limited | Semiconductor device having resin gate hole through substrate for resin encapsulation |
DE10044541C1 (en) * | 2000-09-05 | 2002-02-14 | Siemens Ag | Producing electrically conducting layers on through hole walls in substrate involves deep drawing plastic foil with metal layer in substrate, removing foil from metal layer with conical tools |
JP3096172U (en) | 2003-02-27 | 2003-09-05 | アルプス電気株式会社 | Television tuner |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0395947A (en) * | 1989-09-07 | 1991-04-22 | Toshiba Corp | Semiconductor integrated circuit packaging device and manufacture thereof |
JPH0410552A (en) * | 1990-04-27 | 1992-01-14 | Nec Corp | Semiconductor package tab tape |
-
1991
- 1991-07-17 JP JP3176598A patent/JP2757593B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0521537A (en) | 1993-01-29 |
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Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19980210 |