JPH0521471B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timing pulse generation circuit, and particularly to processing of a vertical synchronization signal of a television signal.

[Conventional technology]

Television equipment often requires vertical synchronization, such as the timing of video switching.
For this reason, although it may be supplied as a vertical drive pulse, it is generally supplied as a composite synchronization signal due to the system configuration. Correspondingly, it is necessary to extract the vertical synchronization pulse from the composite synchronization signal within the device.

As shown in Fig. 4, the conventional method for extracting vertical synchronization pulses is to integrate the pulse by a low-pass filter 11 and then input it to a comparator or logic IC 1.
2 and converting it into a vertical synchronizing pulse is relatively simple and often used. FIG. 5 shows the waveform diagram.

[Problem that the invention seeks to solve]

However, as can be seen in Figure 5b, with this method, the phase of the pulse extracted for slicing the integral waveform is considerably delayed, and due to variations and fluctuation factors in the filter constant, comparator, or logic IC.
It is difficult to keep this delay amount within a certain range. This is a problem when a relatively early phase of the vertical synchronization pulse is required, or when driving other devices with the same circuit using the vertical synchronization pulse obtained from the first stage device as shown in Figure 6. becomes.

Another method is to use a monomulti and a flip-flop to set the pulse width triggered by the input sync between the equalization pulse and the vertical notch pulse, and use this pulse to latch the input sync. Although the amount of delay is relatively small and stable vertical pulses can be obtained, it cannot be used when the input is vertical synchronization, making it difficult to share the circuit.

[Means for solving problems]

The present invention includes a first mono multivibrator that detects a vertical cut pulse or vertical synchronization, a flip-flop receiving the output thereof, a second mono multivibrator triggered by the flip-flop output, and a second mono multivibrator output. This is a timing pulse generation circuit that takes out an output from the flip-flop and has means for setting the flip-flop by the AND of the input synchronization and the input synchronization.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. The first mono multivibrator 1 is triggered by the falling edge of the synchronization input and is supplied as a clock to the flip-flop 2. The flip-flop 2 latches the synchronization input according to the timing of this clock, and at the same time obtains a timing pulse output. Multi 4 is triggered and its output is ANDed with the input sync by gate 3 to set flip-flop 2.

Figure 2 is a timing diagram showing the operation in the case of composite synchronous input in Figure 1. Figure 3 is a timing diagram showing the operation in the case of vertical synchronous input as well, where a is the input, b is the first mono multivibrator, and c is the flip-flop. 2 output, d is the second mono multivibrator 4
In the output of , e indicates the output of gate 3.

First, in the case of a composite synchronous input, the pulse width of the output of the first monomultivibrator 1 is wider than the equalization pulse or the horizontal synchronous pulse, but narrower than the vertical notch pulse, and the flip-flop 2 is latched at the trailing edge of this output pulse. The output is at a low level during the vertical cut pulse period and at a high level at other times. In addition, in the case of vertical synchronization input, the first mono multivibrator 1 is triggered only by the leading edge of the input,
As a result, the flip-flop 2 becomes a low level, and the flip-flop 2 is set by the AND of the output of the second monomultivibrator 4 and the input synchronization, and becomes a high level.

〔Effect of the invention〕

As explained above, the present invention obtains stable vertical synchronization with a relatively small amount of delay by latching the input synchronization signal with a flip-flop using a clock delayed by a mono-multivibrator. By setting a flip-flop with the AND of the output of the mono-multivibrator and the input synchronization signal, a timing pulse generation circuit that can handle both composite synchronization input and vertical synchronization can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
2 is a timing diagram showing the operation in the case of composite synchronous input in FIG. 1, FIG. 3 is a timing diagram showing the operation in the case of vertical synchronous input in FIG. 1,
Fig. 4 is a block diagram showing a conventional example, and Fig. 5 is a block diagram showing a conventional example.
FIG. 6 is a waveform diagram showing the operation in the figure, and FIG. 6 is a diagram showing an example of connection between a plurality of devices. In the figure, 1...first mono multivibrator, 2...flip-flop, 3...gate, 4
...Second mono multivibrator, 11...
Low-pass filter, 12... Comparator or logic IC, 21-24... Device requiring vertical synchronization pulse.

Claims (1)

[Claims] 1. A first mono multivibrator that receives a composite synchronization signal or a vertical synchronization signal and is triggered at the falling edge of the input signal, and uses the trailing edge of the output of the first mono multivibrator as a clock to latch the input signal. a flip-flop that outputs an output as a timing pulse; a second mono multivibrator triggered by the output of the flip-flop; ANDing the output of the second mono multivibrator and the input signal; 1. A timing pulse generation circuit comprising: a gate for setting a timing pulse;