JPH05211277A - Package for high output transistor - Google Patents

Abstract

PURPOSE:To reduce the number of components of a package for a high output transistor and the causes of an irregularity in characteristics and to effectively utilize an occupying area in the package. CONSTITUTION:A lead section 7, a semiconductor chip 4 and a chip capacitor 5 are mounted on a metallized surface of an integrated dielectric part 1. The chip 4 is grounded via a through hole 3. Thus, a reduction in the number of components of the package for the transistor, deletion of mounting and bonding steps, a decrease in causes of an irregularity in characteristics and an increase in the degree of freedoms of an inner alignment are realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hermetic package for high power transistors.

[0002]

2. Description of the Related Art A conventional high-power transistor package will be described with reference to the plan view of FIG. 4A and the sectional view taken along the line AB of FIG.

A protrusion for mounting a semiconductor chip is formed at the center of a metal portion 6 which serves as a heat dissipation plate. The dielectric portion 1 is metallized so that the lead portion 7 has a resistance of 50Ω.

A state in which circuit components are mounted on a conventional package will be described with reference to the plan view of FIG. 5A and the sectional view of FIG. 5B.

All the circuit components are mounted on the metal portion 6, and the back surface of the semiconductor chip 4 is grounded by the mount. Normally, the dielectric substrate 9 for internal matching and the dielectric 1 connecting the lead portion 7 are made of the same material. The dielectric portion 1 made of ceramic is relayed from the semiconductor chip 4 by the bonding wire 8 to be electrically connected to the lead portion 7.

[0006]

In the high power transistor package, the dimensional error of the circuit parts is 50-100 at maximum.
μm.

As shown in FIG. 5A, when the circuit components are mounted on the package, dimensional errors of the chip capacitor 5, the dielectric substrate 9 and the package body overlap. The maximum dimensional error for each of the input and output is 350 μm, which causes a variation in characteristics.

When mounting the circuit components, an interval of about 500 μm is required. A wasteful part is generated in the area occupied by the package, and the area of the dielectric for internal matching is limited.

[0009]

A high-power transistor package of the present invention is one in which a dielectric substrate for internal matching and a dielectric substrate for mounting external leads are integrally formed.

[0010]

EXAMPLE FIG. 1A shows a first example of the present invention.
Will be described with reference to a plan view of FIG.

The dielectric 1 includes a mount portion for a semiconductor chip or a chip capacitor, and an internal matching circuit as a metallized portion 2.
Is formed by. The central mount portion is grounded through the through hole 3. The metallized portion 2 extends to the lead portion 7.

FIG. 2 (a) is a plan view of a circuit component mounted on this package, and FIG.
It shows in (b). The number of components of the package is reduced as compared with the conventional ones shown in FIGS. In addition, the space provided in consideration of the workability of the mount is no longer necessary, the dielectric expands, and the degree of freedom of internal alignment increases.

Next, regarding the second embodiment of the present invention, FIG. 3 is a plan view of FIG. 3A and a sectional view taken along the line AB.
This will be described with reference to (b). Since the metal portion 6 is exposed only in the portion for mounting the semiconductor chip or the chip capacitor in the center of the package, the heat radiation effect is improved as compared with the first embodiment.

[0014]

The dielectric substrate for internal matching and the dielectric in the package are integrally formed. As a result, the effects of reducing the number of components of the package, reducing the mounting and bonding man-hours, reducing the characteristic variation, and increasing the degree of freedom of internal matching are provided.

[Brief description of drawings]

FIG. 1A is a plan view showing a package of a first embodiment of the present invention. (B) is an AB sectional view of (a).

FIG. 2A is a plan view showing a state in which circuit components are mounted on the package according to the first exemplary embodiment of the present invention. (B) is an AB sectional view of (a).

FIG. 3A is a plan view showing a package of a second embodiment of the present invention. (B) is an AB sectional view of (a).

FIG. 4A is a plan view showing a conventional package. (B) is an AB sectional view of (a).

FIG. 5A is a plan view showing a state in which circuit components are mounted on a conventional package. (B) is an AB sectional view of (a).

[Explanation of symbols]

 1 Dielectric Part 2 Metallized Part 3 Through Hole 4 Semiconductor Chip 5 Chip Capacitor 6 Metal Part 7 Lead Part 8 Bonding Part 9 Dielectric Substrate for Internal Matching

Claims (1)

[Claims] 1. A package for a high power transistor in which a dielectric substrate for internal matching and a dielectric substrate for mounting external leads are integrally formed.