JPH05210913A - Data reproducing circuit and data storage device using its circuit - Google Patents

Abstract

PURPOSE:To set the reference level of amplitude detection to an optimum value to prevent the error in the data reproducing circuit in the peak detection system using the amplitude detection as well. CONSTITUTION:The reference voltage of a level slicing circuit 7 is set by a level slice control circuit 10. An error detecting circuit 9 detects the error of a data pulse signal 107 demodulated by a data demodulating circuit 8 and outputs an error detection signal 108 to the level slice control circuit 10. This circuit 10 changes a level slice reference voltage 109 as the threshold of the level slicing circuit 7 and obtains the error occurrence rate from the error detection signal 108 and sets the level slice reference voltage 109 to such value that the error occurrence rate is minimum.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproducing circuit, and more particularly to a data reproducing circuit for reproducing data using a peak detecting circuit used in a data storage device.

[0002]

2. Description of the Related Art In a conventional data storage device, as a peak detection circuit used in a data reproducing circuit, a reproduction signal read from a magnetic head is amplified to an appropriate amplitude, and then an equalizer (equalizer) and a low-pass filter. The reproduced signal is equalized and the noise is suppressed by the differential circuit, then differentiated by the differentiating circuit, and the peak detection signal which is a pulse is generated by the zero-cross comparator according to the peak position of the reproduced signal. However, this peak detection signal also includes pulses other than the peak, such as the saddle portion of the differential signal. And to remove the pulses other than this peak,
A read pulse signal, which is a true peak signal of the reproduced signal, is generated by a sequential circuit such as a flip-flop circuit from the gate signal and the peak detection signal, which is generated by comparing the reproduced signal with an appropriate reference voltage by a level slice circuit. To make.

The read pulse signal is demodulated by the data demodulation circuit into the original data by the clock synchronized with the data. Here, the lower limit of the reference voltage applied to the level slice circuit is a voltage that does not detect noise and the shoulder portion of the reproduced signal, and the upper limit is selected as a voltage that can detect the drop of the reproduced signal.

[0004]

However, in the peak detection circuit of the conventional magnetic memory device as described above, the level slice voltage is fixed. Therefore, when the reference voltage is not optimum, the peak level may vary depending on the characteristics of the reproduction signal. When there is not enough margin, there is a problem that the probability of error occurrence increases due to the fluctuation of the waveform.

[0005]

SUMMARY OF THE INVENTION A data reproducing circuit of the present invention detects a differential circuit for differentiating an equalized signal whose reproduced waveform is equalized, and a zero cross of the differentiated signal output from the differentiating circuit. A zero-crossing comparator that outputs a peak detection signal, a level slice circuit that outputs a gate signal by comparing the equalized signal and a reference voltage, and a true peak value of a reproduced waveform from the peak detection signal and the gate signal. A peak detection circuit that detects and outputs a read pulse signal,
A data demodulation circuit that demodulates the original recording data from the read pulse signal and outputs a data pulse signal, an error detection circuit that detects an error of the data pulse signal and outputs an error detection signal, and a data detection circuit that outputs data from the error detection signal. A level slice control circuit for calculating an error occurrence rate, storing the result in a RAM, and varying the reference voltage of the level slice circuit.

A data storage device using this data reproducing circuit is characterized in that the level slice reference voltage of the level slice circuit is determined so that the error rate is minimized.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the data reproducing circuit of the present embodiment, as shown in FIG. 1, a reproducing AMP (reproducing amplifier) 2 amplifies the reproducing signal A100 read from the magnetic head 1 to an appropriate amplitude, and automatically reproduces it as a reproducing signal B101. A circuit consisting of a controller, an equalizer (equalizer), and a low-pass filter (hereinafter,
(Abbreviated as AGC + EQLZ + LPF) 3).
(AGC + EQLZ + LPF) 3 is a reproduction signal B101
To output the equalized signal 102 to the differentiating circuit 4 and the level slice circuit 7. The differentiating circuit 4 uses the equalized signal 10
2 is input and the differentiated signal 103 is output to the zero-cross comparator 5. The zero-cross comparator 5 inputs the differentiated signal 103 and outputs the peak detection signal 104 to the flip-flop circuit 6. Level slice circuit 7
Is the equalized signal 102 and the level slice reference voltage 109
And the gate signal 105 is output to the flip-flop circuit 6.

The flip-flop circuit 6 inputs the peak detection signal 104 and the gate signal 105 and outputs a read pulse signal 106 to the data demodulation circuit 7. The data demodulation circuit 8 inputs the read pulse signal 106 and outputs the data pulse signal 107 to the error detection circuit 9. The error detection circuit 9 inputs the data pulse signal 107 and outputs an error detection signal 108 to the level slice control circuit 10. The level slice control circuit 10 inputs the error detection signal 108 and the level slice control signal 111 and outputs the level slice reference voltage 109 to the level slice circuit 7.
Output to. The level slice control circuit 10 also transfers the slice level data 110 to and from the RAM 11.

Next, the operation of the data reproducing circuit of this embodiment will be described.

First, the reproduction AMP2 amplifies the reproduction signal A100 read from the magnetic head 1 to an appropriate amplitude, and outputs it as a reproduction signal B101 (AGC + EQLZ + LP).
F) Output to 3. (AGC + EQLZ + LPF) 3
Performs waveform equalization and noise reduction on the reproduced signal 101 by EQLZ and LPF so as to reduce peak shift and jitter, and outputs the equalized signal 102. The differentiating circuit 4 differentiates the equalized signal 102 and outputs a differentiated signal 103. The differentiated signal 103 is compared by the zero-cross comparator 5 at the zero-cross point of the differentiated signal 103, and the peak detection signal 104 corresponding to the zero-cross position is output to the flip-flop circuit 6.

As a result, the peak detection signal 104 becomes a pulse signal corresponding to the peak of the equalized signal 102.
Since a pulse other than the peak such as a saddle part of the differential signal is also included, the equalized signal 102 is compared with the level slice reference voltage 109 which is an appropriate reference voltage by the level slice circuit 7 in order to remove it. 105
To make. The gate signal 105 and the peak detection signal 10
4, the read pulse signal 106, which is the true peak of the reproduced signal, is generated by the sequential circuit of the flip-flop circuit 6. The read pulse signal 106 generates a reference clock synchronized with the data by the data demodulation circuit 8 and is demodulated to the original data by the reference clock to output the data pulse signal 107. The data pulse signal 107 is judged by the error detection circuit 9 whether or not there is a read error in the data pulse by the error detection means using a cyclic redundancy check code (CRC), an error correction code (ECC), etc. The result is output to the level slice control circuit 10 as the error detection signal 108. The level slice control circuit 10 outputs the level slice reference voltage 109 for the level slice of the level slice circuit 7 to the level slice circuit 7. Here, when the level slice control circuit 10 receives the level slice control signal 11, it changes the level slice reference voltage 109 to a value higher or lower than the value of the set voltage. At this time, the error occurrence rate is detected from the error detection signal 108 and stored in the RAM 11.

By thus detecting the error occurrence rate while changing the level slice reference voltage, it is possible to obtain the level slice reference voltage that minimizes the error occurrence rate. Further, in the data storage device using this data reproducing circuit, the optimum value of the level slice reference voltage differs depending on the difference between the head and the cylinder. Therefore, as described above, each head and cylinder is based on the error occurrence rate. The optimum value can always be set for and. Further, it is possible to automatically adjust the reference voltage of the level slice.

[0014]

As described above, the data reproducing circuit of the present invention can determine the error occurrence rate while changing the reference voltage of the level slice, and can always set the optimum level slice reference voltage from the result. The optimum setting can be made even for the difference in the characteristics of the reproduction signal, and there is an effect that the occurrence of an error can be suppressed and the reliability of the data can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

[Explanation of symbols]

1 magnetic head 2 reproduction AMP (reproduction amplifier) 3 AGC + EQLZ + LPF (circuit consisting of automatic gain controller, equalizer (equalizer), low-pass filter) 4 differentiation circuit 5 zero cross comparator 6 flip-flop circuit 7 level slice circuit 8 data demodulation circuit 9 Error detection circuit 10 Level slice control circuit 11 RAM 100 Playback signal A 101 Playback signal B 102 Equalized signal 103 Differentiated signal 104 Peak detection signal 105 Gate signal 106 Read pulse signal 107 Data pulse signal 108 Error detection signal 109 Level slice reference Voltage 110 Slice level data 111 Level slice control signal

Claims (2)

[Claims] 1. A differentiating circuit for differentiating an equalized signal whose reproduced waveform is equalized, a zero-cross comparator for detecting a zero-cross of the differentiated signal output from the differentiating circuit and outputting a peak detection signal, and the like. A level slice circuit that outputs a gate signal by comparing the converted signal with a reference voltage; and a peak detection circuit that outputs a read pulse signal by detecting the true peak value of the reproduced waveform from the peak detection signal and the gate signal. A data demodulation circuit that demodulates the original recording data from the read pulse signal and outputs a data pulse signal,
An error detection circuit that detects an error in the data pulse signal and outputs an error detection signal, an error occurrence rate of data is calculated from the error detection signal, and the result is stored in a RAM and a reference voltage of the level slice circuit is stored. A data reproducing circuit comprising a variable level slice control circuit. 2. A data storage device using the data reproduction circuit according to claim 1, wherein the level slice reference voltage of the level slice circuit is determined so as to minimize an error occurrence rate. Data storage device.