JPH04315876A - Data regenerating processor - Google Patents

Abstract

PURPOSE:To suppress a code error rate to the minimum without being affected by noise by varying the prescibed constant of a digital data regenerating means based on the code error rate detected with a demodulation process means adn adjusting the code error rate. CONSTITUTION:By a controller 15 constituted of a microcomputer, the code error rate of demodulative digital signal demodulated by a demodulation process circuit 14 is supervised normally. Then, the slice level of a level comparator 8 is controlled variabloy in accordance with the code error rate and adjusted so that the code error rate is minimum. By this configuration, an extra pulse generated by detecting erroneously the noise distributing in the vicintiy of a reference slice level is dissolved and the code error rate is suppressed to the minimum.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data reproduction processing apparatus for reproducing digital data from an information recording medium.

0002

2. Description of the Related Art FIG. 5 is a block diagram showing a conventional data reproduction processing device for pit position recording. In the figure, reference numeral 1 denotes a photoelectric converter for receiving reflected light from an optical disk (not shown) used as an information recording medium and converting it into an electrical signal. Further, a head amplifier circuit is constituted by a resistor 2 and an amplifier 3, and a current signal of the photoelectric converter 1 is converted into a voltage signal to generate a reproduction signal. 4 is an equalizer circuit for correcting the frequency characteristics of the reproduced signal, 5 is a low-pass filter (hereinafter abbreviated as LPF) for removing high frequency noise superimposed on the reproduced signal, and 6 is a differentiation circuit for differentiating the reproduced signal. Also, 7
8 is a zero-crossing comparator for detecting the zero-crossing point of the differential signal of the differentiating circuit 6 and detecting the center position of the recording pit; 8 is a level comparator for slicing the reproduced signal at a predetermined level and generating a window pulse; 10
is an AND circuit that performs the logical product of the zero-cross signal and the window pulse and outputs encoded data. 11 is a PLL that extracts the recovered clock from the end code data.
A circuit 12 is a synchronization circuit that samples encoded data using this reproduced clock, and a PLL circuit 11
, a synchronization circuit 12 constitute a data separation circuit 13. Further, 14 is a demodulation processing circuit that demodulates the information data of the synchronization circuit 12 into codes etc. based on the reproduced clock.

Next, the operation of the data reproduction processing device will be explained with reference to a time chart shown in FIG. Note that (a) in the same figure shows recorded data when information is recorded, and (b) in the same figure shows recording light pulses irradiated onto the optical disk based on this recorded data. This recording pulse records recording pits on the optical disc as shown in FIG. 2(c).

When reproducing information, a light beam for reproduction is irradiated onto the optical disk from a light source (not shown), and the reflected light is incident on the photoelectric converter 1 through the reproduction optical system. The reproduced light is converted into a current by a photoelectric converter 1, and further converted into a voltage signal by a head amplifier circuit including a resistor 2 and an amplifier 3. The reproduced signal thus obtained is compensated by the equalizer circuit 4 for high-frequency signal components lowered by the reproduction optical system, and the LPF 5 removes pulse noise. Figure 6
(d) is the output signal of the LPF 5, which is a Gaussian pulse signal whose high-frequency components have deteriorated due to the influence of the MTF of the reproduction optical system compared to the recorded data in (a) of the figure. Note that the peak position of this Gaussian signal coincides in timing with the center position of the recording pit.

The output signal of the LPF 5 is differentiated by a differentiating circuit 6, and a differentiated signal is generated as shown in FIG. 2(e). Further, a zero-crossing point of this differential signal is detected by a zero-crossing comparator 7, and a zero-crossing signal S1 is generated as shown in FIG. In the zero-crossing signal S1, the rising edge of the pulse corresponds to the zero-crossing point of the differential signal, and also corresponds to the center position of the recording pit. Note that the logic of the zero-cross signal is undefined when no differential signal exists. On the other hand, the level comparator 8 slices the output signal of the LPF 5 at a predetermined slice level Vref to determine the presence or absence of a reproduced signal, and sends the obtained window signal S2 to the AND circuit 10 as shown in FIG. In this case, when the reproduced signal is at or above the slice level, the window signal becomes high level, which causes the AND circuit 10
is given as a window pulse. Then, the AND circuit 10 performs a logical product of the zero cross signal S1 and the window signal S2, and generates encoded data S3 as shown in FIG. The encoded data S3 is sent to the data separation circuit 13, where a reproduced clock is extracted and the encoded data is sampled. The demodulation processing circuit 14 also uses the synchronization circuit 1 based on the reproduced clock.
A process of demodulating the information data of No. 2 into a code or the like is performed.

[0006]

[Problems to be Solved by the Invention] However, in the conventional data reproduction processing device described above, an LPF is provided to limit the band of the signal transmission path in order to reduce the probability of occurrence of code errors that determine the quality of the system. However, if a code error occurs in the waveform shaping circuit that generates encoded data at the next stage, the code error is further transmitted to the demodulation processing circuit at the next stage. Furthermore, since the slice level of the level comparator that generates the window signal is fixed at a constant level, noise components distributed around the slice level as shown in FIG. 6(d) are caused by eccentricity of the disk and drive device. Depending on the situation, the slice level may or may not be crossed. Therefore, Figure 6 (
As shown in f), the window signal that is the output of the level comparator may or may not generate extra pulses, resulting in instability. In addition, when setting the slice level, it is difficult to set it unambiguously because of the margin for the noise level to prevent extra pulse generation and the margin for the playback signal to prevent data dropout. This also made it difficult to guarantee the compatibility of drive devices.

The present invention has been made to solve these problems, and its purpose is to provide a data reproduction processing device that is not affected by noise and can minimize the bit error rate. It is about providing.

[0008]

[Means for Solving the Problems] It is an object of the present invention to provide a means for binarizing a reproduced signal read from an information recording medium and reproducing it into digital data, and a means for demodulating the digital data. In the data reproduction processing device, a predetermined constant of the digital data reproduction means is varied based on the code error rate detected by the demodulation processing means, and adjustment is made so that the code error rate is minimized. This is achieved by a data reproduction processing device.

[0009]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a data reproduction processing device of the present invention. In FIG. 1, components having the same functions as those of the conventional device are denoted by the same reference numerals, and their explanation will be omitted in this embodiment.

In FIG. 1, 9 is a level comparator 8.
This is a D/A converter for setting the slice level of the control circuit 15, and converts the digital value sent from the control circuit 15 into an analog value to set the slice level. Control circuit 15
is composed of a microcomputer, and constantly monitors the code error rate of the demodulated digital signal demodulated by the demodulation processing circuit 14, and variably controls the slice level of the level comparator 8 in accordance with the code error rate. That is, since the code error rate is detected in the demodulation processing circuit 14, the control circuit 15 varies the slice level according to the code error rate and performs control so that the code error rate is minimized. . Note that the other configurations are exactly the same as the conventional device shown in FIG.

FIG. 2 is a diagram showing the relationship between the slice level of the level comparator 8 mentioned above and the bit error rate. As is clear from the figure, the bit error rate can be minimized by setting the slice level to the optimal value Vs. The present invention focuses on this point and attempts to adjust the slice level to an optimal value that minimizes the bit error rate.

The specific slice level adjustment operation of the control circuit 15 will be explained using the flowchart shown in FIG. Here, it is assumed that a reproducing light beam is irradiated onto an optical disk, which is an information recording medium, and in the embodiment shown in FIG. 1, the reflected light is detected to perform data reproducing processing as described above. In FIG. 3, first in step S1, the control circuit 15 sets the slice level to a predetermined level V.
1, and instructs the D/A converter 9 to set it to S2.
When this slice level is V1, demodulation processing circuit 1
The code error rate detected in step 4 is stored in the internal first memory area E.
Store in 1. Next, in S3, the internal counter is initialized, and in S4, the D/A converter 9 is instructed to step up the slice level from V1 to a higher potential by a predetermined potential. The control circuit 15 stores the code error rate detected at this time in S5 in an internal second memory area E2.
, and the counter is incremented in S6. After this, the control circuit 15 selects the first memory area E1 in S7.
and the second memory area E2 are compared, and E
It is determined whether the value of 1 is smaller than the value of E2. If it is determined that E1 is larger than E2, S8
The value of the second memory area E2 is transferred to the first memory area E1.
After storing the voltage, the process returns to S4 and the slice level is reset to further raise the potential by a predetermined potential. Then, S7 continues until the condition E1 < E2 is satisfied.
4 to S8 are repeated. That is, the control circuit 15 increases the slice level step by step by a predetermined potential, and compares the code error rate obtained each time with the previous code error rate. When E1 < E2, the slice level is as shown in Figure 2.
Since this is the time when the minimum value of the error rate curve shown in is exceeded, the operation of increasing the slice level is stopped at this point.

[0013] When the condition E1 < E2 is satisfied in this way, the control circuit 15 switches the level comparator 8 at S9.
The D/A converter 9 is instructed to step down the slice level by a predetermined potential lower than the current level, and it is determined in S10 whether the value of the internal counter is 2 or more. If the counter value is 2 or more, the slice level is held at the current level at this time. on the other hand,
If the counter value is less than 2, the control circuit 15
In step 11, the D/A converter 9 is instructed to step down by a predetermined potential to a lower potential than the current slice level, and in step S12, the code error rate at this time is stored in the third memory area E3. Next, in S13, the value of the first memory area E1 and the value of the third memory area E3 are compared, and it is determined whether the value of E1 is smaller than the value of E3. If it is determined that the value of E1 is larger than the value of E3, the control circuit 15 stores the value of the third memory area E3 in the first memory area E1 in S14, and returns to S11 again. Then, the processes of S11 to S14 are repeated until the condition of E1 < E3 is satisfied in S13. That is, the slice level is sequentially lowered one step at a time to the lower potential side, and the code error rate obtained each time is compared with the previous code error rate in the same way as described above. If E1 < E3, this means that the slice level has exceeded the minimum value of the error rate curve in FIG. 2, so the operation to lower the slice level is stopped and the process proceeds to S15. In S15, since the current slice level has shifted to the lower potential side than the optimum value, the control circuit 15 instructs the D/A converter 9 to shift the slice level by one step to the higher potential side. The level of is fixed as the slice level and the process ends. As a result, the slice level of the level comparator 8 is set to the optimum value V shown in FIG.
s, the error rate can be effectively reduced.

[0014] Here, the above slice level settings are as follows:
It may be performed all the time during the reproduction processing operation, or the demodulation processing circuit 1
This may be performed when the bit error rate detected in step 4 is equal to or higher than a predetermined value. In addition, implementation may be determined from the viewpoint of system reliability and throughput, such as when error correction becomes impossible.

FIG. 4 is a block diagram showing another embodiment of the present invention. This embodiment is an example in which a variable gain amplifier 18 is provided between the amplifier 3 and the equalizer circuit 4, and the amplitude level of the reproduced signal is optimally adjusted instead of adjusting the slice level. Variable gain amplifier 18 is connected to amplifier 16 and D/
The control circuit 15 is composed of an A converter 17 and a D/A converter 17.
The converter 17 is instructed to increase and decrease the gain of the amplifier 16 stepwise, and adjust the gain value to a value that minimizes the error rate. Therefore, by replacing the slice level with the gain of the amplifier 16 in the flowchart shown in FIG. 2, the gain value can be adjusted to minimize the error rate, and the bit error rate can be reduced as in the previous embodiment. Can be done.

It should be noted that the present invention is not limited to the embodiments described above, and it is also possible to use the embodiments shown in FIGS. 1 and 4 in combination, for example. That is, by first setting either the slice level or the gain to a value that minimizes the error rate, and then setting the other side so that the error rate is minimized,
Furthermore, the error rate can be reduced. Also, Figure 4
It is also possible to minimize the error rate by changing the equalizer constant of the equalizer circuit 4 to change the amount of waveform equalization, or by changing the filter constant of the LPF 5 to change the cutoff frequency, as shown in FIG. It is. Further, in the above embodiments, an optical disk reproducing apparatus has been described as an example, but the present invention is not limited to this, and can be widely applied to data reproducing apparatuses that reproduce digital data such as floppy disks, DATs, and 8mm VTRs.

[0017]

[Effects of the Invention] As explained above, the present invention has the following effects.

(1) The problem that extra pulses are generated due to erroneous detection of noise distributed around the reference slice level can be solved, and the code error rate can be suppressed to a minimum.

(2) When there is not much difference between the reproduced signal level and the reference slice level, the encoded data does not become unstable due to noise, and the margin in the amplitude level of the reproduced signal is improved.

(3) The slice level of the level comparator, the gain of the amplifier, etc. can be automatically set to optimal values for each recording medium and device, and compatibility between the device and the medium can be easily guaranteed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a data reproduction processing device of the present invention.

FIG. 2 is an explanatory diagram showing a relationship between a code error rate and a slice level of a level coparator.

FIG. 3 is a flowchart showing the slice level optimum adjustment operation of the level comparator in the embodiment of FIG. 1;

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram showing a conventional data reproduction processing device.

FIG. 6 is a time chart showing the data reproduction operation of the conventional device.

[Explanation of symbols]

1 Photoelectric converter 4 Equalizer circuit 5 LPF 6 Differential circuit 7 Zero cross comparator 8 Level comparator 9 D/A converter 10 AND circuit 14 Demodulation processing circuit 15 Control circuit 16 Amplifier 17 D/A converter 18 Variable gain amplifier

Claims (5)

[Claims] 1. A data reproducing processing device comprising means for binarizing a reproduced signal read from an information recording medium and reproducing it into digital data, and means for demodulating the digital data, wherein the data is detected by the demodulating processing means. A data reproduction processing device, characterized in that a predetermined constant of the digital data reproduction means is varied based on the determined bit error rate, and adjustment is made so that the bit error rate is minimized. 2. The predetermined constant is a slice level of a level comparator for generating a window pulse by binarizing the reproduced signal at a predetermined level to AND with a signal indicating a zero-crossing position of a signal obtained by differentiating the reproduced signal. 2. A data reproducing processing device according to claim 1, characterized in that: 3. The data reproduction processing device according to claim 1, wherein the predetermined constant is an amplification degree of an amplifier provided for amplifying a reproduction signal read from a recording medium. 4. The data reproduction processing device according to claim 1, wherein the predetermined constant is an equalizer constant of an equalizer circuit that corrects frequency characteristics of a reproduction signal read from a recording medium. 5. The data reproduction processing device according to claim 1, wherein the predetermined constant is a filter constant of a low-pass filter that removes high frequency noise from a reproduction signal read from a recording medium.