JP4576008B2 - Signal processing apparatus and data recording / reproducing apparatus equipped with the signal processing apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal processing method for a magnetic disk or an optical disk device, and more particularly to a signal processing method for improving data reliability during data recovery.
[0002]
[Prior art]
In recent years, a partial response maximum likelihood decoding method (Partial Response Maximum Likelihood, hereinafter abbreviated as PRML) capable of realizing a desired data error rate with a low S / N is generally used in signal processing devices such as magnetic disk devices. A typical PRML signal processing method for magnetic disk drives is the `` Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel '' (IEEE Transactions on communications.VOL.COM-34, No.5, MAY) by ROGER W.WOOD et al. 1986 pp 454-461). Furthermore, the Extended PRML (EPRML) signal processing method that realizes lower S / N signal reproduction is also adopted as the signal processing method of the disk device, as disclosed in JP-A-7-201135, JP-A-8-116275, etc. Has been. On the other hand, sampling of a signal waveform in the PRML signal processing method is performed by a phase synchronization device, and is performed as shown in Japanese Patent Laid-Open Nos. 1-143447 and 2-2719. Recently, a complementary phase synchronization circuit (Interpolated Timing Recovery, hereinafter abbreviated as ITR) is also proposed, which generates desired sample data synchronized by interpolation from asynchronously sampled data as described in JP-A-9-231506. Has been.
[0003]
FIG. 38 shows a configuration example of a general magnetic disk device using the PRML signal processing method.
[0004]
The magnetic recording medium 54 is a circular rotating magnetic recording medium and stores data from an external processing device. Data recording / reproduction processing is performed in units of blocks called sectors on concentric tracks. The track on the magnetic recording medium 54 has servo information at regular intervals, and the servo control circuit 52 causes the recording / reproducing head 53 to follow the rotating track. Perform positioning. The other blocks record / reproduce data from the external processing device, and operate as follows.
[0005]
The data recording operation is started by a write command from the external processing device. The write command is sent to the microcomputer 55 via the controller 51, and the microcomputer 55 issues a recording control command to the controller 51 and the servo control circuit 52. The controller 51 temporarily stores recording data from the external processing device following the recording command in the RAM 56. The servo control circuit 52 moves the recording / reproducing head 53 to a predetermined track on the magnetic recording medium 54. After the movement of the recording / reproducing head 53 is completed, the data temporarily stored in the RAM 56 is sent to the recording circuit 58 together with a synchronization signal required at the time of reproduction and an error correction code generated by the ECC generation / correction circuit 57. The recording circuit 58 performs modulation necessary for the PRML signal processing system on this data, and the recording data is recorded in the sector of the designated track via the RW amplifier 59 and the recording / reproducing head 53.
[0006]
On the other hand, the data reproduction operation from the magnetic disk device is started by a read command from the external processing device. The microcomputer 55 that has received the read command issues a read control command to the servo control circuit 52 and the controller 51. The servo control circuit 52 moves the recording / reproducing head 53 to a track in which designated data is stored. After the movement of the recording / reproducing head 53 is completed, the controller 51 instructs the reproducing circuit 60 to start the reading process. The recording information on the magnetic recording medium 54 is transmitted as a reproduction signal to the reproduction circuit 60 via the recording / reproducing head 53 and the RW amplifier 59. The reproduction circuit 60 makes a sample data sequence synchronized with the reproduction signal based on the synchronization signal added at the time of recording, and demodulates the data by the PRML signal processing circuit based on this. The demodulated data is temporarily stored in the RAM 56, and if an error exists in the data, the ECC error correction circuit 57 corrects the data error. If there is no error in the demodulated data or the error can be corrected by the ECC generation / correction circuit 57, it is transferred as reproduction data to the external processing device via the controller 51. On the other hand, when the error cannot be corrected by the ECC generation / correction circuit 57, the microcomputer 55 executes the read process again until the data can be correctly reproduced while changing various control parameters. When the data is read correctly, the reproduction data in the RAM 56 is transferred to the external processing device via the controller 51. If it is not read correctly, it is reported to the external processing device as a reproduction error. In addition to the data recording / reproducing operation described above, defect registration processing for detecting the defect position and length of the magnetic recording medium 54 and circuit constant optimization processing for correcting characteristic fluctuations of the recording circuit 58 and the reproducing circuit 60 are also performed. .
[0007]
With the configuration described above, the conventional magnetic recording / reproducing apparatus performs data recording / reproducing operation.
[0008]
[Problems to be solved by the invention]
In the data recording / reproducing process as described above, if the code word is within the error correction range of the ECC generation / correction circuit 57, the corrected data is immediately transferred to the external processing device. However, when an error that cannot be corrected by the ECC generation / correction circuit 57 occurs, the read process is executed again. For this reason, a data waiting time until the sector can be read after the magnetic recording medium 54 rotates, that is, a so-called rotation waiting occurs, and a decrease in data access time becomes a problem.
[0009]
Furthermore, partial missing of recording information caused by a defect in the magnetic film of the magnetic recording medium 54 may cause a malfunction of the phase synchronization circuit. In such a case, even if the data reproduction operation is performed again, the possibility of success is low, and wasteful waiting for rotation occurs. As a result, the data access time is significantly reduced.
[0010]
In addition, tests such as circuit parameter optimization of the signal processing circuit and disk defect check are performed by repeatedly performing the test based on the playback signal from the disk while changing the circuit constants, thus increasing the test time. Is a problem.
[0011]
A first object of the present invention is to provide a signal processing device that reduces rotation waiting due to a data error.
[0012]
A second object of the present invention is to provide a signal processing apparatus that reduces data burst errors due to malfunction of a phase locked loop.
[0013]
Furthermore, a third object of the present invention is to provide a signal processing device capable of optimizing circuit constants or shortening the test time of a magnetic recording / reproducing apparatus.
[0014]
[Means for Solving the Problems]
The first object of the present invention is realized by providing storage means for storing a reproduction signal and performing data reproduction with different control parameters based on the stored reproduction signal.
[0015]
Reproducing operation can be performed repeatedly with different control parameters without waiting for rotation by the storage means.
[0016]
In addition to this, the first object of the present invention can also be achieved by providing storage means for storing a reproduction signal obtained by reproducing the same sector a plurality of times and averaging means for averaging the input reproduction signal. The By improving the signal S / N by the storage means and the averaging means, the reliability of the second and subsequent data reproduction operations can be increased.
[0017]
A second object of the present invention is to provide a storage means for storing a reproduction signal and a sampling data generation means for reproducing sampling data that is phase-synchronized from the stored reproduction signal, to prevent malfunction of the phase synchronization circuit after the data defect. This is achieved by suppressing by the sample data generating means.
[0018]
A third object of the present invention is to provide a storage means for storing a reproduction signal, to optimize circuit constants, or to repeatedly perform a test of the magnetic recording / reproducing apparatus using the reproduction signal stored in the storage means. Realized.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described in detail with reference to the drawings.
[0020]
FIG. 1 shows an embodiment of a signal processing circuit for achieving the first object of the present invention and a magnetic recording / reproducing apparatus using the signal processing circuit. The basic configuration is the same as that of the conventional example, but the blocks constituting the reproduction circuit 60 are different. The recording circuit 58 includes a write synthesizer 61 that determines a data recording frequency, a scrambler 62 that randomizes a recording data string, an encoder 63 that modulates data, a precoder 64, and a recording correction circuit 65 that corrects nonlinear distortion inherent in magnetic recording. It consists of. The reproduction circuit 60 is roughly divided into an analog block that processes an analog signal from the RW amplifier 59 and a digital block that processes a digital signal obtained by sampling the analog signal. The analog block consists of HPF1 that cuts off low-frequency signals, variable gain amplifier 2 (hereinafter abbreviated as VGA) to keep the input signal amplitude constant, LPF3 that removes high-frequency noise, and digital signals by sampling analog signals AD converter (hereinafter abbreviated as AD) 4 for converting to 4; a read synthesizer 5 for determining the sampling frequency; and a thermal for detecting baseline fluctuations in the signal waveform caused by contact between the recording / reproducing head 53 and the magnetic recording medium 54 And an asperity (TA) detection circuit 17. The digital block consists of a FIFO 6 that stores the digital signal sampled by AD4, a selection circuit 7 that selects the digital signal, an As correction circuit 8 that digitally corrects the vertical asymmetry of the analog signal, and digital baseline fluctuations caused by TA. DC correction circuit 9 that corrects the waveform, equalizer 10 that performs waveform equalization, coefficient learning circuit 18 that optimizes the characteristics of the equalizer 10, and digital signal that is synchronized with the recording timing from the asynchronously sampled digital signal Complementary phase synchronization circuit (hereinafter abbreviated as ITR) 11, gain control circuit 19 for adjusting the digital signal amplitude to a constant, amplitude correction circuit (hereinafter abbreviated as AGC circuit) 12, digital signal data decoding by maximum likelihood decoding method Maximum likelihood decoding circuit (hereinafter abbreviated as ML) 13, SYNC detector 14 for performing byte synchronization, decoder 15 for demodulating data, and scrambler 62 re-synthesize the randomized data. A descrambler 16 that converts the data into the original data string and a register 20 that controls the operation mode of the reproduction circuit 60 are included.
[0021]
The operation of the above magnetic recording / reproducing apparatus will be described. First, the recording operation will be described in detail. The recording operation is started by a write command from the external processing device. The write command is sent to the microcomputer 55 via the controller 51, and the microcomputer 55 issues a recording control command to the controller 51 and the servo control circuit 52. The controller 51 temporarily stores user data from the external processing device following the recording command in the RAM 56. The servo control circuit 52 receives the recording control command and moves the recording / reproducing head 53 to a predetermined track on the magnetic recording medium 54. After the movement of the recording / reproducing head 53 is completed, the controller 51 detects the recording position of the sector from the servo information, and asserts the write gate to the recording circuit 58. At the same time, the controller 51 outputs PLO data (PLO) for bit synchronization and SYNC data (SYNC) for byte synchronization to the recording circuit 58, and then the user data (DATA) stored in the RAM 56, and Then, an error correction code (ECC) generated by the ECC generation / correction circuit 57 is output. The recording circuit 58 processes a series of data strings based on the clock generated by the write synthesizer 61. DATA and ECC after SYNC are randomized by the scrambler 62 and modulated by the encoder 63 (for example, block modulation from 8 bits to 9 bits) in units of byte data. Further, the precoder 64 performs modulation such as 1 / (1 + D ^ 2) on the entire data string after the PLO. Here, the symbol D ^ 2 indicates a bit two clocks before the modulated recording data, and the operator + indicates an exclusive OR. The recording correction circuit 65 determines a data pattern of a plurality of bits in order to reduce the non-linear distortion inherent in magnetic recording, and moves the recording bit position around several tens of percent of the 1-bit interval. A series of data strings obtained as described above is recorded in the sector on the magnetic recording medium 54 via the RW amplifier 59 and the recording / reproducing head 53.
[0022]
Next, the reproduction operation will be described in detail. Data reproduction operation from the magnetic recording / reproducing apparatus is started by a read command from the external processing apparatus. The microcomputer 55 that has received the read command issues a read control command to the servo control circuit 52 and the controller 51.
[0023]
The servo control circuit 52 moves the recording / reproducing head 53 to the designated track. After the movement of the recording / reproducing head 53 is completed, the controller 51 detects the reproducing position of the sector from the servo information and asserts a read gate to the reproducing circuit 60. The recorded information on the magnetic recording medium 54 is transmitted as a reproduction signal to the reproduction circuit 60 via the recording / reproducing head 53 and the RW amplifier 59. The reproduced signal is controlled by the VGA 2, the gain control circuit 19, and the AGC circuit 12 so that noise outside the signal band is removed by the HPF 1 and LPF 3 and the input amplitude to the ML circuit 13 is constant. When the TA is detected by the TA detection circuit 17, the microcomputer 55 detects the occurrence of TA via the register 20, and raises the cutoff frequency of the HPF 1 to minimize the baseline fluctuation due to the TA. The reproduction signal subjected to waveform processing in this way is sampled as a digital signal by AD 4 in accordance with a sampling clock generated by the read synthesizer 5. The sampling clock frequency of the read synthesizer 5 is not necessarily synchronized with the frequency and phase of the reproduction signal, and the ITR circuit 11 synchronizes the frequency and phase. The digital signal sampled by the AD 4 is accumulated in the FIFO 6 and output to the As correction circuit 8 via the selection circuit 7. Normally, the selection circuit 7 selects the output of AD4 by the sel signal (= 0) of the register 20 set by the microcomputer 55. The output of the FIFO 6 is output to the As correction circuit 8 by setting the sel signal (= 1) of the register 20 when the microcomputer 55 determines that data reproduction is necessary again. The output signal of the selection circuit 7 is decoded into a bit string through the As correction circuit 8, the DC correction circuit 9, the equalizer 10, the ITR circuit 11, the AGC circuit 12, and the ML circuit 13 whose characteristics can be changed by the sel signal. (These configuration examples will be described later). Further, the SYNC detector 14 performs byte synchronization based on the obtained bit string, the decoder 15 performs inverse demodulation of the encoder 63 to demodulate data, and the descrambler 16 converts the original user data. The obtained user data is temporarily stored in the RAM 56, and error correction of data is performed by the ECC generation / correction circuit 57. If there is no error in the read data or the error can be corrected by the ECC generation / correction circuit 57, the converted data string is transferred as reproduction data to the external processing device via the controller 51. On the other hand, if the ECC generation / correction circuit 57 cannot correct the error, the microcomputer 55 sets the sel signal (= 1) and uses the output of the FIFO 6 to equalize the As correction circuit 8 and the DC correction circuit 9 with different characteristics. The data reproduction operation is repeatedly performed only within the reproduction circuit 60 until the data can be correctly reproduced by the device 10, the ITR circuit 11, the AGC circuit 12, the ML circuit 13, and the SYNC detector 14. If the data is correctly read, the reproduction data in the RAM 56 is transferred to the external recording device via the controller 51. If the data is not read correctly, the data reproduction operation of the magnetic recording / reproducing device is repeated again.
[0024]
If the data is still not reproduced correctly, it is reported to the external processing device as a reproduction error.
[0025]
The recording / reproducing operation of the magnetic recording / reproducing apparatus is realized by the processing as described above.
[0026]
Here, circuit configuration examples of the As correction circuit 8, the DC correction circuit 9, the equalizer 10, the ITR circuit 11, the AGC circuit 12, and the ML circuit 13 having different characteristics are shown. In addition, a method of generating sel signal generation conditions other than whether error correction is possible by the ECC generation and correction circuit 57 is also shown.
[0027]
First, an embodiment of the As correction circuit 8 is shown in FIG. FIG. 6 (a) shows the input / output characteristics of the output signal amplitude with respect to the input signal amplitude of the As correction circuit 8. The input / output characteristics are a straight line when the sel signal = 0 and a broken line when the sel signal = 1. Is shown. An embodiment of the As correction circuit 8 that realizes such input / output characteristics is shown in FIG. 6 (b). In the figure, 100 is a multiplier, 101 and 103 are selection circuits, and 102 is a sign determination circuit. The sign determination circuit 102 determines the sign of the input signal, and switches the input of the selection circuit 103 according to the determination result. Here, the selection circuit 103 outputs the output of the multiplier 100 when the input signal is positive, and outputs the input itself when the input signal is negative. The selection circuit 101 determines the positive gain of the input signal and determines the degree of the broken line. In the normal state, when the sel signal = 0, gain1 is selected, and as a result, the multiplier of the multiplier 100 is gain1 (= 1.0). On the other hand, when the sel signal = 1, gain2 is selected, and the multiplier of the multiplier 100 is gain2 (= 0.5). Therefore, the input / output characteristics of the As correction circuit 8 are a straight line when the sel signal = 0 and a broken line of 0.5 on the positive side when the sel signal = 1. With the configuration as described above, the As correction circuit 8 capable of changing the circuit constant is realized.
[0028]
Next, an embodiment of the DC correction circuit 9 is shown in FIG. In the figure, 110 is a delay circuit, 111 and 112 are averaging circuits, 113 and 114 are subtractors, and 115 is a selection circuit. The ITR circuit 110 is obtained by delaying the input data every sampling clock. If the input data at time n is x (n), the output of each ITR circuit 110 is x (n), x (n-1), .... x (n-8). The averaging circuits 111 and 112 calculate the average of input data, and the output y1 (n) of the averaging circuit 111 is given by the following equation.
[0029]
[Expression 1]
y1 (n) = Σ {x (k)} / 6 k = n to n-5 ...... Equation 1
The output y2 (n) of the averaging circuit 112 is given by the following equation.
[0030]
[Expression 2]
y2 (n) = Σ {x (k)} / 9 k = n to n-8 ...... Equation 2
The averaging circuits 111 and 112 having different average lengths are low-pass filters having different frequency characteristics, and have different extraction characteristics for low-frequency signals such as TA waveforms. The outputs of the subtractors 113 and 114 become DC correction circuits having different TA removal characteristics by subtracting the outputs of the averaging circuits 111 and 112 and the input signal of the DC correction circuit 9. The selection circuit 115 selects such a different DC correction circuit by the sel signal. As a result, the DC correction circuit 9 is a circuit whose DC correction characteristics can be changed.
[0031]
Next, an embodiment of the equalizer 10 having different equalization characteristics is shown in FIG. In the figure, 120 is a delay circuit, 121 is a multiplier, 122 is an adder, and 123 is a coefficient selection circuit. The delay circuit 120, the multiplier 121, and the adder 122 constitute an FIR filter, and the frequency characteristics thereof are changed by changing the coefficient of the multiplier 121. The coefficient selection circuit 123 selects the coefficient group 1 or the coefficient group 2 prepared in advance or obtained by the coefficient learning circuit 18 based on the sel signal. Thereby, the equalizer 10 can perform equalization processing with different frequency characteristics.
[0032]
Next, FIG. 9 shows an embodiment of the ITR circuit 11 having a different phase synchronization response. In the figure, 125 is a waveform interpolation filter, 126 is a phase error detector, 127 is a digital filter, and 128 is an integrator. The waveform interpolation filter 125 is a linear filter that complements the waveform of the sample phase indicated by the integrator 128 based on the asynchronously sampled digital signal. Specifically, the waveform interpolation filter 125 includes a delay circuit 130, a multiplier 131, and an addition. The FIR filter of the device 132 is configured. The complementary coefficient of the multiplier 131 is given by the complementary coefficient 1-133 and the complementary coefficient 2-134, and the complementary characteristic can be changed by switching in the selection circuit 135 by the sel signal. The phase error detector 126 is the same as the conventional one, and includes a data determination unit 136, a delay circuit 137, a multiplier 138, and a subtractor 139. The obtained phase error is smoothed by a digital filter 127 composed of multipliers 140a and 140b, an adder 141 and a delay circuit 142, and an integrator 128 composed of an adder 145 and a delay circuit 146. The 128 outputs determine the sample phase of the waveform interpolation filter 125.
[0033]
Here, the operation of the circuit block whose characteristics can be changed by the sel signal will be described.
[0034]
The frequency characteristic of the digital filter 127 is determined by the multipliers of the multipliers 140a and 140b, and can be varied by selecting the coefficient group 1 or the coefficient group 2 by the selection circuit 144. The transfer function Hf (z) of the digital filter 127 and the open loop transfer function Ho (z) of the ITR circuit 11 are expressed as follows: A1 is the coefficient of the multiplier 140a, A2 is the coefficient of the multiplier 140b, and K is the loop gain. It is represented by the following formula.
[0035]
[Equation 3]
Hf (z) = A1 * {(1 + A2 / A1) -z} / (1-z) ...... Number 3
Ho (z) = K * Hf (z) / (1-z)
These frequency characteristics can be obtained by substituting z = exp (−j2πf / fs) into the above function. Here, f is a frequency, fs is a sampling frequency, j is an imaginary unit, and exp () is an exponential function. The digital filter 127 configured as described above is known as a digital filter having lag lead characteristics, and the corner frequency thereof is determined by the ratio of the coefficient A2 / A1. When the ratio A2 / A1 is high, the corner frequency of the digital filter 127 is high, and as a result, the zero-cross frequency of the open loop frequency characteristic Ho (z) of the ITR circuit 11 is also high. When the open loop frequency characteristic Ho (z) increases, the phase-locked response followability of the ITR circuit 11 improves, but the sampling error for noise increases. Therefore, in the re-read operation due to the reduction in the S / N of the reproduction signal, the coefficient ratio A2 / A1 is set to be small in order to stably follow the phase synchronization.
[0036]
The delay circuit 142 stores data relating to the difference between the sampling frequency and the reproduction signal frequency. The normal ITR circuit 11 completes the frequency / phase synchronization within the PLO region. However, if the rotational speed of the recording / reproducing head 53 fluctuates and the error between the sampling frequency and the reproduction signal frequency increases, the frequency synchronization time cannot be secured in the PLO region, and subsequent data reproduction becomes impossible. Therefore, by selecting the initial values F0 and F1 by the selection circuit 143, the difference between the sampling frequency and the reproduction signal frequency is reduced to a synchronizable range, and the frequency / phase synchronization is completed in the PLO region.
[0037]
The delay circuit 146 determines the sample phase whose waveform is complemented by the waveform complement filter 125. Normally, the frequency / phase synchronization is completed within the PLO region as described above. However, if a sufficiently long PLO data is not input to the ITR circuit 11 due to a defect in the playback waveform, the phase synchronization time in the PLO area cannot be secured, and similarly, subsequent data playback becomes impossible. . Therefore, the initial phase can be changed by selecting the initial values P0 and P1 by the selection circuit 147. When an appropriate initial phase is given, the ITR circuit 11 starts zero phase, and the PLO region can be shortened. By phase-synchronizing the playback data of FIFO 6 while changing the initial value of the sample phase, reliable phase synchronization is possible even if the PLO region is short. Furthermore, even if there is no PLO area, it is possible to change the initial values of P0 and P1 until the Sync byte is detected in the SYNC area, and to perform phase synchronization. This can be realized because the sampling data is stored in the FIFO 6, and cannot be realized by the conventional method. According to this method, the PLO area can be reduced and the area for recording data can be expanded.
[0038]
The selection circuit 135 changes the interpolation coefficient of the waveform interpolation filter 125.If the error between the sampling frequency and the reproduction signal frequency increases, the estimation error due to data interpolation increases, resulting in a decrease in data demodulation performance. Connected. Therefore, it is also possible to improve the data complementing accuracy by changing the complementing coefficient by the sel signal.
[0039]
In the present embodiment described above, clock control by sampling overtaking / overtaking is not considered, but since it is a processing method similar to the conventional method, description thereof is omitted.
[0040]
Next, FIG. 10 shows an embodiment of the AGC circuit 12 having different amplitude synchronization responses. In the figure, 150 is a multiplier, 151 is an amplitude error detector, 152 is a multiplier, and 153 is an integrator. The amplitude error detector 151 is composed of the same data determiner 155, subtractor 156, multiplier 157, delay circuit 158, and adder 159 as the conventional one, and the output signal and the target amplitude determined by the selection circuit 164 Generate an amplitude error. Multiplier 152 multiplies the amplitude error by a multiplier determined by selection circuit 163 and outputs the result to integrator 153 including adder 160 and delay circuit 161. The integrator 153 integrates the amplitude error to calculate the error gain, and the multiplier 150 multiplies the input signal by the error gain to obtain the output of the AGC circuit 12.
[0041]
These one-round operations are normally completed within the PLO region, and the error gain between the input waveform and the target amplitude is given to the delay circuit 161. However, if the amplitude synchronization is not completed due to a defect in the PLO area or the like, subsequent user data reproduction becomes impossible. Therefore, the initial error gain can be changed by selecting the initial values G00 and G01 at the time of reproduction data from the FIFO 6 by the selection circuit 162. When an appropriate initial error gain is given, the AGC circuit 12 starts zero gain, and the PLO region can be shortened.
[0042]
For the multipliers G0 and G1 selected by the selection circuit 163, for example, when the amplitude drop due to the defect in the reproduction waveform becomes large, there is a high possibility that the reproduction data after the defect also causes a data error due to the amplitude reduction. Therefore, by reducing the multiplier given to the multiplier 152 when reproducing data from the FIFO 6, it becomes possible to reliably reproduce data after the defect.
[0043]
The selection circuit 164 changes the target amplitude, and when an amplitude drop occurs due to a defect in the playback waveform, the data playback performance other than the defect is reduced by reproducing the data by lowering the target amplitude from the normal setting. However, it is possible to increase the data reproduction capability against the decrease in the amplitude of the defective portion. Therefore, when reproducing data from the FIFO 6, by selecting and reproducing the target amplitude with the selection circuit 164, it is possible to improve the entire data reproducing capability.
[0044]
Next, FIG. 11 shows an embodiment of switching detection condition generation using the ITR circuit 11 and the AGC circuit 12 described above. In the figure, 165 indicates a selection circuit, 166 indicates a comparator, 167 indicates a delay circuit, and 168 indicates a determination circuit. The selection circuit 165 selects one of the phase error signal and complementary frequency error that are internal signals of the ITR circuit 11 and the amplitude error that is an internal signal of the AGC circuit 12 by the condition selection signal, and the comparator 166 Output to. The comparator 166 compares the selected error signal with a predetermined threshold value, and outputs “1” when the error signal is equal to or greater than the threshold value, and outputs “0” otherwise. The delay circuit 167 stores the output of the comparator 166 for each sample. The determination circuit 168 determines the lapse of time of the error signal from the output of the delay circuit 167 and asserts the switching condition. For example, if the phase error or amplitude error that is equal to or greater than the threshold value continues, it is considered that phase synchronization loss or amplitude synchronization loss has occurred. Detect and make the switching condition active. When the complementary frequency error is different from the threshold value or more, the determination circuit 168 determines that the frequency synchronization has been lost, and similarly activates the switching condition. The switching conditions described above are notified to the microcomputer 55 via the register 20, for example.
[0045]
Next, an embodiment of the ML circuit 13 capable of changing the data decoding performance will be described with reference to FIG. In the figure, 170 is a PRML decoding circuit, 171 is an EPRML decoding circuit, 172 is a comparator, and 173 is a selection circuit. In the normal state, the sel signal is “0”, and the selection circuit 173 outputs the decoding result of the PRML decoding circuit 170. At this time, the comparator 172 compares the metric value indicating the determination margin of the PRML decoding circuit 170 with a known threshold value, and when the metric value is equal to or lower than the threshold value, asserts the switching condition and decreases the data determination margin. For example, the microcomputer 55 is notified of this. As a result, the microcomputer 55 sets the sel signal to “1” and uses the reproduction data from the FIFO 6 to decode it by the EPRML decoding circuit 171, and the result is output via the selection circuit 173. With this configuration, when it is determined that data reproduction by the PRML decoding circuit 170 is difficult, an EPRML decoding circuit that can decode a lower S / N signal at a desired error rate By using 171, the data decoding performance can be improved.
[0046]
Another embodiment shown in FIG. 13 in which more complicated data decoding performance can be changed will be shown and described in the ML circuit 13. In the figure, 175 and 176 are branch metric generation circuits, 181 is a selection circuit, 182 is an ACS circuit, 183 is a path memory, and 184 is a comparator. The branch metric generation circuit 175 and the branch metric generation circuit 176 are composed of a delay circuit 177, a multiplier 178, an adder 179, and a branch metric generation circuit 180. The branch metric generation circuit 175 has a response 1 characteristic, for example, EEPRML ( 1, 2, 1), and the branch metric generation circuit 176 has a response 2 characteristic, for example, MEEPRML (2, 2, 1). The selection circuit 181 selects the output of the branch metric generation circuit having a different response, and outputs it to the ACS circuit 182. The ACS circuit 182 performs path addition / comparison / selection based on the branch metric, and outputs probable path selection information to the path memory 183. The path memory 183 determines the probability of the path in time series, and outputs the most likely decoding result. On the other hand, the comparator 184 compares the metric value, which is the margin at the time of addition / comparison of the path of the ACS circuit 182, with a known threshold value, and when the metric value falls below the threshold value, asserts the switching condition, For example, the microcomputer 55 is notified that the determination margin has decreased. Similar to the ML circuit described above, the microcomputer 55 sets the sel signal to “1” and sets the data decoding using the reproduction data from the FIFO 6, and the selection circuit 181 selects the branch metric of the branch metric generation circuit 176. Is output to the ACS circuit 182. Even with the above-described configuration, a maximum likelihood decoding circuit having different data decoding performance can be realized.
[0047]
In this embodiment, different responses are selected, but the maximum likelihood decoding is performed by the same process even when the response of the branch metric generation circuit 176 is k times (k: rational number) the response of the branch metric generation circuit 175. A circuit can be constructed.
[0048]
Next, another embodiment of the switching condition generation circuit in the maximum likelihood decoding circuit will be described with reference to FIG. In the figure, 185 is a delay circuit, 186 is an autocorrelation operation circuit, and 187 is a comparison circuit. The delay circuit 185 stores a signal obtained by delaying the input signal of the ML circuit 13, and when the input signal at time n is x (n), the input signal to the autocorrelation operation circuit 186 is the input x ( n) and outputs x (n-1),..., x (n-4) of the delay circuit 185. The autocorrelation calculation circuit 186 calculates the following autocorrelation function and determines the characteristics of the reproduction signal. However, it is assumed that the DC component of the input signal has been removed.
[0049]
[Expression 4]
a (-j) = {Σ (x (n) * x (nj)) / x (n) * x (n)} / N n = 0 ~ N-1, j = 0 ~ 4 ...... Equation 4
The autocorrelation function indicates the correlation between the output reproduction waveform of the equalizer 10 and noise, and the reproduction performance of the ML circuit 13 is greatly deteriorated when this characteristic is significantly different from that of the known one. Therefore, the comparison circuit 187 compares a (−j) obtained from the above autocorrelation function with a known autocorrelation function, determines whether the error is equal to or greater than a threshold, and The result is output to the microcomputer 55 as a switching condition. A switching condition generation circuit can also be configured with such a configuration.
[0050]
Next, an embodiment of the SYNC detector 14 whose detection conditions can be switched will be described with reference to FIG. Here, it is assumed that the Sync code is composed of two SyncA and SyncB. Reference numeral 190 denotes a SyncA detector, 191 denotes a SyncB detector, 192 denotes a sync detector, 193 denotes a selection circuit, and 194 denotes a logical sum. Detection condition 1 is a sync detection condition when both SyncA and SyncB are detected. Detection condition 2 is a sync detection condition when either SyncA or SyncB is detected. Normally, the selection circuit 193 gives the detection condition 1 to the sync detector 192, and the sync detector 192 asserts the Sync detection output only when the SyncA detection circuit 190 and the SyncB detection circuit 191 detect both Sync codes. . At this time, if neither of the sync codes is detected, the OR circuit 194 asserts the switching condition as not detecting the sync and notifies the microcomputer 55 of it. As a result, the sel signal is set to select detection condition 2, and the sync detector 192 asserts the Sync detection output when either SyncA detection circuit 190 or SyncB detection circuit 191 is detected. To do. As described above, the SYNC detector 14 capable of switching the sync detection condition can be configured.
[0051]
Next, an embodiment of the decoder 15 for generating the switching condition is shown in FIG. 16 and will be described. In the figure, 195 is a decoder, 196 is an encoder, 197 is a comparator, 198 is an RLL detector, and 199 is a logical sum. The encoder 196 is the same as the encoder 63 described above, and the reference numerals are separated for convenience of explanation. As described above, in the data recording operation, for example, 8-bit byte data is converted into 9-bit recording data on a one-to-one basis by the encoder 63 and recorded on the disk 54. On the other hand, in the data reproduction operation, the data-decoded bit string is converted by the decoder 195 from, for example, a 9-bit bit string to 8-bit byte data. Here, the decoding process is configured by an inverse conversion process for forcibly converting an unassigned bit string into certain byte data, in addition to the conversion of the encoder 63 and the inverse conversion process from the bit string corresponding to one-to-one to byte data. If there is no error at the time of data demodulation, the decoder 195 correctly converts the input bit string (for example, a 9-bit bit string) into byte data given by the inverse conversion of the encoder 63. Accordingly, the bit string obtained by modulating the byte data demodulated by the decoder 195 again by the encoder 196 is the same as the input bit string. On the other hand, if there is an error during data demodulation, the decoder 195 inputs a bit string different from the bit string converted by the encoder 63, and forcibly converts the input bit string into appropriate byte data. Of course, the bit string obtained by modulating the converted byte data with the encoder 196 again does not match the input bit string. Therefore, an error during data decoding can be detected by comparing the above input bit string with the bit string output from the encoder 196. The comparator 197 compares these bit strings, and outputs that a data decoding error has occurred via the OR circuit 199 as a switching condition.
[0052]
On the other hand, the RLL detector 198 determines whether or not the continuous length (0 run length) of “0” in the input data string of the decoder 15 is equal to or greater than a predetermined value. The recording data that is the output of the subtracter 113 uses a code in which 0 run length is limited in advance, for example, a continuous “0” of 7 bits or more does not occur. Therefore, if there is no error at the time of reproduction, the input data string of the decoder 15 should be limited to 0 run length. The RLL detector 198 asserts the switching condition via the OR circuit 199 when the 0 run length is equal to or greater than the predetermined value. In this way, it is possible to configure the decoder 15 that generates the switching condition.
[0053]
Next, an embodiment of the ECC generation / correction circuit 57 capable of changing the error correction capability will be described with reference to FIG. In the figure, reference numerals 200 and 201 denote ECC correction circuits, 202 denotes a selection circuit, and 203 denotes an error detection circuit. The ECC correction circuit 200 and the ECC correction circuit 201 are ECC circuits in which the number of error-correctable bytes is different. For example, the ECC correction circuit 200 is an ECC correction circuit having a correction capacity of 12 bytes, and the ECC correction circuit 201 is 20 bytes. It is assumed that the ECC correction circuit has the correction capability of In a normal state, the sel signal is “0”, and the selection circuit 202 outputs the correction result of the ECC correction circuit 200 having a low ECC correction capability. The error detection circuit 203 is a circuit that detects the presence of an error that cannot be corrected by the ECC correction circuit 200. When such a condition occurs, the error detection circuit 203 notifies the microcomputer 55 as a switching condition. When the switching condition is asserted, the sel signal is set to “1”, and the correction result of the ECC correction circuit 201 having a high error correction capability is output. Thus, by providing ECC correction circuits having different error correction capabilities, and switching them, the error correction capability can be changed.
[0054]
Circuit configuration with different characteristics by As correction circuit 8, DC correction circuit 9, equalizer 10, ITR circuit 11, AGC circuit 12, ML circuit 13, SYNC detector 14, decoder 15, and ECC generation correction circuit 57 described above Is realized. As a result, the first object of the present invention can be achieved by applying these circuit blocks to FIG. Specifically, data reproduction is performed based on a reproduction signal stored in the FIFO due to a data error. At this time, the magnetic recording / reproducing apparatus does not need to reproduce the reproduction signal on the magnetic recording medium 54 immediately. Therefore, in the case of a reproduction signal that can be read by changing the circuit constant, data is reproduced without causing rotation waiting, and high speed data access is achieved.
[0055]
Further, in FIG. 1, the start of the data reproduction operation based on the reproduction signal stored in the FIFO 6 is performed based on whether or not the ECC generation correction circuit 57 can correct the error. However, when the TA is detected by the TA detection circuit 17, each of the above-described configurations The same control method can be used depending on the switching condition in the block. Further, by analyzing the occurrence of these switching conditions, it is possible to determine the optimum circuit characteristic change site. For example, when TA is detected by the TA detection circuit 17, it goes without saying that changing the characteristic of the DC correction circuit 9 can appropriately cope with the change rather than changing the frequency characteristic of the equalizer 10.
[0056]
In performing the data reproduction operation using the FIFO 6 described above, a processing method as shown in FIG. 18 can be considered. In the figure, (a) indicates that when a data error is detected, the playback process for the entire sector, which is a data processing unit, is started from the start position of the sector, and (b) is the playback process for the area where the data error occurs Are processed from the reproduced data. Further, (c) stores the reproduction data only in the area where the data error has occurred in the FIFO 6, and subsequently reproduces the data only in that area. The operation will be described with reference to the configuration of FIG. Here, the case where the TA detection circuit 17 detects TA in a sector will be described as a condition for detecting the occurrence of a data error, that is, as a switching condition.
[0057]
First, FIG. 18 (a) will be described. The time of operation 1 is a normal read operation and indicates a data string input to the FIFO 6. After the reproduction signal of the recording / reproducing head 53 is sampled by AD4, the sampling data is sent to the FIFO 6 simultaneously with the data decoding circuit after the As correction circuit 8, and the sampling data is stored in the FIFO 6 from the head of the sector. When the TA detection signal is generated at the timing shown in the figure during data reproduction, the content of the register 20 is set at the rising edge of the TA detection signal, and the TA generation is stored. The microcomputer 55 reads the contents of the register 20 after the completion of one sector reproduction operation in response to the notification from the controller 51, and detects that TA has occurred in the currently processed sector. When TA occurs, the data playback operation is performed using the FIFO6 data at the time of operation 2. The microcomputer 55 sets the sel signal to “1” via the register 20 in order to perform the data reproduction operation using the reproduction signal stored in the FIFO 6. As a result, for example, the coefficient of the equalizer 10 described above is switched from the coefficient group 1 to the coefficient group 2, and the frequency characteristics thereof are changed. The controller 51 asserts the read gate in order to process data using the reproduction data of the FIFO 6.
[0058]
The FIFO 6 outputs the stored reproduction signal from the beginning, that is, from the beginning of the sector at the time of the operation 2, and the data is decoded by the circuits after the As correction circuit 8. For the decoded data, the ECC generation / correction circuit 57 performs error detection / correction of the data while discarding the previously decoded data and storing it in the RAM 56 again. The subsequent processing is as described above. Such a processing method has a feature that the processing method of the controller 51 is simplified, although it is necessary to process the data of one sector again after the error occurs at the time of the operation 2 and the processing time is increased.
[0059]
Next, the processing method (b) will be described. As shown at the time of operation 1, the FIFO 6 stores sampling data after the head of the sector as in (a). The register 20 records the generation position and pulse width of the TA detection signal after the read gate is asserted. Such a circuit is realized by a combination of general counters, not shown in the figure, and after the read gate is asserted, it counts the bit clock or byte clock used as a reference for data transfer, and counts when the TA detection signal is generated. The error data range can be easily obtained from the value. When the read operation is completed at the time of operation 1, the microcomputer 55 confirms the contents of the register 20 and detects that TA has occurred.
[0060]
Thereafter, the microcomputer 55 sets the sel signal to “1”. Further, the microcomputer 55 sets the reproduction data output start position of the FIFO 6 in the FIFO 6 via the register 20 based on the TA detection signal generation position recorded in the register 20. In this case, the start position set in the FIFO 6 is set slightly before the TA detection signal generation position in consideration of the synchronization time of the ITR circuit 11 and the AGC circuit 12 or the decoding processing delay time of the ML circuit 13. Further, the output position of the FIFO 6 is determined from the storage position of the sampling data corresponding to the byte delimiter position with reference to the byte synchronization position of the SYNC detector 14. After the above FIFO 6 output start position is set, the controller 51 executes the read operation again at the time of operation 2, and only the sampling data in the area where TA occurs is subjected to data decoding by the circuits after the As correction circuit 8 . The controller 51 replaces only the previous byte data corresponding to the TA signal generation position and length with the reproduced data and stores it in the RAM 56. The playback data of operation 1 in which a part of the byte data is replaced with the playback data of operation 2 constitutes data of one sector. Again, the data of one sector is detected / corrected by the ECC generation and correction circuit 57. Done. The subsequent operation is as described above. According to this processing method, the data processing method of FIFO 6, controller 51, etc. is complicated, but at the time of operation 2, only the TA occurrence position data is decoded, so the processing time is compared to method (A). Can be shortened.
[0061]
Next, the processing method (c) will be described. The reproduction signal of the recording / reproducing head 53 is decoded by the reproducing circuit 60 and then stored in the RAM 56 via the controller 51. At this time, the FIFO 6 stores sampling data from the time just before the TA detection signal is asserted until the TA detection signal is negated. The register 20 stores the start position and length of the TA detection signal as in the method (b). Here, the data recording length before the TA detection signal is asserted is determined from the synchronization time of the ITR circuit 11 and the AGC circuit 12 and the byte delimiter position of the SYNC detector 14 as in the method (b). The microcomputer 55 detects the presence / absence of TA from the result of the register 20, and requests the controller 51 to execute the read operation again. The controller 51 asserts the read gate, and the data decoding circuit after the As correction circuit 8 processes only the data stored in the FIFO 6 at the time of the operation 2, that is, the sampling data at the time when the TA detection signal is active. Similarly to the method (b), the controller 51 replaces only the processed data with a part of the data reproduced at the time of the operation 1, and stores it in the RAM 56. The ECC generation / correction circuit 57 detects / corrects a data error based on the data of one sector stored in the RAM 56. Subsequent operations are the same as those described above. This processing method can decode data only at the TA occurrence position in the same processing time as the method (b). Furthermore, the amount of data stored in the FIFO 6 can be reduced compared to the methods (a) and (b), which is about the TA generation length, and the circuit scale can be reduced.
[0062]
The first object of the present invention can be achieved by the signal processing circuit and processing procedure of FIG. 1 as described above.
[0063]
Next, one procedure of the coefficient learning method of the equalizer 10 using FIG. 1 is shown below. The coefficient learning method of the equalizer 10 in the present embodiment is that the coefficient learning is conventionally performed while reproducing a plurality of sectors many times, but the coefficient learning is performed using the sampling data stored in the FIFO 6. Features. Specifically, in order to reproduce one sector on the track, the controller 51 asserts a read gate. When the read gate is asserted, the reproduction signal of the recording / reproducing head 53 is subjected to signal processing by the analog circuit described above, and then converted to sampling data by AD4. While the sampling data is stored in the FIFO 6, data decoding processing is performed by the circuits after the As correction circuit 8. At this time, the coefficient learning circuit 18 updates the coefficient by obtaining the coefficient update amount of the coefficient learning circuit 18 based on the error between the digital data that is the output of the ITR circuit 11 and the internal equalization target. . When the reproduction operation for one sector is completed, the FIFO 6 stops storing the sampling data, and the coefficient learning circuit 18 once ends the coefficient update. Next, the microcomputer 55 changes the sel signal via the register 20 and connects the output of the FIFO 6 to the input of the As correction circuit 8. Thereafter, the controller 51 asserts the read gate. The FIFO 6 outputs data after the sampling data stored at the specific position to the As correction circuit 8. The coefficient learning circuit 18 restarts the coefficient update operation using the previous coefficient as an initial value. Further, when the sampling data at a specific position stored in the FIFO 6 is processed, the controller 51 negates the read gate, and the coefficient learning circuit 18 once ends the coefficient update operation. Following this, the controller 51 asserts the read gate again, and thereafter performs the coefficient learning operation described above. After the coefficient learning operation using the FIFO 6 sampling data is performed a specified number of times, the reproduction operation from the recording / reproducing head 53 is performed again, and then the coefficient learning operation using the FIFO 6 sampling data is performed. By repeatedly performing such an operation, the coefficient of the equalizer 10 is determined by the coefficient learning circuit 18. According to this embodiment, the coefficient learning time can be increased by performing the coefficient learning operation using the sampling data stored in the FIFO 6 instead of performing the coefficient learning by reading the reproduction signal of the conventional sector a plurality of times. It becomes possible.
[0064]
Next, a procedure for searching for a defective area of the magnetic recording medium 54 in the magnetic recording / reproducing apparatus of FIG. 1 and a registration method thereof will be described. In a general magnetic recording / reproducing apparatus, a defective area on the magnetic recording medium 54 has a method in which a sector having a low read margin is determined as a defective area by reproducing a plurality of sectors while changing a circuit constant of a signal processing circuit. It is taken. For this reason, it is necessary to continue reading the same sector as many times as the number of circuit constant changes. In this embodiment, for example, as in the coefficient learning method described above, the reproduction signal of a specific sector is stored as sampling data in the FIFO 6, and the sampling data of the FIFO 6 is changed while changing the circuit constants after the As correction circuit 8. Reproduce. Specifically, in order to reproduce one sector on the track, the controller 51 asserts a read gate. When the read gate is asserted, the reproduction signal of the recording / reproducing head 53 is subjected to signal processing by the analog circuit described above, and then converted to sampling data by AD4. While the sampling data is stored in the FIFO 6, data decoding processing is performed by the circuits after the As correction circuit 8. When the reproduction operation for one sector is completed, for example, the presence or absence of a data error is detected by the ECC generation and correction circuit 57. Next, the RAM 56 changes the sel signal via the register 20, and as a result, the output of the FIFO 6 is input to the As correction circuit 8. The microcomputer 55 changes the characteristics of the signal processing circuit after the As correction circuit 8, changes the target amplitude of the AGC circuit 12, for example, and requests the controller 51 to start the data reproduction operation. When the controller 51 asserts the read gate again, the data is decoded by different characteristics after the As correction circuit 8 using the sampling data of the FIFO 6. The above procedure is repeated, and from the obtained data decoding result, the microcomputer 55 analyzes the data error distribution in the sector and obtains information on the position and length of the defective area of the magnetic recording medium 54. Based on this, the defect area can be registered. By such a processing procedure, it is not necessary to reproduce the sector every time the circuit constant is changed, and the defect area can be searched with at least one reproduction operation, and the search time for the defect area can be shortened. it can.
[0065]
Next, a configuration example of another signal processing circuit in which the position of the FIFO 6 is changed will be described with reference to FIG. In FIG. 2, the position of the FIFO 6 is changed to the output of the equalizer 10. In FIG. 2, the same components as those in FIG. The adin input signal is an analog signal obtained by processing the reproduction signal from the recording / reproducing head 53 by the circuit described above. The AD 4 samples the adin input signal with a sampling clock asynchronous with the input signal generated by the read synthesizer 5, and outputs it to the As correction circuit 8 as sampling data. The As correction circuit 8, the DC correction circuit 9, and the equalizer 10 realize the above-described functions, and a signal from which the intersymbol interference of the input signal is removed is obtained at the output of the equalizer 10. The obtained digital signal is simultaneously input to the selection circuit 7 and the FIFO 6. In the FIFO 6, sampling data of the sector to be processed is stored from the top. During normal data reproduction, the sel signal of the register 20 is set to “0”, for example, and the selection circuit 7 is controlled to input the output of the equalizer 10 to the ITR circuit 11. The ITR circuit 11 processes complementary data whose frequency and phase are synchronized based on the digital signal of the equalizer 10 by digital calculation, and the AGC circuit 12 controls the signal amplitude to be constant. The obtained signal is maximum likelihood decoded by the ML circuit 13 and output to the SYNC detector 14 as an mlout signal.
[0066]
On the other hand, when an error is detected by the ECC generation / correction circuit 57 and the like and the read operation is started again, the sel signal is set to, for example, “1” by the microcomputer 55 via the register 20. As a result, the sampling data stored in the FIFO 6 is input to the ITR circuit 11, and at least one of the characteristics of the ITR circuit 11, the AGC circuit 12, and the ML circuit 13 is changed by the configuration as described above. . The sampling data stored in the FIFO 6 is processed by the ITR circuit 11, the AGC circuit 12, and the ML circuit 13 having different characteristics, and then output to the SYNC detector 14 as an mlout signal. Also in this embodiment, the same processing as that in FIG. 1 is realized, and the first object of the present invention can be achieved.
[0067]
Furthermore, it can be understood from FIG. 3 that the same processing as in FIG. 1 can be performed even if the FIFO 6 is arranged at any position. FIG. 3 shows an embodiment of the present invention, in which 21, 22, 23, 24, and 25 are 2to1 selection circuits, and 26 is a 6to1 selection circuit. The same functions as those in FIG. 1 are denoted by the same reference numerals. Each signal processing circuit, As correction circuit 8, DC correction circuit 9, equalizer 10, ITR circuit 11, AGC circuit 12, and ML circuit 13 have selection circuits 7, 21, 22, 23, 24, and 25 at the input. Further, a selection circuit 26 is provided at the input of the FIFO 6. Each selection circuit is controlled by an independent selection signal, and in normal read operation, the output of AD4 is as correction circuit 8, DC correction circuit 9, equalizer 10, ITR circuit 11, AGC circuit 12, It is processed in series by the ML circuit 13. The selection circuit 26 selects any one of these signal processing circuits, and the FIFO 6 stores the selected digital signal. On the other hand, at the time of retry, only one of the selection circuits 7, 21, 22, 23, 24, 25 connected to the output of the signal processing circuit selected by the selection circuit 26 selects the output of the FIFO 6. Be controlled. For example, in the normal read operation, the output of the equalizer 10 selected by the selection circuit 26 is controlled, and at the time of retry, only the selection circuit 23 is controlled to input the output of the FIFO 6 to the ITR circuit 11. In this example, it is needless to say that the same data reproduction operation as in FIG. 2 is realized. Similarly, when the characteristics of only the ML circuit 13 are changed at the time of retry, in the normal read operation, the selection circuit 26 stores the output of the AGC circuit 12 in the FIFO 6, and at the time of retry, only the selection circuit 25 is in the FIFO 6 state. Select an output.
[0068]
According to the embodiment as shown in FIGS. 2 and 3 described above, it is possible to switch the processing operation range of the circuit for each factor causing the data error. For example, if it is empirically known that phase synchronization becomes malfunctioning due to distortion of the reproduction signal of the recording / reproducing head 53, and as a result, data errors frequently occur, the sampling data of FIFO 6 is the ITR circuit 11 or later at the time of retry It is sufficient to operate only the data decoding circuit, and it is not necessary to operate the irrelevant equalizer 10 or the like. Therefore, unnecessary power consumption can be suppressed by narrowing down the parts to be operated at the time of retry.
[0069]
Here, an embodiment of a circuit configuration for reducing the circuit scale of the FIFO 6 will be described with reference to FIG. In this embodiment, arithmetic circuits are provided before and after the FIFO 6 to reduce the number of bits stored in the FIFO 6. In the figure, 210 is a data determination circuit, 211 is an adder, 212 and 214 are delay circuits, and 213 is A sequencer 215 indicates a subtracter. The input x (n) of the FIFO circuit is signed two's complement digital data, which is, for example, (1,0) in the Partial Response Class-4 because of the channel characteristics used in the magnetic recording / reproducing apparatus. ,-1). This is because, when '1' occurs at time n in the input signal, there is no correlation at time (n + 1), and at time (n + 2), '0' or '- 1 'indicates that it occurs. This data correlation is used to reduce the number of bits stored in FIFO6. The data judgment circuit 210 judges the data of x (n), and when x (n)> 0.5, '1', x (n) <-0.5 is output to the sequencer 213 as “-1” and other values as “0”. The sequencer 213 detects the data string by detecting the data string because the signal in the PLO area at the start of the sector is a continuous pattern of (1,1, -1,1) based on the determination result of the data determination circuit 210. Output a signal. As shown in FIG. 20 (a), after the read gate is asserted, (1,1, -1, -1) is detected and the wcmd signal is output at the next time. After being cleared by asserting the wcmd signal, the delay circuit 212 delays the output y (n) of the adder 211 by two clocks and outputs it to the adder 211. After wcmd signal is asserted, y (n-2) becomes '0' for 2 clocks. The adder 211 adds the inputs x (n) and y (n−2) and outputs the output yn to the FIFO 6. Thereafter, when such an operation is repeated, the output y (n) of the adder 211 becomes as shown in FIG. The data write operation to the FIFO 6 is performed after the wcmd signal is asserted. Therefore, for example, if the number of bits of the input x (n) is 6 bits, y (n) is 5 bits, and 1 bit can be reduced.
[0070]
On the other hand, when reading data from FIFO 6, it must be the same data b (n) as the original x (n). Data b (n) is delayed from the sequencer 213 and the digital data a (n) of FIFO 6. Restored from the output a (n-2) of the circuit 214. When the sequencer 213 receives the read gate signal, it generates an rcmd signal and clears the delay circuit 214. The subtracter 215 subtracts the read data a (n) from the FIFO 6 and the output a (n-2) from the delay circuit 214 and outputs the result as data b (n). An example of this calculation is shown in FIG. After asserting the rcmd signal, a (n-2) becomes '0' for 2 clock periods. The output a (n) of the FIFO 6 is the same as y (n) in FIG. 20 (a), and b (n) is obtained by subtracting a (n-2) from this signal. When b (n) thus obtained is compared with FIG. 20 (a), it can be seen that the same numerical value is obtained.
[0071]
The above operation can be expressed as an arithmetic expression as follows.
[0072]
[Equation 5]
y (n) = x (n) + y (n-2) ... number 5
b (n) = a (n) -a (n-2)
Since y (n) = a (n), y (n) -y (n-2) = x (n)
b (n) = x (n) + y (n-2) -x (n-2) -y (n-4) = x (n) -x (n-2) + x (n-2) = x (n)
As can be understood from the above arithmetic expression, even when the above circuit is added, both b (n) and x (n) are equal and delayed while reducing the circuit scale by reducing the number of bits of FIFO6. Sampling data can be output.
[0073]
In the signal processing circuit in the embodiment described above, the conventional circuit is switched by the circuit such as the selection circuit 7 at the time of retry. However, in such a configuration, when a continuous sector is continuously processed as in a magnetic disk device, the processing is interrupted by a retry operation. For example, when data is decoded for 1 sector and 2 sectors in succession, if an error occurs in 1 sector, instead of data decoding for the 2nd sector, 1 sector is output using the same signal processing circuit using the output of FIFO 6. In order to perform the second data decoding, it is necessary to interrupt the second sector data decoding. Accordingly, since the data decoding of the second sector is executed after waiting for rotation, the access time is reduced. FIG. 4 shows an embodiment of a signal processing circuit for avoiding this, in which 30 is an As correction circuit, 31 is a DC correction circuit, 32 is an equalizer, 33 is an ITR, 34 is an AGC, 35 Indicates ML, and the basic configuration is the same although the characteristics are different from the corresponding As correction circuit 8, DC correction circuit 9, equalizer 10, ITR circuit 11, AGC circuit 12, and ML circuit 13, respectively. . 36, 37, and 38 have the same functions as the SYNC detector 14, the decoder 15, and the descrambler 16, respectively, but are given different reference numerals for explanation. These operations will be described by taking as an example a case where data of 1 sector and 2 sectors are processed successively. Here, it is assumed that the data storage capacity of the FIFO 6 is large enough to store sampling data of two sectors. In normal operation, first sector data is first input to AD4, and digital data of AD4 is output to descrambler 16 via As correction circuit 8 and simultaneously stored in FIFO6. The controller 51 performs error detection by the ECC generation / correction circuit 57 while storing the reproduction data of the first sector output from the descrambler 16 in the RAM 56. Here, when a data error is detected by the ECC generation correction circuit 57, the sampling data of the subsequent second sector is processed by a signal processing circuit after the As correction circuit 8 and output to the descrambler 16 as reproduction data, Following the data in the first sector, it is stored in FIFO6. On the other hand, the previously stored sampling data of the first sector of the FIFO 6 is decoded by the signal processing circuit after the As correction circuit 30 and output to the descrambler 38. Each signal processing circuit is the same as that described above except for the characteristics. The controller 51 stores the second sector data output from the descrambler 16 and the first sector data output to the descrambler 38 in separate areas on the RAM 56. The ECC generation / correction circuit 57 detects an error in the data in the second sector, and then performs error detection based on the data in the first sector stored in the RAM 56. If an error is detected in the data in the second sector, the sampling data in the second sector is stored in the FIFO 6. After the read operation of the second sector is completed, data reproduction is performed again by the signal processing circuit after the As correction circuit 30 using the sampling data of the FIFO 6.
[0074]
In this way, by providing a signal processing circuit for separately processing a sector in which a data error is detected, a data reproducing apparatus in which access time does not decrease with respect to up to one sector error is configured. Furthermore, it goes without saying that it is possible to cope with up to two sector errors by providing three signal processing circuits in parallel.
[0075]
As described above, according to this embodiment, even if a data error occurs, normal data processing is not hindered, and signal processing of the sector in which the data error is detected can be performed in parallel. Access time does not decrease.
[0076]
In the present embodiment, the signal processing circuit is provided in parallel, but the same processing can be realized by the configuration shown in FIG. FIG. 5 shows an example of a configuration in which data reproduction at the time of retry is processed by software. In FIG. 5, the same functions as those in FIG. 1 are denoted by the same reference numerals. For convenience of explanation, the presence / absence of a data error is determined by data error detection of the ECC generation / correction circuit 57. A reproduction signal from the recording / reproducing head 53 is input as an adin signal to the AD 4 via the signal processing circuit described above. The AD 4 samples the adin signal input asynchronously with the input signal frequency by the sampling clock generated by the read synthesizer 5 and outputs it to the FIFO 6 and the As correction circuit 8 as sampling data. Since the data demodulation processing after the As correction circuit 8 is the same as described above, the description thereof is omitted. The reproduction data obtained by the descrambler 16 is temporarily stored in the RAM 56 via the controller 51, and the ECC generation / correction circuit 57 detects a data error. As a result, when a data error occurs, the ECC generation / correction circuit 57 performs data correction using the contents of the RAM 56 and the syndrome information obtained together with the data error detection. When an error outside the error correction range occurs, the controller 51 requests the microcomputer 55 to perform a data decoding process using the FIFO 6 data. For example, the microcomputer 55 reproduces data in accordance with a processing procedure as shown in FIG. 21, and stores the obtained data in the RAM 56. Based on the data sent from the microcomputer 55, the ECC generation / correction circuit 57 detects the data error again and corrects the error after the processing of all data is completed. Here, the software processing procedure of the microcomputer 55 will be described with reference to FIG. The FIFO 6 stores sampling data from the head of the sector, and the microcomputer 55 reads and processes each one. In step 1, the data of FIFO 6 is read and the data decoding process in step 2 is performed. The data decoding process is performed by the following process. Step 100 corrects the vertical asymmetry of the sampling data, and step 101 removes the DC component of the waveform with a filter. Step 102 performs equalization processing to remove intersymbol interference of the waveform, step 103 performs waveform complement processing for complementing the synchronized waveform from the asynchronously sampled waveform, and step 104 performs amplitude adjustment. Step 105 performs the maximum likelihood decoding process using the finally obtained data. After performing such processing, step 3 detects a specific pattern (Sync) for byte synchronization and repeats the above processing until Sync is detected. After detecting Sync, in step 4, sampling data is read from the FIFO 6, and in step 5, data decoding processing is performed. Based on the obtained data, decoding is performed in step 6, and descrambling is performed in step 7. In step 8, the reproduced byte data is stored in the RAM 56 via the controller 51. In step 9, it is determined whether the data of the FIFO 6 has been processed to the end, and the processing from step 4 is executed until the processing is completed. The data demodulation is processed by such a procedure, which is the same as the data processing after the As correction circuit 30 in FIG. Therefore, when performing a retry reproduction operation by software, the As correction circuit 8, the DC correction circuit 9, the equalizer 10, the ITR circuit 11 are used to determine the constants that determine the data reproduction characteristics of steps 100, 101, 102, 103, 104, and 105. By changing the constants in the AGC circuit 12 and the ML circuit 13, the data can be decoded. In particular, since the data decoding method processed by software shown in the present embodiment can easily change each constant, data decoding can be performed by a plurality of combinations of different constants. Therefore, according to the present embodiment, the probability that data can be read is increased.
[0077]
Next, an embodiment of a signal processing circuit combining a memory and a signal processing circuit is shown.
[0078]
FIG. 22 shows an example of a signal processing circuit in which a memory and a phase synchronization circuit are combined. In FIG. 22, 220 indicates a RAM, 221 indicates a RAM control circuit, and the other components are the same as those in FIG. The same reference numerals are given. In this embodiment, a method of improving the phase synchronization accuracy by repeatedly performing phase synchronization by combining a memory and an ITR circuit is shown. Sampling data sampled by the AD 4 is processed by the signal processing circuit of the As correction circuit 8, DC correction circuit 9, and equalizer 10, and then input to the RAM 220. A specific configuration example of the ITR circuit 11, the RAM 220, and the RAM control circuit 221 is shown in FIG. In the figure, reference numerals 230, 231, 232 and 233 denote address generators. The eqout signal that is the output of the equalizer 10 is input to the RAM 234 of the RAM 220 divided into two, and stored in the address indicated by the address generator 230. The written data is once read from the address of the address generator 231 and processed by the ITR circuit 11 into phase-synchronized digital data. At this time, an address indicated by the address generator 231 is also used as a work area when processing is performed by the ITR circuit 11. The data generated by the ITR circuit 11 is again stored in the RAM 235 at the address indicated by the address generator 232, read again by the address generator 233, and output to the agcin signal. The agcin signal is output to the AGC circuit 12, the amplitude is adjusted, and then the data is decoded by the ML circuit 13. With the above configuration, the address generator 230 and the address generator 233 act as an address counter for configuring a normal FIFO, and the circuit for improving the phase synchronization accuracy shown in this embodiment is an address generator. 231 and 232, realized by ITR circuit 11.
[0079]
A specific address generation procedure is shown in FIG. The address management of the RAM 220 is performed by wr_a and rd_b managing addresses of the RAM 234 and wr_b and rd_b managing addresses of the RAM 235. The data structure of the RAM 234 is roughly divided into a variable raw_data for storing the eqout signal and a work area variable for the ITR circuit 11, and the work area variable for the ITR circuit 11 is, for example, a storage variable of the digital filter 127 in FIG. The variable filter_internal which is (the contents of the delay circuit 142) and the variable nco_internal which is the storage variable of the integrator 128 (the contents of the delay circuit 146). Step 1 initializes each address pointer and is executed only when the read gate is asserted. Among these, N_offset indicates the processing delay time for performing the repeated processing. Steps 2 to 6 are processed each time the eqout signal is input. Step 2 writes the eqout signal to the raw_data variable in the area indicated by wr_a, and step 3 outputs the data indicated by rd_a to adc_in. In step 4, the processing is controlled by the fixed_start variable. If the fixed_start variable is true, the addresses of rd_a and wr_b are subtracted by N_delay and the position is returned. Furthermore, raw_data between rd_a and rd_a + N_area is cleared, and nco_internal is fixed with fixed_nco. In these processes, for example, when the TA signal is asserted, preparations are made to perform data complementation again by ITR based on the data stored in the RAM 234. In step 5, complementary data is stored in the RAM 235 at the address indicated by wr_b using the address indicated by rd_a as a work area. In steps 4 and 5, the input data to the ITR circuit 11 between rd_a and rd_a + N_area becomes '0', so the phase control is held, and as a result, the output of the ITR circuit 11 has a fixed period (sampling indicated by fixed_nco). Complementary data sampled at intervals). Step 6 updates each address pointer. step7 is equivalent to the program describing the processing procedure of the ITR circuit 11, the function phase_error () generates the phase error filter_in from the input data raw_data, and the function filter () Complement frequency error nco_in is calculated using filter_internal which is an internal variable. The function nco () outputs the sample phase phase_offset using the obtained complementary frequency error nco_in and the internal variable nco_internal. The function interpolater () outputs complementary data from the sample phase indicated by phase_offset and the input data. By controlling the address pointer in this way, even if ITR phase tracking becomes impossible, data processing can be started again from the time when phase tracking becomes impossible. .
[0080]
For example, a specific processing method will be described in the case where a waveform as shown in FIG. 25 is input to the signal processing circuit. The input waveform has a data defect due to a missing recording medium in a part of the data. The phase synchronization response by this input signal is stable until the defect waveform at time A is input as shown in condition (a), but is unstable due to the defect waveform from time A to time B. Become. Since the input waveform becomes normal after time B, the phase synchronization response follows this, and phase synchronization is stabilized at time C. In this case, a data error occurs from time A to time C. At time B, for example, when a data error is detected at time C by the above-described data error detection method using the phase error, the variable N_delay is set to τ (0) in order to return the input data to τ (0) that is time A. ). Further, N_area corresponding to τ (0) to τ (1) is set, and phase synchronization between them is held. After τ (1), phase synchronization is resumed. However, since the defect waveform is still input to the phase synchronization circuit, the phase synchronization response becomes unstable. However, the data error length is shorter because the phase error at time B is smaller than that in condition (a) (from time A to time T (1)). Furthermore, the condition (c) is that the phase synchronization hold time is extended from τ (1) to τ (2) to suppress the amount of phase fluctuation at time B. While checking the presence or absence of errors while changing the N_area length, which is the phase synchronization hold period as described above, and finally the condition (d), the phase synchronization for the period from time A to time B is held. The phase fluctuation after time B is minimized. In this way, data reproduction with stable phase synchronization is possible.
[0081]
In this embodiment, data reproduction is performed while changing the phase synchronization hold period. However, by providing a special phase synchronization circuit as shown in FIG. 26, more efficient data reproduction processing can be performed. FIG. 26 shows an embodiment of the configuration. In the figure, 222 indicates a Reverce ITR (abbreviated as RITR), which is in reverse order to the input signal to the ITR circuit 11, that is, the sampling time is reversed. Complement data is generated for such an input signal based on the sampling data. Other symbols indicate the same functions as those in FIG. The sampling data sampled by the AD 4 is processed by the As correction circuit 8, DC correction circuit 9, and equalizer 10 as described above, and then input to the RAM 220. As shown in FIG. 28, the specific configuration of the RAM 220 is provided with address generators 240 and 241 for managing the input / output of the RITR 222 with respect to FIG. The addresses generated by the address generator 230, the address generator 231, the address generator 232, and the address generator 233 are counted up as described above, but the address generator 240 and the address generator 241 perform a count down operation. . As a result, when the digital data input to the ITR circuit 11 is x (0), x (1), x (2), x (3), ..., the digital data input to the RITR 222 is The direction opposite to the data order stored in the generator 230, that is, ..., x (3), x (2), x (1), x (0) is inputted. If the output of the ITR circuit 11 is y (0), y (1), y (2), y (3), ..., the output of the RITR222 is complemented using a signal that is temporally opposite. Data is calculated and becomes y, (3), y (2), y (1), y (0). A specific configuration of the RITR 222 will be described later. The data complemented by the ITR circuit 11 is first input to the address indicated by the address generator 232. On the other hand, the complementary data output from the RITR 222 rewrites the complementary data previously written by the address generator 232 in the reverse direction to the address indicated by the address generator 241 only when there is a data error. The complementary data finally remaining in the RAM 235 is read by the address generator 233 and output as an agcin signal.
[0082]
A specific configuration of the RITR 222 is shown in FIG. The basic configuration is the same as that of FIG. 9 except that a selection circuit 237 that reverses the complementary coefficient 1-133 is provided. Since the signal input to the RITR 222 is sampling data that is temporally reversed, the complement coefficient selection circuit 237 of the waveform complement filter 125 is temporally line symmetric with respect to the complement coefficient 1-133 shown in FIG. . Using the data complemented by the waveform complement filter 125, the phase error detector 126 calculates the phase error by calculation. Here, since the output of the waveform interpolation filter 125 is reversed in time, the phase error detector 126 performs detection opposite to the phase detection of FIG. That is, the phase advance is determined as the phase lag. However, since the phase direction of the sample phase obtained by the processing of 127 and integrator 128 is also reversed, the overall phase control direction is not changed at all. With the above configuration, complementary data can be generated based on sampling data that is reversed in time. In this embodiment, the selection circuit 237 is replaced with the complementary coefficient 1-133 shown in FIG. 9. However, the complementary coefficient 1-133 often forms a linear phase filter, and the original coefficient is linear. Since they are symmetrical, the coefficient given by the selection circuit 237 may be the same as the complement coefficient 1-133. Therefore, the RITR 222 can be realized by the same circuit as the ITR circuit 11.
[0083]
The data reproduction operation for one sector using the RITR 222 will be described with reference to FIG. Assume that the same input waveform as that in FIG. 25 is input. The phase synchronization response of the ITR circuit 11 becomes unstable from time A to time C as shown in the condition (a) by this input signal. As a result, a data error occurs from time A to time C. When the end of the data error is detected at time C by other means (not shown), the RITR 222 calculates complementary data from time C to time A using the phase synchronization information at time C as shown in condition B. Then, the complementary data up to time A until the phase is determined to be unstable is stored in the RAM 235. At this time, since the RITR 222 from time C to time B has no defect in the input signal itself, its phase synchronization response is stable, and correct complementary data is output. However, from time B to time A, the phase synchronization response becomes unstable due to the defect waveform of the input waveform. Finally, RAM 235 stores complementary data before and after time A generated by ITR circuit 11 and complementary data from time A to time C generated by RITR 222, and address generator 233 stores The complemented data is output as an agcin signal. As for the obtained agcin signal, the complementary data from time B to time C among the complementary data of RITR222 is correctly calculated. For this reason, a data error due to unstable phase synchronization is shortened in a period from time A to time B. Further, in the signal processing circuit using the RITR 222, it is not necessary to perform a plurality of iterative processes as described above, so that data decoding can be performed in a short time.
[0084]
In the present embodiment, the case where the phase synchronization response becomes stable at time C has been described, but the phase synchronization may become inoperable due to a defective waveform. On the other hand, the data decoding performance can be improved by using the sector format as shown in FIG. The sector format of FIG. 31 is processed in the order of PLO, SYNC, DATA, and ECC from the head of the sector in normal data reproduction. On the other hand, when a data error is detected, SYNC and POST areas are added after the ECC in order to enable a reproduction operation from the rear of the sector. It is sufficient that the POST area has a length equal to or less than that of the PLO area, and has a length that allows phase synchronization in the POST area. For reproduction from the back of the sector, POST, SYNC, ECC, DATA, SYNC, and PLO are read, and all supplementary data is generated from the back of the sector by RITR222. The complementary data finally stored in the RAM 235 is output from the head of the sector, and the data decoding process is performed in the subsequent circuits. A specific data processing method is shown in FIG. The phase synchronization response when data decoding is performed from the head of the sector becomes unstable due to the defect waveform after time D, and the phase synchronization becomes unstable and becomes inoperable even after passing the defect waveform. Next, when the data decoding process proceeds until time F and a data error is detected, the RITR 222 starts generating complementary data using the sample data stored in the RAM 234. The RITR 222 first performs phase synchronization in the POST area, and then stores complementary data up to the time D after the time E in the RAM 235. When the phase synchronization response becomes unstable again at time D, the writing of the complementary data to the RAM 235 is stopped here, and the complementary data in the RAM 235 is read from the head of the sector by the address generator 233, and the subsequent data is set as the agcin signal. Perform decryption. With the above processing, even when phase synchronization malfunctions due to some cause and subsequent phase synchronization becomes impossible, retry processing can be performed without reading the reproduction signal again.
[0085]
In the present embodiment, the POST area length is described as being equal to or less than the PLO area length. For example, the same process can be realized even if the POST area length is 1 byte or less. Specifically, the phase synchronization operation is performed while changing the initial value of the sample phase of the RITR222, for example, the initial value of the delay circuit 146, in the same way as the means for changing the initial value of the ITR circuit 11 and realizing the zero phase start. By doing so, the RITR222 can also start zero phase. As a result, it is possible to reduce the area for phase synchronization.
[0086]
Although the scrambler 62 is not mentioned in this embodiment, the general scrambler 62 changes the data, ECC, and POST areas after the sync byte to random data during recording. The POST area in the data format described in the present embodiment needs to be the same data as the PLO area, and the scrambler 62 needs to handle data and ECC areas excluding the POST area as random data. For this reason, the scrambler 62 is controlled by a scramble control signal as shown in FIG. 31 for discriminating the data, ECC area and POST area. Such a control signal is an indispensable signal for controlling the ECC generation / correction circuit 57 and the RAM 56 in the controller 51, and can be easily output to the recording circuit 58.
[0087]
In addition to the embodiment described above, the same processing can be realized by the configuration shown in FIG. In the figure, 223 is the same RAM as the RAM 220, and 224 and 225 are the same functions as the AGC circuit 12 and the ML circuit 13, and are added for convenience of explanation. Sampling data that is the output of AD4 is processed by a signal processing circuit from the As correction circuit 8 to the equalizer 10. The output of the equalizer 10 is input to the RAM 220 and the RAM 223, and the AGC circuit 12 and the ML circuit based on the complementary data processed by the RAM 220, the ITR circuit 11 and the RAM control circuit 221 from the head to the rear of the sector. In step 13, data decryption processing is performed. On the other hand, the RAM 223 and the RAM control circuit 221 once store data from the head data of the sector to the last data of the sector, and then generates complementary data in the direction from the last data of the sector to the head data by the RITR 222. The obtained complementary data is output in the direction from the head data of the sector to the final data by the RAM control circuit 221 and the RAM 223, and the AGC 224 and the ML circuit 225 perform data decoding processing. The two decoded data obtained from the ML circuit 13 and ML circuit 225 are equivalent to the outputs of the ML circuit 13 and ML circuit 35 as shown in FIG. 4, for example, of the SYNC detectors 14 and 36 of FIG. By connecting to the input, it functions as a signal processing circuit.
[0088]
Furthermore, FIG. 33 shows an embodiment of a signal processing circuit using other memory. In the figure, reference numeral 245 denotes a phase locked loop (VFO), and a detailed description of the configuration is omitted. Reference numeral 246 denotes a sampling clock selection circuit. The read gate signal is asserted during a head read operation using a reproduction signal from the recording / reproduction head 53 and an internal retry read operation using sampling data of the FIFO 6. The sel signal that determines the sampling clock of AD4 is, for example, “0” only in the head read operation, and “1” in other states. The sampling clock of AD4 is a clock output from the VFO 245 when sel = "0" (that is, during head read operation). On the other hand, when the head read operation is completed and the internal retry read operation is performed, ksel = “1”, and the sampling clock of AD4 becomes a clock output from the read synthesizer 5. Hereinafter, the operation of each unit will be described with respect to the head read operation.
[0089]
The AD 4 samples the analog signal obtained by processing the above-described reproduction signal with a sampling clock generated by the VFO 245. The VFO245 performs phase synchronization using either the digital data obtained by processing the sampling data that is the output of AD4 by the As correction circuit 8 or the DC correction circuit 9 or the digital data that is equalized by the equalizer 10 . The VFO 245 performs a phase pull-in operation using the output of the DC correction circuit 9 in the PLO region at the head of the sector, and then performs a phase tracking operation after the PLO region using the output of the equalizer 10.
[0090]
The equalizer 10 is connected to the TA detection circuit 17, the selection circuit 7, and the FIFO 6, and the TA detection circuit 17 controls the VGA 2 described above to make the signal amplitude constant. The FIFO 6 sequentially stores the digital data output from the equalizer 10 from the head of the sector. The selection circuit 7 inputs the output of the equalizer 10 to the ML circuit 13 because the sel signal = "0". The output of the equalizer 10 is subjected to data decoding by the ML circuit 13 and subjected to data processing by the blocks after the SYNC detector 14.
These are the same as those described above, and the description thereof is omitted.
[0091]
When the head read operation is completed and, for example, the ECC generation / correction circuit 57 determines that there is an error in the sector data, the internal retry read operation is performed with the sel signal = 1. This operation is to decode data based on the digital data stored in the FIFO 6, and is not processed using the sampling data that is the output of AD4. For this reason, it is not necessary to input the AD4 sampling clock, but in general, the circuit blocks after the As correction circuit 8 often operate using the AD4 sampling clock. It is set as the structure switched. In the internal retry read operation, the circuit blocks of the FIFO 6 and ML circuit 13 operate with the clock of the read synthesizer 5. The output of the FIFO 6 is data-decoded from the head of the processing sector, for example, by changing the characteristics of the ML circuit 13, and is processed by a circuit after the SYNC detector 14. If there is no data error due to this operation, the data reproduction operation can be performed without causing a rotation wait.
[0092]
In this embodiment, if the phase synchronization response of the VFO 245 is stable over all sectors, the data error probability is low even if the data is demodulated with the digital data of the FIFO 6, but if the VFO 245 becomes unstable and becomes inoperable, The probability is very high. Therefore, an embodiment for avoiding a data error in the retry operation even when the VFO 245 becomes inoperable will be described with reference to FIG. In the drawing, the same components as those described above are denoted by the same reference numerals. In the head read operation described above, the sel signal becomes “0”, the sampling clock of AD4 is controlled to output the clock of VFO245, and the selection circuit 7 is controlled to output the output of the equalizer 10 to the ML circuit 13, Similar data decoding is performed by the circuit block.
[0093]
Here, when the head read operation is completed and the phase synchronization of the VFO 245 becomes inoperable, for example, when the ECC generation / correction circuit 57 determines that there is an error in the sector data, the sel signal = "1" The internal retry read operation is performed. The sampling data stored in the FIFO 6 stores digital data whose phase synchronization is disabled. This is because the data is not demodulated correctly in the ML circuit 13 because the phase synchronization with the input analog signal is not performed, and the data itself is not missing. Therefore, the ITR circuit 11 and the AGC circuit 12 estimate complementary data that is stable in both phase and amplitude from the sampling data stored in the FIFO 6. The complementary data is decoded again by the ML circuit 13 and the subsequent processing is performed. As a result, if there is no data error, the data reproducing operation can be performed without waiting for rotation.
[0094]
Next, an example of a signal processing circuit capable of reproducing a lower S / N signal will be described with reference to FIG. In the figure, reference numeral 250 denotes an averaging circuit, and the other blocks are denoted by the same reference numerals as those described above. The sampling data stored in the FIFO 6 is data storing the previous read signal of the same sector. Specifically, as shown in FIG. 36, the sampling data of the FIFO 6 stores one sector on one track stored in the rotating magnetic recording medium 54. The sampling data stored in the FIFO 6 is assumed to store, for example, digital data after sync byte detection. Next, when the magnetic recording medium 54 rotates once and reproduces the same sector, the averaging circuit 250 averages the sampling data of the FIFO 6 stored in the previous read operation and the digital data currently output by the AGC circuit 12. And the ML circuit 13 decodes the data. Averaging averages the digital data after detection of the sync byte and the digital data stored in the FIFO 6, so that the digital data after the sync byte input to the ML circuit 13 is subjected to synchronous addition processing of the same sector. The As a result, the processed signal amplitude remains the same, and only the noise superimposed on it is attenuated by the square root of 1/2. As a result, the signal S / N input to the ML circuit 13 is improved by 3 dB, and the lower S / N signal playback is possible.
[0095]
Next, an embodiment of a TA removal circuit will be described with reference to FIG. Also in this embodiment, the processing is executed by the above-described two-sector data read operation. In the figure, 255 and 257 indicate subtracters, 256 indicates a DA converter, and the other functions described above are denoted by the same reference numerals. The subtractor 255 subtracts the output of the DC correction circuit 9 from the output of the As correction circuit 8, and outputs a DC component of the output of the As correction circuit 8, for example, a TA baseline signal. When TA is detected in the first sector read operation, the TA baseline signal is stored in the FIFO 6 via the subtractor 255. Next, in the second sector read operation, the TA baseline signal, which is digital data stored in the FIFO 6, is converted into an analog signal by the DA converter 256, and the analog signal is subtracted by the subtractor 257. Since the position of TA is generally fixed, the output of subtracter 257 is subtracted from the TA waveform stored in the previous read operation, so that a waveform without baseline fluctuation due to TA is input to AD4. The As a result, there is no baseline fluctuation due to TA, and data decoding errors due to malfunction of the signal processing circuit after the equalizer 10 do not occur.
[0096]
FIG. 39 shows an example of a chip layout of a read channel LSI in which the recording circuit 58 and the reproducing circuit 60 of the present invention are sealed in one LSI. The chip layout of the read channel LSI using the present invention is characterized in that it includes a memory circuit area, which is a main component of the FIFO, in a size that can be understood. The conventional read channel LSI chip layout consists of only an analog circuit area where chip layout is performed manually and a digital circuit area where automatic layout is performed by a calculator, etc., so that the memory circuit area is large enough to be understood. This can be easily determined from a chip photograph.
[0097]
In order to realize a compact layout, the memory constituting the FIFO of the present invention is regularly arranged separately from the digital circuit area composed of random circuits. In addition, the number of input / output bits and the capacity of the memory are specialized for its use, so the presence of the memory area of the present invention can be easily confirmed from the chip photograph in addition to the conventional analog circuit area and digital circuit area. The
[0098]
The specific storage capacity of the memory circuit is about 550 bytes in the sector, which is the basis of the disk recording / playback operation. Therefore, according to the 16/17 code rate conversion, the storage capacity is about 4700 samples. Further, since an AD circuit used in a disk device generally outputs an analog signal as a 6-bit digital signal, the number of input bits of a memory connected thereto is an integral multiple of 6 bits. The number of input / output bits of the memory is determined from the sampling frequency of the AD circuit and the limit of the operation speed of the memory. When the transfer rate is about 400 Mbit / s, it is generally 24 bits that are 4 parallelized. Since the memory is also required to have high speed, a static memory configuration is generally adopted.
[0099]
FIG. 40 shows an example of a chip layout of a data recording / reproducing LSI in which the controller 51, RAM 56, ECC generation / correction circuit 57, and microcomputer 55 are sealed in one LSI in addition to the recording circuit 58 and the reproducing circuit 60 described above. Is. Since the controller 51, the ECC generation / correction circuit 57, and a part of the microcomputer 55 are random circuits, automatic layout is performed in the same manner as the digital circuit described above. On the other hand, the RAM 56 is the same memory as the FIFO 6, but has a large difference in capacity and structure. The FIFO 6 has a high-speed static memory configuration of about several kilobytes, and the RAM 56 has a dynamic memory configuration of about several megabytes. For this reason, the presence of the memory area of the present invention can be easily confirmed from a chip photograph of a data recording / reproducing LSI having a large circuit scale.
[0100]
【The invention's effect】
According to the present invention, in the signal processing circuit using the sampling data stored in the storage means and the magnetic recording / reproducing apparatus that implements the same, it is possible to shorten the recovery processing time of the data error that occurs due to the defect of the recording medium. It becomes possible. As a specific example, assuming that the time required for one rotation of the recording medium is 10 ms (corresponding to a rotation speed of 6000 rpm), the number of times of data recovery is 10 times, and the processing time per sector is 250 μs, the conventional data recovery processing is about 100 ms (10 ms However, according to the present invention, processing can be performed in about 2.5 ms (250 μs × 10 times). Thus, the recovery time can be greatly shortened.
[0101]
Similarly, the present invention can be applied to a case where repetitive processing is performed using a reproduction signal from a magnetic recording medium. For example, the present invention can be applied to optimization of circuit parameters such as a signal processing circuit and registration of a recording medium defect position of a magnetic recording / reproducing apparatus, and the processing time can be shortened.
[0102]
Further, according to the present invention, it is possible to minimize a bursty data error length caused by a recording medium defect or the like. Generally, a burst error longer than the defective medium length occurs due to a variation in the phase synchronization response caused by a defect in the recording medium. According to the present invention, there is an effect of suppressing occurrence of a burst error longer than the defective medium length by correcting the phase synchronization response fluctuation after the defect passage of the storage medium.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a magnetic recording / reproducing apparatus using a signal processing circuit of the present invention.
FIG. 2 is a configuration diagram of another signal processing circuit of the present invention.
FIG. 3 is a configuration diagram of another signal processing circuit of the present invention.
FIG. 4 is a configuration diagram of another signal processing circuit of the present invention.
FIG. 5 is a configuration diagram of another signal processing circuit of the present invention.
FIG. 6 is a configuration diagram of an embodiment of an As correction circuit according to the present invention.
FIG. 7 is a configuration diagram of an embodiment of a DC correction circuit according to the present invention.
FIG. 8 is a configuration diagram of an embodiment of an equalization circuit according to the present invention.
FIG. 9 is a configuration diagram of an embodiment of a complementary phase synchronization circuit according to the present invention.
FIG. 10 is a configuration diagram of an embodiment of an amplitude adjustment circuit according to the present invention.
FIG. 11 is a configuration diagram of an embodiment of a switching condition generation circuit according to the present invention.
FIG. 12 is a configuration diagram of an embodiment of a maximum likelihood decoding circuit according to the present invention.
FIG. 13 is another configuration diagram of the maximum likelihood decoding circuit according to the present invention.
FIG. 14 is a configuration diagram of an embodiment of a switching condition generation circuit in the maximum likelihood decoding circuit according to the present invention.
FIG. 15 is a configuration diagram of an embodiment of a sync detection circuit according to the present invention.
FIG. 16 is a configuration diagram of an embodiment of a decoder circuit according to the present invention.
FIG. 17 is a configuration diagram of an embodiment of an error detection and correction circuit according to the present invention.
FIG. 18 is a diagram showing an example of a data processing method using a FIFO.
FIG. 19 is a configuration diagram of an embodiment of a FIFO circuit according to the present invention.
FIG. 20 is a diagram illustrating an example of input / output signals of a FIFO circuit.
FIG. 21 is a diagram showing a software processing procedure in the present invention.
FIG. 22 is a configuration diagram of an embodiment of a signal processing circuit using a RAM according to the present invention.
FIG. 23 is a block diagram of an embodiment of a RAM peripheral circuit according to the present invention.
FIG. 24 is a diagram showing an example of a RAM control procedure.
25 is a diagram showing an operation example of the signal processing circuit in FIG. 22;
FIG. 26 is another configuration diagram of a signal processing circuit using a RAM according to the present invention.
FIG. 27 is another configuration diagram of a signal processing circuit using a RAM according to the present invention.
FIG. 28 is another configuration diagram of a RAM peripheral circuit in the present invention.
FIG. 29 is a configuration diagram of an embodiment of a reverse complement type phase locked loop according to the present invention.
FIG. 30 is a diagram illustrating an operation example of a reverse complement type phase locked loop circuit;
FIG. 31 is a diagram showing a data format having a reverse complement type phase synchronization circuit;
FIG. 32 is a diagram showing another operation example of the reverse complement type phase locked loop circuit;
FIG. 33 is a configuration diagram of another signal processing circuit of the present invention.
FIG. 34 is a configuration diagram of another signal processing circuit of the present invention.
FIG. 35 is a configuration diagram of another signal processing circuit of the present invention.
36 is an operation conceptual diagram of the signal processing circuit in FIG. 35. FIG.
FIG. 37 is a block diagram of an embodiment of a TA removal circuit according to the present invention.
FIG. 38 is a configuration diagram of a general magnetic recording / reproducing apparatus.
FIG. 39 is a block diagram showing an example of a chip layout of a read channel LSI in the present invention.
FIG. 40 is a configuration diagram of an example of a chip layout of a data recording / reproducing LSI according to the present invention.
[Explanation of symbols]
1 ... HPF, 2 ... variable gain amplifier, 4 ... AD converter, 5 ... lead synthesizer,
6 ... FIFO, 7 ... selection circuit, 8 ... As correction circuit, 9 ... DC correction circuit,
10 ... equalization circuit, 11 ... complementary phase synchronization circuit, 12 ... amplitude correction circuit,
13 ... Maximum likelihood decoding circuit, 14 ... SYNC detection circuit, 15 ... Decoder,
16 ... descrambler, 18 ... coefficient learning circuit, 55 ... microcomputer,
57 ... ECC generation and correction circuit, 51 ... Controller, 56 ... RAM,
58 ... Recording circuit, 60 ... Reproducing circuit, 221 ... RAM control circuit,
222: Reverse complementary phase synchronization circuit.

Claims (6)

A disk for recording sector data;
A head for reading the sector data from the disk;
A first signal processing unit that performs signal processing on the sector data read by the head to generate and output sampling data;
After performing predetermined signal processing on the sampling data output from the first signal processing unit , the synchronization pattern detection means detects the synchronization pattern, the decoder performs the decoding process, A second signal processing unit that performs descrambling processing by a descrambler and outputs first reproduction data;
A storage unit for storing the sampling data output from the first signal processing unit;
For each of the sampling data stored in the storage unit, each process performed in the second signal processing unit is performed by changing a constant for determining reproduction characteristics by software, and the second reproduction data is output. A microcomputer,
A data recording / reproducing apparatus comprising: An ECC generation correction unit that detects an error in the reproduction data and corrects the data; and a controller connected to the ECC generation correction unit and the microcomputer,
When the ECC generation correction unit detects that the first reproduction data has an error outside the error correction range, the controller causes the microcomputer to perform each process on the sampling data stored in the storage unit. The data recording / reproducing apparatus according to claim 1, wherein the second reproduction data is output.   When the first reproduction data is held and the ECC generation / correction unit detects that the first reproduction data has an error outside the error correction range, the first reproduction data is stored in the second reproduction data. The data recording / reproducing apparatus according to claim 2, further comprising a RAM that is replaced with reproduction data. A disk for recording sector data;
A head for reading the sector data from the disk;
Having a storage unit, and performing signal processing on the sector data read by the head to generate sampling data , performing predetermined signal processing on the sampling data, and then using a synchronization pattern detection unit A channel LSI for detecting a synchronization pattern, performing a decoding process by a decoder, performing a descrambling process by a descrambler , outputting first reproduction data, and storing the sampling data in the storage unit;
The processing for outputting the first reproduction data by the channel LSI is performed on the sampling data stored in the storage unit by changing constants for determining reproduction characteristics by software, and the second reproduction is performed. A microcomputer that outputs data,
A data recording / reproducing apparatus comprising: An ECC generation correction unit that detects an error in the reproduction data and corrects the data; and a controller connected to the ECC generation correction unit and the microcomputer,
When the ECC generation / correction unit detects that the first reproduction data has an error outside the error correction range, the controller causes the microcomputer to perform each process on the sampling data stored in the storage unit. 5. The data recording / reproducing apparatus according to claim 4, wherein the second reproduction data is output.   When the first reproduction data is held and the ECC generation / correction unit detects that the first reproduction data has an error outside the error correction range, the first reproduction data is stored in the second reproduction data. 6. The data recording / reproducing apparatus according to claim 5, further comprising a RAM that is replaced with reproduction data.

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