JP2000048490A - Signal processor and data recording/reproducing device installed with the processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve data reliability at a data recovery time by providing a storage means for storing a reproducing signal and reproducing the data with a different control parameter based on the stored reproducing signal. SOLUTION: A selection circuit 165 selects one of a phase error signal, a complementary frequency error and an amplitude error by a conditional selection signal to output it to a comparator 166 as the error signal. A delay circuit 167 stores the output of the comparator 166 at every sample, and a decision circuit 168 judges the lapse of time of the error signal from the output of the delay circuit 167 to assert a switch condition. For instance, when a phase error or the amplitude error of a threshold or above is continued, the decision circuit 168 detects the continuance of '1' in the outputs of the delay circuit 167 to make the switch condition active. Further, when the complementary frequency error is different to the threshold or above, the decision circuit 168 makes similarly the switch condition active. This switch condition is imparted to a microcomputer through a register.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing method for a magnetic disk or an optical disk device or the like.
The present invention relates to a signal processing method for improving data reliability during data recovery.

[0002]

2. Description of the Related Art In recent years, in a signal processing device such as a magnetic disk device, a partial response maximum likelihood decoding (Partial Response Max.
imum Likelihood (hereinafter abbreviated as PRML) is commonly used. A typical PRML signal processing method of a magnetic disk drive is “Viterbi Detection of C” by ROGER W. WOOD and the like.
lass IV Partial Response on a Magnetic Recording C
hannel '' (IEEE Transactions on communications.VOL.C
OM-34, No. 5, MAY 1986 pp 454-461). In addition, Extended PRML (E
PRML) signal processing methods have also been adopted as signal processing methods for disk devices, and are disclosed in JP-A-7-201135 and JP-A-8-116275. On the other hand, sampling of a signal waveform in the PRML signal processing method is performed by a phase synchronizer, and is performed as shown in JP-A-1-143447 and JP-A-2-21919. Recently, Japanese Patent Application Laid-Open
As described in 231506, from an asynchronously sampled data, a complementary phase locked loop (Interpolated Timing Rec) which generates synchronized desired sample data by interpolation.
overy (hereinafter abbreviated as ITR) has also been proposed.

FIG. 38 shows a configuration example of a general magnetic disk drive using a PRML signal processing method.

The magnetic recording medium 54 is a circular rotating magnetic recording medium for storing data from an external processing device. Data recording / reproducing processing is performed on concentric tracks in units of blocks called sectors. The track on the magnetic recording medium 54 has servo information at regular intervals, and the servo control circuit 52 causes the recording / reproducing head 53 to follow the rotating track. Perform positioning.
The other blocks record / reproduce data from the external processing device, and operate as follows.

A data recording operation is started by a write command from an external processing device. The write command is sent to the microcomputer 55 via the controller 51, and the microcomputer 55
The controller 51 issues a recording control command to the servo control circuit 52. The controller 51 temporarily stores the recording data from the external processing device following the recording instruction in the RAM 56. The servo control circuit 52 moves the recording / reproducing head 53 to a predetermined track on the magnetic recording medium 54. After the movement of the recording / reproducing head 53 is completed, the data temporarily stored in the RAM 56 includes a synchronizing signal required for reproduction and an error correction code generated by the ECC generation / correction circuit 57, and a recording circuit 58.
Sent to The recording circuit 58 modulates this data as required for the PRML signal processing method, and the recorded data is
59, recorded in the sector of the designated track via the recording / reproducing head 53.

On the other hand, the operation of reproducing data from the magnetic disk device is started by a read command from an external processing device. The microcomputer 55 that has received the read command issues a read control command to the servo control circuit 52 and the controller 51. The servo control circuit 52 moves the recording / reproducing head 53 to a track where the specified data is stored. After the movement of the recording / reproducing head 53 is completed, the controller 51 instructs the reproducing circuit 60 to start a reading process. Magnetic recording media
The recording information on 54 is transmitted as a reproduction signal to a reproduction circuit 60 via a recording / reproduction head 53 and an RW amplifier 59. Regeneration circuit 60
Is converted into a sample data sequence synchronized with the reproduction signal based on the synchronization signal added at the time of recording, and the PRML signal processing circuit demodulates the data based on this. The demodulated data is temporarily stored in the RAM 56, and when an error exists in the data, the ECC generation / correction circuit 57 corrects the data error. If there is no error in the demodulated data, or if the error can be corrected by the ECC generation / correction circuit 57, the data is transferred to the external processing device via the controller 51 as reproduction data. On the other hand, when the error cannot be corrected by the ECC generation / correction circuit 57, the microcomputer 55 executes the reading process again until the data can be correctly reproduced while changing various control parameters. If the data is read correctly,
The reproduction data in the RAM 56 is transferred to an external processing device via the controller 51. If it is not read correctly, it is reported to the external processing device as a reproduction error. In addition to the data recording / reproducing operations described above, a defect registration process for detecting the defect position and length of the magnetic recording medium 54, a recording circuit 58, and a reproducing circuit 60
A circuit constant optimizing process for correcting the variation in the characteristic is also performed.

With the above-described configuration, the conventional magnetic recording / reproducing apparatus performs a data recording / reproducing operation.

[0008]

In the data recording / reproducing process as described above, if the code word is within the error correction range of the ECC generation / correction circuit 57, the corrected data is immediately transferred to the external processing device. However, the ECC generation and correction circuit 57
When an error that cannot be corrected by the above occurs, the reading process is executed again. For this reason, a data waiting time until the magnetic recording medium 54 rotates and the sector can be read, that is, a so-called rotation waiting occurs, and a reduction in data access time becomes a problem.

Furthermore, a partial loss of recorded information caused by a defect in the magnetic film of the magnetic recording medium 54 may cause a malfunction of the phase locked loop circuit. In such a case,
It is unlikely that success will occur even if the data playback operation is performed again.
Unnecessary rotation waiting occurs. As a result, the data access time is significantly reduced.

Further, tests such as optimization of the circuit constants of the signal processing circuit and checking of disk defects are performed by repeatedly performing a test based on a reproduced signal from the disk while changing circuit constants. The increase in time becomes a problem.

A first object of the present invention is to provide a signal processing device for reducing rotation waiting due to a data error.

A second object of the present invention is to provide a signal processing apparatus for reducing a data burst error caused by a malfunction of a phase locked loop.

A third object of the present invention is to provide a signal processing device capable of optimizing a circuit constant or shortening a test time of a magnetic recording / reproducing device.

[0014]

SUMMARY OF THE INVENTION A first object of the present invention is to provide:
This is realized by providing storage means for storing a reproduction signal and performing data reproduction with different control parameters based on the stored reproduction signal.

By the storage means, the reproduction operation can be repeatedly performed with different control parameters without waiting for rotation.

In addition, a storage means for storing a reproduction signal obtained by reproducing the same sector a plurality of times,
The first object of the present invention is also achieved by providing an averaging means for averaging the input reproduced signal. By improving the signal S / N by the storage means and the averaging means, the reliability of the second and subsequent data reproducing operations can be improved.

A second object of the present invention is to provide a storage means for storing a reproduction signal and a sampling data generating means for reproducing sampling data phase-synchronized from the stored reproduction signal, wherein a phase synchronization circuit after a data defect is provided. Is achieved by suppressing the erroneous operation by the sample data generating means.

A third object of the present invention is to provide a storage means for storing a reproduction signal, to optimize circuit constants, or to repeat a test of a magnetic recording / reproducing apparatus using the reproduction signal stored in the storage means. It is realized by doing.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of a signal processing circuit for achieving the first object of the present invention and a magnetic recording / reproducing apparatus using the same. The basic configuration is the same as that of the conventional example, but the blocks constituting the reproducing circuit 60 are different. The recording circuit 58 includes a write synthesizer 61 for determining a data recording frequency, a scrambler 62 for randomizing a recording data sequence,
It comprises an encoder 63 for modulating data, a precoder 64, and a recording correction circuit 65 for correcting nonlinear distortion inherent to magnetic recording. The reproduction circuit 60 is roughly classified into an analog block that processes an analog signal from the RW amplifier 59 and a digital block that processes a digital signal obtained by sampling the analog signal. The analog block consists of an HPF1 that blocks low-frequency signals, a variable gain amplifier 2 (hereinafter abbreviated as VGA) to keep the input signal amplitude constant, an LPF3 that removes high-frequency noise, and a digital signal that samples analog signals. AD converter (hereinafter abbreviated as AD) 4, a read synthesizer 5 for determining a sampling frequency, and a thermal for detecting a baseline fluctuation of a signal waveform caused by contact between the recording / reproducing head 53 and the magnetic recording medium 54. And an asperity (TA) detection circuit 17. The digital block consists of a FIFO 6 that stores the digital signal sampled by the AD 4, a selection circuit 7 that selects the digital signal, an As correction circuit 8 that digitally corrects the vertical asymmetry of the analog signal, DC correction circuit 9, which corrects the waveform, equalizer 10 which performs waveform equalization,
A coefficient learning circuit 18 for optimizing the characteristics of the equalizer 10, and a complementary phase-locked loop circuit for generating a digital signal synchronized with the recording timing from a digital signal sampled asynchronously.
(Hereinafter abbreviated as ITR) 11, a gain control circuit 19 for adjusting the digital signal amplitude to be constant, and an amplitude correction circuit (hereinafter abbreviated as AGC circuit) 1
2, a maximum likelihood decoding circuit (hereinafter abbreviated as ML) 13 for decoding data of a digital signal by a maximum likelihood decoding method, a SYNC detector 14 for performing byte synchronization, a decoder 15 for demodulating data, and randomizing with a scrambler 62 Descrambler 16, which converts the reconstructed data back into the original data sequence, and a playback circuit
It comprises a register 20 for controlling 60 operation modes.

The operation of the above magnetic recording / reproducing apparatus will be described. First, the recording operation will be described in detail. The recording operation is started by a write command from the external processing device. The write command is sent to the microcomputer 55 via the controller 51,
The microcomputer 55 issues a recording control command to the controller 51 and the servo control circuit 52. The controller 51 temporarily stores the user data from the external processing device following the recording instruction in the RAM 56. The servo control circuit 52 receives the recording control command and moves the recording / reproducing head 53 to a predetermined track on the magnetic recording medium 54. After the movement of the recording / reproducing head 53 is completed, the controller 51 detects the recording position of the sector from the servo information, and sets the write gate to the recording circuit.
Assert for 58. At the same time, the controller
51 is PLO data for performing bit synchronization with the recording circuit 58
(PLO), and after outputting SYNC data (SYNC) for performing byte synchronization, outputs the user data (DATA) stored in the RAM 56 and the error correction code (ECC) generated by the ECC generation and correction circuit 57. The recording circuit 58 processes a series of data strings based on a clock generated by the write synthesizer 61. SYNC
In the subsequent DATA and ECC, data randomization by the scrambler 62 and data modulation by the encoder 63 (for example, block modulation from 8 bits to 9 bits) are performed in units of byte data. In addition, the precoder 64
Modulation such as 1 / (1 + D ^ 2) is performed on the entire data string after O. Here, the symbol D ^ 2 indicates a bit two clocks before the modulated recording data, and the operator + indicates an exclusive OR. The recording correction circuit 65 determines a data pattern of a plurality of bits in order to reduce the non-linear distortion inherent to magnetic recording, and sets the recording bit position to several tens% of one bit interval.
Back and forth. A series of data strings obtained as described above is recorded in the sector on the magnetic recording medium 54 via the RW amplifier 59 and the recording / reproducing head 53.

Next, the reproducing operation will be described in detail. The operation of reproducing data from the magnetic recording / reproducing device is started by a read command from an external processing device. The microcomputer 55 that has received the read command issues a read control command to the servo control circuit 52 and the controller 51.

The servo control circuit 52 moves the recording / reproducing head 53 to a designated track. After the movement of the recording / reproducing head 53 is completed, the controller 51 detects the reproducing position of the sector from the servo information and sets the read gate to the reproducing circuit.
Assert for 60. Information recorded on the magnetic recording medium 54 is transmitted to a reproducing circuit 60 via a recording / reproducing head 53 and an RW amplifier 59.
Is transmitted as a reproduction signal. Playback signals are HPF1, LPF3
VGA2, gain control circuit 19, AG so that the noise outside the signal band is removed and the input amplitude to the ML circuit 13 is constant.
It is controlled by the C circuit 12. When TA is detected by the TA detection circuit 17, the microcomputer 55 detects the occurrence of TA through the register 20 and increases the cutoff frequency of HPF1 to increase the TA.
Minimize baseline fluctuations. The reproduced signal subjected to the waveform processing in this manner is sampled as a digital signal by the AD 4 in accordance with the sampling clock generated by the read synthesizer 5. The sampling clock frequency of the read synthesizer 5 does not necessarily need to be synchronized with the frequency and phase of the reproduction signal, and the ITR circuit 11 synchronizes the frequency and phase.
The digital signal sampled by the AD 4 is stored in the FIFO 6 and output to the As correction circuit 8 via the selection circuit 7. Normally, the selection circuit 7 selects the output of the AD4 by the sel signal (= 0) of the register 20 set by the microcomputer 55. The output of the FIFO 6 is output to the As correction circuit 8 by setting the sel signal (= 1) of the register 20 when the microcomputer 55 determines that data reproduction is necessary again. The output signal of the selection circuit 7 is decoded into a bit string via an As correction circuit 8, a DC correction circuit 9, an equalizer 10, an ITR circuit 11, an AGC circuit 12, and an ML circuit 13 whose characteristics can be changed by the sel signal. (These configuration examples will be described later.) Further, the SYNC detector 14 performs byte synchronization based on the obtained bit string, the decoder 15 performs inverse conversion of the encoder 63 to demodulate data, and the descrambler 16 converts the data to the original user data. The obtained user data is temporarily stored in the RAM 56, and error correction of the data is performed by the ECC generation / correction circuit 57. There is no error in the read data or the ECC generation and correction circuit 57
If the error can be corrected in step (1), the converted data string is transferred to the external processing device via the controller 51 as reproduction data. On the other hand, when the error cannot be corrected by the ECC generation and correction circuit 57, the microcomputer 55 sets the sel signal (= 1) and
Using the output of IFO6, As correction circuit 8, DC correction circuit 9, equalizer 10, ITR circuit 11, AGC circuit 12, ML circuit 1 with different characteristics
3. Until the data can be correctly reproduced by the SYNC detector 14, the data reproducing operation is repeated only inside the reproducing circuit 60. If data is read correctly, RAM56
Is transferred to the external recording device via the controller 51, but if it is not read correctly, the data reproducing operation of the magnetic recording / reproducing device is repeated again.

If the data is still not correctly reproduced, a reproduction error is reported to an external processing device.

The recording / reproducing operation of the magnetic recording / reproducing apparatus is realized by the above processing.

Here, an As correction circuit 8, a DC correction circuit 9, an equalizer 10, an ITR circuit 11, an AGC circuit 12, an ML circuit 13 having different characteristics.
The following shows an example of the circuit configuration. In addition, a method of generating sel signal generation conditions other than whether or not error correction is possible by the ECC generation and correction circuit 57 will be described.

First, one embodiment of the As correction circuit 8 is shown in FIG. FIG. 6 (a) shows the input / output characteristics of the output signal amplitude with respect to the input signal amplitude of the As correction circuit 8. Is shown. One embodiment of the As correction circuit 8 for realizing such input / output characteristics is shown in FIG. 6 (b). In the figure, 100 is a multiplier, 101 and 103 are selection circuits, and 102 is a sign determination circuit. The sign judgment circuit 102 judges the sign of the input signal, and switches the input of the selection circuit 103 according to the judgment result. Here, the selection circuit 103 outputs the output of the multiplier 100 when the input signal is positive, and outputs the input itself when the input signal is negative. The selection circuit 101 determines the gain on the positive side of the input signal and determines the degree of the polygonal line. When the sel signal = 0 in the normal state, gain1 is selected, and as a result, the multiplier of the multiplier 100 is gain1 (= 1.0). On the other hand, when the sel signal = 1, gain2 is selected and the multiplier
The multiplier of 100 is gain2 (= 0.5). Therefore, the input / output characteristics of the As correction circuit 8 are linear when the sel signal = 0, and the sel signal = 1
In the case of, the polygonal line is 0.5 on the positive side. With the configuration as described above, the As correction circuit 8 capable of changing the circuit constant is realized.

Next, one embodiment of the DC correction circuit 9 is shown in FIG.
In the figure, 110 is a delay circuit, 111 and 112 are averaging circuits, 113 and 11
4 is a subtractor, and 115 is a selection circuit. The ITR circuit 110 is obtained by delaying the input data for each sampling clock. If the input data at time n is x (n), the output of each ITR circuit 110 is x (n), x (n-
1), ..... x (n-8). The averaging circuits 111 and 112 calculate the average of the input data, and the output y1 (n) of the averaging circuit 111 is given by the following equation.

[0029]

Y1 (n) = Σ {x (k)} / 6 k = n〜n−5 Expression 1 The output y2 (n) of the averaging circuit 112 is given by the following equation.

[0030]

Y2 (n) = Σ {x (k)} / 9 k = n to n−8 Expression 2 The averaging circuits 111 and 112 having different average lengths are low-pass filters having different frequency characteristics. Therefore, the extraction characteristics of the low frequency signal such as the TA waveform are different. The outputs of the subtractors 113 and 114 become DC correction circuits having different TA removal characteristics by subtracting the outputs of the averaging circuits 111 and 112 and the input signal of the DC correction circuit 9.
The selection circuit 115 selects such a different DC correction circuit based on the sel signal. As a result, the DC correction circuit 9 is a circuit whose DC correction characteristics can be changed.

FIG. 8 shows an embodiment of the equalizer 10 having different equalization characteristics. In the figure, 120 is a delay circuit, 121 is a multiplier, 122
Denotes an adder and 123 denotes a coefficient selection circuit. Delay circuit 1
The multiplier 20, the adder 121, and the adder 122 constitute an FIR filter, and changing the coefficient of the multiplier 121 changes its frequency characteristic. The coefficient selection circuit 123 is a coefficient group prepared in advance or obtained by the coefficient learning circuit 18.
1 or coefficient group 2 is selected by the sel signal. As a result, the equalizer 10 can perform equalization processing with different frequency characteristics.

Next, an embodiment of the ITR circuit 11 having a different phase synchronization response is shown in FIG. In the figure, 125 is the waveform complement filter, 12
6 is a phase error detector, 127 is a digital filter, and 128 is an integrator. The waveform complementing filter 125 is a linear filter that complements the waveform of the sample phase indicated by the integrator 128 based on the asynchronously sampled digital signal, and specifically, a delay circuit 130, a multiplier 131, vessel
It consists of 132 FIR filters. The complement coefficient of the multiplier 131 is given by a complement coefficient 1-133 and a complement coefficient 2-134.
It is possible to change the complementary characteristic. Phase error detector 126
Is the same as the conventional one, the data decision unit 136, the delay circuit 137,
It comprises a multiplier 138 and a subtractor 139. The obtained phase error is smoothed by a digital filter 127 composed of multipliers 140a and 140b, an adder 141 and a delay circuit 142, and an integrator 128 composed of an adder 145 and a delay circuit 146. The output of 128 determines the sample phase of the waveform complement filter 125.

Here, the operation of a circuit block whose characteristics can be changed by the sel signal will be described.

The frequency characteristic of the digital filter 127 is determined by the multiplier of the multipliers 140a and 140b,
Alternatively, it can be changed by selecting the coefficient group 2 by the selection circuit 144. Digital filter
The transfer function Hf (z) of 127 and the open loop transfer function Ho (z) of the ITR circuit 11 are as follows, where A1 is the coefficient of the multiplier 140a, A2 is the coefficient of the multiplier 140b, and K is the loop gain. It is represented by the formula.

[0035]

[Formula 3] Hf (z) = A1 * {(1 + A2 / A1) -z} / (1-z)... Formula 3 Ho (z) = K * Hf (z) / (1-z) Can be obtained by substituting z = exp (-j2πf / fs) into the above function. Here, f is a frequency, fs is a sampling frequency, j is an imaginary unit, and exp () represents an exponential function. The digital filter 127 configured as above is
It is known as a digital filter having lag-lead characteristics, and its corner frequency is determined by the ratio of the coefficient A2 / A1. When the ratio A2 / A1 is high, the corner frequency of the digital filter 127 increases, and as a result, the zero-cross frequency of the open loop frequency characteristic Ho (z) of the ITR circuit 11 also increases. When the open loop frequency characteristic Ho (z) increases, the ITR circuit 11
Is improved, but the sampling error with respect to noise increases. Therefore, the S /
In the re-read operation due to the decrease in N, the coefficient ratio A2 / A1 is set small in order to stably follow the phase synchronization.

The delay circuit 142 stores data relating to the difference between the sampling frequency and the reproduction signal frequency. The normal ITR circuit 11 completes frequency / phase synchronization within the PLO region. However, the rotation speed of the recording / reproducing head 53 fluctuates,
If the error between the sampling frequency and the reproduction signal frequency becomes large, the frequency synchronization time cannot be secured in the PLO region, and the subsequent data reproduction becomes impossible. Therefore, by selecting the initial values F0 and F1 by the selection circuit 143, the difference between the sampling frequency and the reproduction signal frequency is reduced to a synchronizable range, and the frequency / phase synchronization is completed in the PLO region.

The delay circuit 146 determines the sample phase for which the waveform is to be complemented by the waveform complementing filter 125, and normally completes the frequency / phase synchronization within the PLO region as described above. However, if PLO data of a sufficient length is not input to the ITR circuit 11 due to a defect in a reproduced waveform or the like, the phase synchronization time in the PLO region cannot be secured, and similarly, subsequent data reproduction becomes impossible. . So this is the initial value
By selecting P0 and P1 by the selection circuit 147, the initial phase can be changed. Given an appropriate initial phase, ITR circuit 1
1 is the zero phase start, and the PLO area can be shortened. By synchronizing the reproduction data of the FIFO 6 with the phase while changing the initial value of the sample phase, the phase synchronization can be reliably performed even if the PLO area is short. Further, even if there is no PLO area, it is possible to perform the phase synchronization by changing the initial values of P0 and P1 until a Sync byte is detected in the SYNC area. This can be realized because the sampling data is stored in the FIFO 6, and cannot be realized by the conventional method. According to this method, the PLO area can be reduced, and the area for recording data can be expanded.

The selection circuit 135 changes the interpolation coefficient of the waveform interpolation filter 125. When the error between the sampling frequency and the reproduction signal frequency increases, the estimation error due to data interpolation increases, and as a result, the data demodulation performance increases. Leads to a decrease in Therefore, it is also possible to change the complement coefficient by the sel signal and improve the data complement accuracy.

Although the present embodiment described above does not consider the clock control based on the overtaking / overtaking of the sampling, the processing method is the same as the conventional one, and therefore, the description is omitted.

Next, one embodiment of the AGC circuit 12 having different amplitude synchronization responses is shown in FIG. In the figure, 150 is a multiplier, 151 is an amplitude error detector, 152 is a multiplier, and 153 is an integrator. The amplitude error detector 151 is the same data decision unit 15 as the conventional one.
5, composed of a subtractor 156, a multiplier 157, a delay circuit 158, and an adder 159, and generates an amplitude error between the output signal and the target amplitude determined by the selection circuit 164. The multiplier 152 multiplies the amplitude error by a multiplier determined by the selection circuit 163,
Output to the integrator 153 composed of the delay circuit 161. An integrator 153 calculates an error gain by integrating the amplitude error, and a multiplier 150 multiplies the input signal by the error gain to obtain an AGC circuit.
Assume 12 outputs.

These round operations are usually completed within the PLO region, and the delay circuit 161 is given an error gain between the input waveform and the target amplitude. However, if amplitude synchronization is not completed due to a defect or the like in the PLO area, subsequent reproduction of user data becomes impossible. Therefore, at the time of reproduction data from the FIFO 6, by selecting the initial values G00 and G01 by the selection circuit 162, the initial error gain can be changed. When an appropriate initial error gain is given, the AGC circuit 12 starts at zero gain, and the PLO region can be shortened.

The multipliers G0 and G1 selected by the selection circuit 163 are:
For example, when the amplitude decrease due to a defect in the reproduced waveform increases, the possibility that a reproduced data after the defect causes a data error due to the amplitude decrease is increased. For this reason, by reducing the multiplier applied to the multiplier 152 at the time of the reproduction data from the FIFO 6, data reproduction after the defect can be reliably performed.

The selection circuit 164 changes the target amplitude. When the amplitude is reduced due to a defect in the reproduced waveform, the target amplitude is reduced from the normal setting to reproduce the data, thereby improving the data reproduction performance other than the defect. , But the data reproduction capability can be improved against a decrease in the amplitude of the defective portion. Therefore, when reproducing data from the FIFO 6, by selecting and reproducing the target amplitude by the selection circuit 164, it is possible to enhance the entire data reproducing capability.

Next, an embodiment of the generation of the switching detection condition using the above-mentioned ITR circuit 11 and AGC circuit 12 is shown in FIG. In the figure, 16
5 is a selection circuit, 166 is a comparator, 167 is a delay circuit, and 168 is a judgment circuit. The selection circuit 165 includes a phase error signal and a complementary frequency error, which are internal signals of the ITR circuit 11, and the AGC circuit 12
One of the amplitude errors, which is an internal signal, is selected by a condition selection signal and output to the comparator 166 as an error signal.
The comparator 166 compares the selected error signal with a predetermined threshold value, and outputs “1” when the error signal is equal to or larger than the threshold value, and outputs “0” otherwise. The delay circuit 167 is a comparator 166
Is stored for each sample. The determination circuit 168 determines the time lapse of the error signal from the output of the delay circuit 167,
Assert the switching condition. For example, when the phase error or the amplitude error equal to or larger than the threshold value continues, it is considered that the phase synchronization or the amplitude synchronization has occurred, and the determination circuit 168 determines that “1” of the output of the delay circuit 167 is continuous. Detect and activate the switching condition. If the complementary frequency error differs by more than the threshold value, the determination circuit 168 determines that the frequency synchronization has been lost, and similarly sets the switching condition to active. The switching conditions described above are notified to the microcomputer 55 via the register 20, for example.

Next, an ML circuit capable of changing the data decoding performance
One embodiment of 13 is shown in FIG. 12 and described. In the figure, 170 is PRML
A decoding circuit, 171 indicates an EPRML decoding circuit, 172 indicates a comparator, and 173 indicates a selection circuit. In the normal state, the sel signal is “0”, and the selection circuit 173 outputs the decoding result of the PRML decoding circuit 170. At this time, the comparator 172 compares a metric value indicating a decision margin of the PRML decoding circuit 170 with a known threshold,
When the metric value becomes equal to or less than the threshold value, the switching condition is asserted, and the microcomputer 55 is notified that the data determination margin has decreased, for example. As a result, the microcomputer 55
The signal is set to "1" and decoded by the EPRML decoding circuit 171 using the reproduction data from the FIFO 6, and the result is output via the selection circuit 173. The selection circuit 173 outputs the decoding result of the EPRML decoding circuit 171. With such a configuration, the PRML decoding circuit 170
If it is determined that data playback on the
By using the EPRML decoding circuit 171 that can decode even an S / N signal at a desired error rate, data decoding performance can be improved.

Another embodiment of FIG. 13 in which the data decoding performance can be changed more complicatedly will be described with reference to the ML circuit 13. In the figure, 175 and 176 are branch metric generation circuits, 18
1 is a selection circuit, 182 is an ACS circuit, 183 is a path memory, and 184 is a comparator. Branch metric generation circuit 175
The branch metric generation circuit 176 includes a delay circuit 177, a multiplier 178, an adder 179, and a branch metric generation circuit 180.
Is different in that it has the characteristic of response 1, for example, EEPROMR (1,2,1), and the branch metric generation circuit 176 has the characteristic of response 2, for example, MEEPRML (2,2,1). The selection circuit 181 selects the output of the branch metric generation circuit having a different response, and outputs it to the ACS circuit 182. The ACS circuit 182 adds and subtracts paths based on branch metrics.
The comparison and selection are performed, and the selection information of the likely path is output to the path memory 183. The path memory 183 determines the likelihood of the path in time series and outputs the most likely decoding result. On the other hand, the comparator 184 compares the metric value, which is the margin at the time of addition and comparison of the paths of the ACS circuit 182, with a known threshold value. For example, the microcomputer 55 is notified that the judgment margin has decreased. This result is described above.
Similarly to the ML circuit, the microcomputer 55 sets the sel signal to "1" and
The setting is made to perform data decoding using the reproduced data from O6, and the selection circuit 181 outputs the branch metric of the branch metric generation circuit 176 to the ACS circuit 182. Even with the configuration described above, maximum likelihood decoding circuits having different data decoding performances can be realized.

In this embodiment, different responses are selected. However, even if the response of the branch metric generation circuit 176 is k times (k: rational number) the response of the branch metric generation circuit 175, the same processing is performed. A maximum likelihood decoding circuit can be configured.

Next, an embodiment of another switching condition generating circuit in the maximum likelihood decoding circuit will be described with reference to FIG. In the figure, 185 is a delay circuit, 186 is an autocorrelation operation circuit, and 187 is a comparison circuit. The delay circuit 185 stores a signal obtained by delaying the input signal of the ML circuit 13, and converts the input signal at time n to x
(n), the input signal to the autocorrelation operation circuit 186 is the input x (n) and the outputs x (n−1),..., x (n−4) of the delay circuit 185.
Becomes The autocorrelation operation circuit 186 calculates the following autocorrelation function and determines the characteristics of the reproduced signal. However, it is assumed that the DC component of the input signal has been removed.

[0049]

A (-j) = {Σ (x (n) * x (nj)) / x (n) * x (n)} / N n = 0 to N-1, j = 0 to 4 ... The autocorrelation function shows the correlation between the output reproduction waveform of the equalizer 10 and the noise, and if this characteristic is significantly different from the known one, the reproduction performance of the ML circuit 13 is significantly deteriorated. . Therefore, the comparison circuit 187 compares a (-j) obtained from the above autocorrelation function with a known autocorrelation function, and determines whether the error is equal to or greater than a threshold. The result is output to the microcomputer 55 as a switching condition. With such a configuration, it is also possible to configure a switching condition generation circuit.

Next, an embodiment of the SYNC detector 14 whose detection conditions can be switched will be described with reference to FIG. Here, it is assumed that the Sync code is composed of two SyncA and SyncB. Reference numeral 190 denotes a SyncA detector, 191 denotes a SyncB detector, 192 denotes a sync detector, 193 denotes a selection circuit, and 194 denotes a logical sum. The detection condition 1 is a condition in which both SyncA and SyncB are detected as a sync detection condition. Detection condition 2 is Sync
The case where either A or SyncB is detected is set as a sync detection condition. Normally, the selection circuit 193
Gives the detection condition 1 to the sink detector 192,
2 asserts the Sync detection output only when both the Sync codes are detected by the SyncA detection circuit 190 and the SyncB detection circuit 191. At this time, if neither of the sync codes is detected, the OR circuit 194 asserts the switching condition as sync not detected and notifies the microcomputer 55. As a result,
The sel signal is set so as to select the detection condition 2, and the sync detector 192 asserts a sync detection output when either the sync A detection circuit 190 or the sync B detection circuit 191 detects sync detection. As described above, the SYNC detector 14 capable of switching the sync detection condition can be configured.

Next, an embodiment of the decoder 15 for generating the switching condition will be described with reference to FIG. In the figure, 195 is a decoder, 1
96 is an encoder, 197 is a comparator, 198 is an RLL detector, and 199 is a logical sum. The encoder 196 is the same as the encoder 63 described above, and the reference numerals are divided for convenience of description. As described above, in the data recording operation, for example, 8-bit byte data is converted one-to-one into 9-bit recording data by the encoder 63 and recorded on the disk 54. On the other hand, in the data reproducing operation, for example, a 9-bit bit string is converted into 8-bit byte data by the decoder 195 from the data decoded bit string. Here, the decoding process includes an inverse conversion process of forcibly converting an unallocated bit sequence into certain byte data, in addition to an inverse conversion process of converting the bit sequence corresponding to the one-to-one correspondence and a byte sequence into byte data. If there is no error at the time of data demodulation, the decoder 195 correctly converts the input bit string (for example, a 9-bit bit string) into byte data given by the inverse conversion of the encoder 63. Therefore,
The bit sequence obtained by modulating the byte data demodulated by the decoder 195 again by the encoder 196 is the same as the input bit sequence. On the other hand, if there is an error during data demodulation, the decoder 195 forcibly converts the input bit string into appropriate byte data because a bit string different from the bit string converted by the encoder 63 is input. The bit string obtained by modulating the converted byte data by the encoder 196 again does not coincide with the input bit string. Therefore, an error at the time of data decoding can be detected by comparing the above input bit string with the bit string output from the encoder 196. The comparator 197 compares these bit strings, and outputs the occurrence of a data decoding error via the OR circuit 199 as a switching condition.

On the other hand, the RLL detector 198 determines whether or not the continuous length (0 run length) of “0” of the input data string of the decoder 15 is equal to or larger than a predetermined value. As the recording data output from the subtractor 113, a code whose 0 run length is limited in advance, for example, a code that does not generate a continuous “0” of 7 bits or more is used. Therefore, if there is no error at the time of reproduction, the input data string of the decoder 15 is also 0.
Run length should be limited. RLL detector 1
Reference numeral 98 asserts the switching condition via the OR circuit 199 when the 0 run length is equal to or greater than the predetermined value. Thus, the configuration of the decoder 15 that generates the switching condition is possible.

Next, an embodiment of the ECC generation / correction circuit 57 capable of changing the error correction capability will be described with reference to FIG. In the figure,
200 and 201 are ECC correction circuits, 202 is a selection circuit, and 203 is an error detection circuit. ECC correction circuit 200, ECC correction circuit 2
01 is an ECC circuit having a different number of error-correctable bytes. Assume that In the normal state, the sel signal is “0”, and the selection circuit 202 outputs a correction result of the ECC correction circuit 200 having a low ECC correction capability. The error detection circuit 203 is a circuit that detects that there is an error that cannot be corrected by the ECC correction circuit 200,
When such a condition occurs, the microcomputer 55 is notified as a switching condition. When the switching condition is asserted, the sel signal is set to "1" and the ECC correction circuit with high error correction capability
The correction result of 201 is output. As described above, the ECC correction circuits having different error correction capabilities are provided, and the error correction capabilities can be changed by switching these.

The characteristics of the characteristic are controlled by the As correction circuit 8, the DC correction circuit 9, the equalizer 10, the ITR circuit 11, the AGC circuit 12, the ML circuit 13, the SYNC detector 14, the decoder 15, and the ECC generation / correction circuit 57 described above. Different circuit configurations are realized. As a result, the first object of the present invention can be achieved by applying these circuit blocks to the above-described FIG. Specifically, data reproduction is performed based on a reproduction signal stored in the FIFO due to a data error. At this time, the magnetic recording / reproducing apparatus does not need to immediately reproduce the reproduction signal on the magnetic recording medium 54. Therefore,
In the case of a reproduced signal that can be read out by changing the circuit constant, data is reproduced without causing a rotation wait, and a high-speed data access is achieved.

Further, the activation of the data reproduction operation by the reproduction signal stored in the FIFO 6 is started by the ECC generation and correction circuit 57 in FIG.
However, the same control method can be used when a TA is detected by the TA detection circuit 17 or according to the switching condition in each of the above-described constituent blocks. Further, by analyzing the state of occurrence of these switching conditions, it is possible to determine an optimum portion where the circuit characteristics are changed. For example, when the TA detection circuit 17 detects a TA, it is needless to say that changing the characteristics of the DC correction circuit 9 is more appropriate than changing the frequency characteristics of the equalizer 10.

In carrying out the data reproducing operation using the FIFO 6 described above, a processing method as shown in FIG. 18 can be considered. In the figure, (a) indicates that when a data error is detected,
Reproduction processing of one entire sector, which is a unit of data processing, is performed from the start position of the sector, and (b) is processing of reproduction processing of an area where a data error has occurred from reproduction data immediately before and after that. Further, (c) stores the reproduction data of only the area where the data error has occurred in the FIFO 6, and subsequently reproduces the data of only that area. The operation will be described with reference to the configuration of FIG. Here, the condition for detecting the occurrence of a data error, that is, the switching condition, is a TA detection circuit.
The case where 17 detects a TA in a sector will be described.

First, FIG. 18A will be described. The time of the operation 1 is a normal read operation, and indicates a data string input to the FIFO 6. The reproduced signal of the recording / reproducing head 53 is sampled by the AD4, and the sampled data is sent to the FIFO 6 at the same time as the data decoding circuit after the As correction circuit 8.
The FIFO 6 stores sampling data from the beginning of the sector. When a TA detection signal is generated at the timing shown in this figure during data reproduction, the contents of the register 20 are set at the rising edge of the TA detection signal, and the TA occurrence is stored. The microcomputer 55 reads the contents of the register 20 after one sector reproducing operation is completed by the notification from the controller 51, and detects that a TA has occurred in the currently processed sector. When a TA occurs, a data reproducing operation is performed using the data in the FIFO 6 at the time of the operation 2. The microcomputer 55 performs the data reproduction operation using the reproduction signal stored in the FIFO 6, so that the sel signal is set to '1' through the register 20.
Set to. As a result, as described above, for example, the equalizer 10
Are switched from coefficient group 1 to coefficient group 2, and their frequency characteristics are changed. Controller 51 is
The read gate is asserted to perform data processing using the reproduced data in the FIFO6.

At the time of the operation 2, the FIFO 6 outputs the stored reproduction signal from the beginning, that is, from the beginning of the sector.
The data is decoded by the circuits after the As correction circuit 8. The ECC generation / correction circuit 57 performs error detection / correction on the decoded data while discarding the previously decoded data and storing the data again in the RAM 56. The subsequent processing is as described above. In such a processing method, it is necessary to reprocess data of one sector after an error occurs at the time of the operation 2 and the processing time increases, but the processing method of the controller 51 is simplified.

Next, the processing method (b) will be described. F
The IFO 6, as shown at the time of the operation 1, stores the sampling data after the head of the sector as in (a). Register 20
Records the position and pulse width of the TA detection signal after the read gate is asserted. Such a circuit is realized by a general combination of counters, not shown, and counts a bit clock or a byte clock as a reference for data transfer after read gate assertion, and counts when a TA detection signal is generated. The error data range can be easily obtained from the value. When the read operation is completed at the time of the operation 1, the microcomputer 55 checks the contents of the register 20 and detects that a TA has occurred.

Thereafter, the microcomputer 55 sets the sel signal to '1'. Further, the microcomputer 55 sets the reproduction data output start position of the FIFO 6 in the FIFO 6 via the register 20, based on the TA detection signal generation position recorded in the register 20.
In this case, the start position to be set in FIFO6 is ITR circuit 11, AG
In consideration of the synchronization time of the C circuit 12 or the decoding processing delay time of the ML circuit 13, it is set slightly before the TA detection signal generation position. Further, the output position of the FIFO 6 is determined from the storage position of the sampling data corresponding to the byte separation position with reference to the byte synchronization position of the SYNC detector 14. After the output start position of the FIFO 6 is set, the controller 51 executes the read operation again at the time of the operation 2 and decodes only the sampling data in the area where the TA has occurred in the circuits after the As correction circuit 8. . The controller 51 replaces only the previous byte data corresponding to the TA signal generation position and the length with the reproduced data and stores it in the RAM 56. The playback data of operation 1 in which part of the byte data has been replaced with the playback data of operation 2 is 1
The sector data is composed, and again, the data of one sector is E
The CC generation / correction circuit 57 detects / corrects a data error. The following is the operation described above. According to this processing method,
Although the data processing method of the FIFO 6, the controller 51, and the like becomes complicated, at the time of the operation 2, since only the data at the TA occurrence position is decoded, the processing time can be reduced as compared with the method (A).

Next, the processing method (c) will be described. The reproduced signal from the recording / reproducing head 53 is stored in the RAM 56 via the controller 51 after the data is decoded by the reproducing circuit 60. At this time, the FIFO 6 stores sampling data from a time shortly before the TA detection signal is asserted until the TA detection signal is negated. Register 20 uses method (b)
Similarly, the start position and length of the TA detection signal are stored. Here, the data recording length before the TA detection signal is asserted depends on the method
As in (b), the synchronization time of the ITR circuit 11 and the AGC circuit 12, SYNC
It is determined from the byte break position of the detector 14. Microcomputer
55 detects the occurrence of TA from the result of the register 20, and requests the controller 51 to execute the read operation again. The controller 51 asserts the read gate and the As correction circuit 8
The subsequent data decoding circuit processes only the data stored in the FIFO 6 at the time of the operation 2, that is, only the sampling data at the time when the TA detection signal is active. As in the method (b), the controller 51 replaces only the processed data with a part of the data reproduced at the time of the operation 1, and stores the data in the RAM 56. The ECC generation and correction circuit 57 stores the 1
Data error detection / correction is performed based on the sector data. Subsequent operations are the same as those described above. This processing method can decode data only at the TA occurrence position in the same processing time as the method (b). Furthermore, the amount of data stored in the FIFO 6 can be reduced to about the TA generation length, as compared with the methods (a) and (b), and the circuit scale can be reduced.

The first object of the present invention can be achieved by the signal processing circuit and the processing procedure of FIG. 1 described above.

Next, one procedure of the coefficient learning method of the equalizer 10 using FIG. 1 will be described below. The coefficient learning method of the equalizer 10 in the present embodiment has conventionally performed coefficient learning while regenerating a plurality of sectors many times.On the other hand, coefficient learning using sampling data stored in the FIFO 6 is performed. Features. Specifically, the controller 51 asserts the read gate to reproduce one sector on the track. When the read gate is asserted, the reproduced signal of the recording / reproducing head 53 is signal-processed by the above-described analog circuit, and then converted into sampling data by the AD4.
While the sampling data is stored in the FIFO 6, data decoding processing is performed by the circuits after the As correction circuit 8. At this time, the coefficient learning circuit 18 obtains a coefficient update amount of the coefficient learning circuit 18 and updates the coefficient based on an error between digital data output from the ITR circuit 11 and an internal equalization target. . When the reproduction operation of one sector is completed, the FIFO 6 stops storing the sampling data, and the coefficient learning circuit 18 once ends the coefficient update. Next, the microcomputer 55
The sel signal is changed via 20 and the output of the FIFO 6 is connected to the input of the As correction circuit 8. Thereafter, the controller 51 asserts the read gate. The FIFO 6 stores data after the sampling data stored in a specific position as an As correction circuit 8.
Output to The coefficient learning circuit 18 restarts the coefficient update operation using the previous coefficient as an initial value. Further, when the processing up to the sampling data at the specific position stored in the FIFO 6 is processed, the controller 51 negates the read gate, and the coefficient learning circuit 18 once ends the coefficient updating operation. Following this, controller 51 reasserts the read gate,
Thereafter, the above-described coefficient learning operation is performed. After the coefficient learning operation using the sampling data of the FIFO 6 is performed a specified number of times, the reproducing operation from the recording / reproducing head 53 is executed again, and then the coefficient learning operation using the sampling data of the FIFO 6 is performed. By repeating such an operation, the equalizer 10
Are determined by the coefficient learning circuit 18. According to the present embodiment, the coefficient learning time is shortened by performing the coefficient learning operation using the sampling data stored in the FIFO 6 instead of reading the reproduction signal of the conventional sector a plurality of times and performing the coefficient learning. It becomes possible.

Next, a procedure for searching for a defective area of the magnetic recording medium 54 in the magnetic recording / reproducing apparatus of FIG. 1 and for registering the defective area will be described. In a general magnetic recording / reproducing apparatus, a method of determining a defective area on the magnetic recording medium 54 as a defective area by reproducing a plurality of sectors while changing a circuit constant of a signal processing circuit to determine a sector having a low read margin. Has been adopted. Therefore, it is necessary to keep reading the same sector for the number of times the circuit constant is changed. In this embodiment, for example,
As in the coefficient learning method described above, the reproduction signal of a specific sector is stored as sampling data in the FIFO 6, and reproduces the sampling data of the FIFO 6 while changing circuit constants after the As correction circuit 8. Specifically, the controller 51 asserts the read gate to reproduce one sector on the track. When the read gate is asserted, the reproduced signal of the recording / reproducing head 53 is signal-processed by the above-described analog circuit, and then converted into sampling data by the AD4. Sampling data is FIFO
While being stored in 6, the data decoding process is performed by the circuits after the As correction circuit 8. When the reproduction operation of one sector is completed, for example, the presence or absence of a data error is determined by the ECC generation and correction circuit 5.
Detected by 7. Next, the RAM 56 changes the sel signal via the register 20, and as a result, the output of the FIFO 6 is
Entered in 8. The microcomputer 55 changes the characteristics of the signal processing circuits after the As correction circuit 8, and requests the controller 51 to start the data reproduction operation by changing the target amplitude of the AGC circuit 12, for example. When the controller 51 asserts the read gate again, the data is decoded using the sampling data of the FIFO 6 with different characteristics after the As correction circuit 8.
The above procedure is repeated, and based on the obtained data decoding result, the microcomputer 55 analyzes the data error distribution in the sector, and obtains information on the position and length of the defective area of the magnetic recording medium 54. Based on this, it is possible to register a defective area. By such a processing procedure, it is not necessary to reproduce the sector every time the number of times of changing the circuit constant, and it is possible to search for the defective area by at least one reproduction operation, thereby shortening the search time for the defective area. it can.

Next, a configuration example of another signal processing circuit in which the position of the FIFO 6 is changed will be described with reference to FIG. Figure 2 shows the FIFO
The position of 6 is changed to the output of the equalizer 10, and in the figure, the same components as those in FIG. 1 are denoted by the same reference numerals. The adin input signal is an analog signal obtained by processing the reproduction signal from the recording / reproduction head 53 by the above-described circuit. The AD4 samples the adin input signal with a sampling clock that is asynchronous with the input signal generated by the read synthesizer 5, and outputs it to the As correction circuit 8 as sampling data. As correction circuit
8. The DC correction circuit 9 and the equalizer 10 realize the above-mentioned functions, and a signal from which the intersymbol interference of the input signal is removed is obtained at the output of the equalizer 10. The obtained digital signal is
Input to the selection circuit 7 and FIFO 6 at the same time. The FIFO 6 stores the sampling data of the sector to be processed from the beginning. At the time of normal data reproduction, the sel signal of the register 20 is set to, for example, “0”, and the selection circuit 7 is controlled so that the output of the equalizer 10 is input to the ITR circuit 11. The ITR circuit 11 processes complementary data whose frequency and phase are synchronized by digital operation based on the digital signal of the equalizer 10, and the AGC circuit 12 controls the signal amplitude to be constant. The obtained signal is subjected to maximum likelihood decoding in the ML circuit 13,
The signal is output to the SYNC detector 14 as an mlout signal.

On the other hand, when an error is detected by the ECC generation / correction circuit 57 or the like and the read operation is started again, the sel signal is set to, for example, “1” by the microcomputer 55 via the register 20. As a result, the sampling data stored in the FIFO 6 is input to the ITR circuit 11, and the ITR circuit 11, the AGC
At least one of the characteristics of the circuit 12 and the ML circuit 13 is changed by the above-described configuration. The sampling data stored in the FIFO 6 is stored in the ITR circuits 11 and A having different characteristics.
After being processed by the GC circuit 12 and the ML circuit 13, S
Output to YNC detector 14. According to this embodiment, the same processing as that of FIG. 1 is realized, and the first object of the present invention can be achieved.

Further, it can be understood from FIG. 3 that the same processing as in FIG. 1 can be performed regardless of the position of the FIFO 6. FIG. 3 shows one embodiment of the present invention.
Reference numerals 3, 24, and 25 denote 2to1 selection circuits, and 26 denotes a 6to1 selection circuit. The same functions as those in FIG. 1 are denoted by the same reference numerals. Selection circuits 7, 21, 22, 23, 24, and 25 are input to the inputs of each signal processing circuit, As correction circuit 8, DC correction circuit 9, equalizer 10, ITR circuit 11, AGC circuit 12, and ML circuit 13. Provided, and FIF
A selection circuit 26 is provided at the input of O6. Each selection circuit is controlled by an independent selection signal.In normal read operation, the output of AD4
8, DC correction circuit 9, equalizer 10, ITR circuit 11, AGC circuit 12, ML
It is processed in series by the circuit 13. The selection circuit 26 selects one of the outputs of the signal processing circuits, and the FIFO 6 stores the selected digital signal. On the other hand, at the time of retry, the selection circuits 7, 21, 22, 23, 24, 25 connected to the output of the signal processing circuit selected by the selection circuit 26
Only one of them is controlled to select the output of FIFO6. For example, in the normal read operation, the output of the equalizer 10 selected by the selection circuit 26 is controlled so that only the selection circuit 23 inputs the output of the FIFO 6 to the ITR circuit 11 at the time of retry. Needless to say, in this example, the same data reproduction operation as in FIG. 2 is realized. Similarly, when changing only the characteristics of the ML circuit 13 at the time of retry, in a normal read operation, the selection circuit 26 stores the output of the AGC circuit 12 in the FIFO 6,
At the time of retry, only the selection circuit 25 selects the output of the FIFO 6.

According to the embodiment as described above with reference to FIGS. 2 and 3, it is possible to switch the processing operation range of the circuit for each factor causing a data error. For example, empirically, if it is known that the phase synchronization malfunctions due to the distortion of the reproduction signal of the recording / reproducing head 53, and as a result that data errors frequently occur, the sampling data of the FIFO 6 is retried after the ITR circuit 11 It is only necessary to operate and process only the data decoding circuit of
There is no need to operate such. Therefore, unnecessary power consumption can be suppressed by narrowing down the parts to be operated at the time of retry.

Here, an embodiment of a circuit configuration for reducing the circuit scale of the FIFO 6 will be described with reference to FIG. In this embodiment,
Arithmetic circuits are provided before and after the FIFO 6 to reduce the number of bits stored in the FIFO 6. In the figure, 210 is a data determination circuit, 211 is an adder, 212 and 214 are delay circuits, 213 is a sequencer, and 215 is 4 shows a subtractor. X which is the input of the FIFO circuit
(n) is signed two's complement digital data. For example, the correlation of (1,0, -1) in Partial Response Class-4 is obtained from the channel characteristics used in the magnetic recording and reproducing apparatus. Have. This is because when '1' occurs at time n in the input signal, there is no correlation at time (n + 1), and at time (n + 2),
This indicates that "0" or "-1" is generated from a combination of signal sequences. Using the correlation of this data, FIFO
Reduce the number of bits stored in 6. The data judgment circuit 210
x (n) data judgment, x (n)> 0.5 when '1', x (n) <-0.5
And outputs it to the sequencer 213 as '-1' and the rest as '0'. The sequencer 213 detects this data sequence based on the determination result of the data determination circuit 210 because the signal in the PLO area at the start of the sector is a continuous pattern of (1,1, -1,1), and
Output md signal. At this timing, as shown in FIG. 20 (a), after the read gate is asserted, (1,1, -1,-
1) is detected and the wcmd signal is output at the next time. Delay circuit
212 is cleared by assertion of wcmd signal,
The output y (n) of the adder 211 is delayed by two clocks so that the adder 211
Output to After the wcmd signal is asserted, y (n-2) becomes '0' for two clocks. Adder 211 has inputs x (n) and y (n-2)
And outputs the output yn to FIFO6. Thereafter, when such an operation is repeated, the output y (n) of the adder 211 becomes as shown in FIG.
And a signal sequence with no sign. The operation of writing data to the FIFO 6 is performed after the assertion of the wcmd signal. Therefore, the number of bits of data stored in FIFO6 is, for example, when the number of bits of input x (n) is 6 bits, y
(n) has 5 bits, and can be reduced by 1 bit.

On the other hand, when reading data from FIFO 6,
It must be the same data b (n) as the original x (n),
b (n) is the sequencer 213 and FIFO6 digital data a (n)
And the output a (n−2) of the delay circuit 214. Upon receiving the read gate signal, the sequencer 213 generates an rcmd signal and clears the delay circuit 214. Subtractor 215 is FIFO
The read data a (n) of No. 6 is subtracted from the output a (n−2) of the delay circuit 214 and output as data b (n). This calculation example is shown in FIG.
It is shown in (b). After the rcmd signal is asserted, a (n−2) becomes “0” for two clock periods. The output a (n) of FIFO6 is shown in FIG.
Is the same as y (n), and by subtracting a (n−2) from this signal, it becomes like b (n). Sought in this way
Comparing b (n) with FIG. 20 (a) shows that the same numerical value is obtained.

The above operation is represented by the following arithmetic expression.

[0072]

[Equation 5] y (n) = x (n) + y (n−2) Equation 5 b (n) = a (n) −a (n−2) y (n) = a (n), Since y (n) -y (n-2) = x (n), b (n) = x (n) + y (n-2) -x (n-2) -y (n-4 ) = x (n) -x (n-2) + x (n-2) =
x (n) As can be understood from the above equations, even if the above circuit is added, b (n) and x (n) are equal, and the circuit scale is reduced by reducing the number of bits of FIFO6. , It is possible to output delayed sampling data.

In the signal processing circuit according to the above-described embodiment, the conventional circuit is switched and used by a circuit such as the selection circuit 7 at the time of retry. However, in such a configuration, when continuous sectors are continuously processed as in a magnetic disk device, the processing is interrupted by a retry operation. For example, when decoding data in consecutive one and two sectors, if an error occurs in one sector, instead of decoding data in the second sector, F
Since the data of the first sector is decoded using the same signal processing circuit by using the output of the IFO6, the data decoding of the second sector needs to be interrupted. Therefore, the data decoding of the second sector is performed after the rotation wait, and the access time is reduced. FIG. 4 shows an embodiment of a signal processing circuit for avoiding this, in which 30 is an As correction circuit, 31 is a DC correction circuit, 32 is an equalizer, 33 is ITR, and 34 is AG
C and 35 indicate ML, and the corresponding As correction circuits
8, DC correction circuit 9, equalizer 10, ITR circuit 11, AGC circuit 12, ML
Although the characteristics are different from those of the circuit 13, the basic configuration is the same.
36, 37, and 38 have the same functions as the SYNC detector 14, the decoder 15, and the descrambler 16, respectively, but have been given different reference numerals for explanation. These operations will be described by taking as an example a case where data of one sector and two sectors are continuously processed. Here, it is assumed that the data storage capacity of the FIFO 6 is large enough to store the sampling data of two sectors. In a normal operation, first, the data of the first sector is input to the AD4, and the digital data of the AD4 is output to the descrambler 16 via the As correction circuit 8, and is stored in the FIFO 6 at the same time. The controller 51 causes the ECC generation / correction circuit 57 to detect an error while storing the reproduction data of the first sector output by the descrambler 16 in the RAM 56.
Here, when a data error is detected by the ECC generation and correction circuit 57, the sampling data of the subsequent second sector is processed by a signal processing circuit after the As correction circuit 8 and output to the descrambler 16 as reproduction data. 1
Following the data of the sector, it is stored in FIFO6. on the other hand,
The previously stored sampling data of the first sector of the FIFO 6 is decoded by a signal processing circuit after the As correction circuit 30 and output to the descrambler 38. The operation of each of the signal processing circuits is the same as that described above except for the characteristics, and a description thereof will be omitted. Controller 51 is
The second sector data output from the descrambler 16 and the first sector data output to the descrambler 38 are stored in separate areas on the RAM 56. ECC generation correction circuit
After detecting an error in the data of the second sector, the 57 performs error detection based on the data of the first sector stored in the RAM 56. If an error is also detected in the data of the second sector, the sampling data of the second sector is stored in the FIFO 6. After the read operation of the second sector is completed, the data is reproduced again by the signal processing circuit after the As correction circuit 30 using the sampling data of the FIFO6.

As described above, by providing a signal processing circuit for separately processing a sector in which a data error is detected, a data reproducing apparatus in which the access time is not reduced for up to one sector error is configured. Further, it goes without saying that by providing three signal processing circuits in parallel, up to two sector errors can be dealt with.

As described above, according to this embodiment, even if a data error occurs, normal data processing is not hindered.
Since the signal processing of the sector in which the data error has been detected can be performed in parallel, the access time does not decrease.

In this embodiment, the signal processing circuits are provided in parallel. However, the same processing can be realized by the configuration shown in FIG. FIG. 5 shows one embodiment of a configuration in which data reproduction at the time of retry is processed by software.
The same functions as those in 1 are denoted by the same reference numerals. For the sake of explanation, it is assumed that the presence or absence of a data error is determined by the ECC generation and correction circuit 57 detecting a data error. The reproduced signal from the recording / reproducing head 53 is fed to the AD4 via the signal processing circuit described above.
Input as a signal. AD4 samples the adin signal input asynchronously with the input signal frequency by the sampling clock generated by the read synthesizer 5,
The data is output to the FIFO 6 and the As correction circuit 8 as sampling data. Since the data demodulation processing after the As correction circuit 8 is the same as that described above, the description is omitted. The reproduction data obtained by the descrambler 16 is temporarily stored in the RAM 56 via the controller 51, and a data error is detected by the ECC generation / correction circuit 57. As a result, when a data error occurs, the ECC generation and correction circuit 57
The data is corrected using the contents of the above and the syndrome information obtained together with the data error detection. When an error out of the error correction range occurs, the controller 51
Request the 55 to perform data decryption processing using the data in FIFO6. The microcomputer 55 reproduces data according to a processing procedure as shown in FIG. 21, for example, and stores the obtained data in the RAM 56. The ECC generation and correction circuit 57 includes a microcomputer 55
Based on the data sent from, data error detection and error correction after processing of all data is completed again. Here, the software processing procedure of the microcomputer 55 will be described with reference to FIG. The sampling data from the head of the sector is stored in the FIFO 6, and the microcomputer 55 reads out each one of them and performs processing. In step 1, the data in the FIFO 6 is read, and the data decoding process in step 2 is performed. The data decoding process is performed by the following process. Step 100 corrects the vertical asymmetry of the sampling data, and step 101 removes the DC component of the waveform by a filter. Step 102 performs equalization processing to remove intersymbol interference of waveforms, step 103 performs waveform complementing processing for complementing synchronized waveforms from asynchronously sampled waveforms, and step 104 performs amplitude adjustment. Step 105 performs maximum likelihood decoding processing using the finally obtained data. After performing such processing, step 3 detects a specific pattern (Sync) for byte synchronization, and repeats the above processing until Sync is detected. After the Sync is detected, in step 4, the sampled data from the FIFO 6 is read, and in step 5, data decoding is performed. Based on the obtained data, decoding is performed in step 6, and descrambling is performed in step 7. In step 8, the reproduced byte data is stored in the RAM 56 via the controller 51. In step 9, it is determined whether the data in the FIFO 6 has been processed to the end, and the processing from step 4 is executed until the processing is completed. Data demodulation is processed by such a procedure.
This is the same as the data processing performed by the software after the As correction circuit 30 in FIG. Therefore, when performing the retry reproduction operation by software, the constants for determining the data reproduction characteristics of steps 100, 101, 102, 103, 104, and 105 are determined by the As correction circuit 8, the DC correction circuit 9,
Data can be decoded by changing the constant in the equalizer 10, the ITR circuit 11, the AGC circuit 12, and the ML circuit 13. In particular, in the data decoding method performed by software described in this embodiment, since each constant can be easily changed, data decoding can be performed by a plurality of combinations of different constants.
Therefore, according to the present embodiment, the probability that data can be read increases.

Next, an embodiment of a signal processing circuit combining a memory and a signal processing circuit will be described.

FIG. 22 shows an example of a signal processing circuit in which a memory and a phase locked loop are combined. In FIG.
AM and 221 denote RAM control circuits, and the same components as those in FIG. 1 are denoted by the same reference numerals. In this embodiment, the memory and the IT
It shows a method of improving the phase synchronization accuracy by repeatedly performing phase synchronization by combining with an R circuit. The sampling data sampled by AD4 is A
After being processed by the s correction circuit 8, the DC correction circuit 9, and the signal processing circuit of the equalizer 10, they are input to the RAM 220. ITR circuit 11, RAM22
0, a specific configuration example of the RAM control circuit 221 is shown in FIG. In the figure, 230, 231, 232 and 233 indicate address generators. The eqout signal output from the equalizer 10 is input to the RAM 234 of the RAM 220 divided into two parts,
Stored at the address indicated by 230. The written data is temporarily read from the address of the address generator 231 and processed by the ITR circuit 11 into digital data that is phase-synchronized. At this time, an address indicated by the address generator 231 is also used as a work area when processing is performed by the ITR circuit 11. The data generated by the ITR circuit 11 again
It is stored in the RAM 235 at the address indicated by the address generator 232, read again by the address generator 233, and
Output to gcin signal. The agcin signal is output to the AGC circuit 12 and subjected to amplitude adjustment, and then data is decoded by the ML circuit 13.
With the above configuration, the address generator 230 and the address generator 233
Functions as an address counter for configuring a normal FIFO, and the circuit for improving the phase synchronization accuracy described in the present embodiment is realized by the address generators 231, 232 and the ITR circuit 11.

FIG. 24 shows a specific address generation procedure.
The address management of the RAM 220 is wr_a, rd_a, which manages the address of the RAM 234, and wr_, which manages the address of the RAM 235.
b, rd_b. Further, the data structure of the RAM 234 is roughly divided into a variable raw_data for storing an eqout signal and a work area variable of the ITR circuit 11, and the work area variable of the ITR circuit 11 is, for example, a digital filter 127 shown in FIG.
The variable filter_inte which is the storage variable (contents of the delay circuit 142)
rnal, a variable nco_internal which is a storage variable of the integrator 128 (contents of the delay circuit 146). Step 1 performs initialization processing of each address pointer, and is executed only when the read gate is asserted. Among them, N_offset indicates a processing delay time for performing the repetitive processing. step2 to step6 are eq
Processed each time an out signal is input. step2 is eqou
The t signal is written to the raw_data variable in the area indicated by wr_a, and step 3 outputs the data indicated by rd_a to adc_in. In step 4, the processing is controlled by the fixed_start variable. If the fixed_start variable is true, the addresses of rd_a and wr_b are subtracted by N_delay and the position is returned. Furthermore, raw_dat between rd_a and rd_a + N_area
Clear a and fix nco_internal with fixed_nco. In these processes, for example, when the TA signal is asserted, preparations are made to perform data complementation again by the ITR based on the data stored in the RAM 234. In step 5, using the address indicated by rd_a as a work area, the complementary data is stored in the RAM 235 at the address indicated by wr_b. step4,5
As a result, the input data to the ITR circuit 11 between rd_a and rd_a + N_area becomes '0', so the phase control is held, and as a result, the output of the ITR circuit 11 has a fixed period (sampling interval indicated by fixed_nco). It becomes sampled complementary data. In step 6, each address pointer is updated. step7
Is equivalent to a program describing the processing procedure of the ITR circuit 11, and the function phase_error ()
Generate a phase error filter_in from _data and use the function filter ()
Is the obtained phase error and the internal variable filter_interna
Using l, a complementary frequency error nco_in is calculated. Function n
co () calculates the sample phase phase_offset using the obtained complementary frequency error nco_in and the internal variable nco_internal.
Is output. The function interpolater () outputs complementary data from the sample phase indicated by phase_offset and the input data. By controlling the address pointer in this way,
Even if the phase tracking of the ITR becomes impossible, the data processing can be started again to the time when the phase tracking becomes impossible.

For example, a specific processing method when a waveform as shown in FIG. 25 is input to the signal processing circuit will be described. The input waveform has a data defect in a part of data due to a missing recording medium. The phase synchronization response due to this input signal is stable until the defect waveform at time A is input, but is unstable due to the defect waveform from time A to time B, as shown in condition (a). Become. Since the input waveform becomes normal after time B, the phase synchronization response follows this, and the phase synchronization stabilizes at time C. In this case, a data error occurs from time A to time C. At time B, for example, when a data error is detected at time C by the data error detection method using the above-described phase error, the input data is
To return to (0), the variable N_delay is set to τ (0). Further, an N_area corresponding to τ (0) to τ (1) is set, and the phase synchronization during this period is held. After τ (1), the phase synchronization is restarted, but the defect waveform is still input to the phase synchronization circuit, so that the phase synchronization response becomes unstable. However, the data error length becomes shorter because the phase error at time B is smaller than the condition (a) (from time A to time T (1)). Further, the condition (c) is such that the phase synchronization hold time is extended from τ (1) to τ (2) to suppress the amount of phase fluctuation at time B. N_area which is the hold period of the above phase synchronization
Check for errors while changing the length, and finally
In the case of (d), the phase synchronization in the period from time A to time B is held, and the phase fluctuation after time B is minimized. Thus, data reproduction with stable phase synchronization can be performed.

In this embodiment, data is reproduced while changing the hold period of phase synchronization. However, by providing a special phase synchronization circuit as shown in FIG. 26, more efficient data reproduction can be performed. become. FIG. 26 shows an embodiment of the configuration, in which 222 indicates a Reverce ITR (abbreviated as RITR), in the reverse order to the input signal to the ITR circuit 11, that is, the sample time goes in the reverse direction. Complementary data is generated for such an input signal based on the sampling data. Other symbols indicate the same functions as in FIG. The sampling data sampled by the AD 4 is processed by the As correction circuit 8, the DC correction circuit 9, and the equalizer 10 as described above, and then input to the RAM 220. The specific configuration of the RAM 220 is, as shown in FIG.
Are provided with address generators 240 and 241 for managing the input and output. Address generator 230, address generator 2
The addresses generated by the address generator 31, the address generator 232, and the address generator 233 are count-up operations as described above, but the address generator 240 and the address generator 241 perform count-down operations. Thus, if the digital data input to the ITR circuit 11 is x (0), x (1), x (2), x (3), ..., the digital data input to the RITR 222 .., X (3), x (2), x (1), x (0) are input in a direction opposite to the data order stored in the generator 230. Also, ITR
Assuming that the output of the circuit 11 is y (0), y (1), y (2), y (3), ..., RI
The output of TR222 calculates complementary data by using signals that are temporally reversed, and becomes, y (3), y (2), y (1), y (0). Specific R
The configuration of the ITR 222 will be described later. The data complemented by the ITR circuit 11 is first input to the address indicated by the address generator 232. On the other hand, the complementary data output from the RITR 222 is only output when there is a data error.
The complementary data previously written by the address generator 232 is rewritten to the address indicated by 1 in the reverse direction. Eventually RA
The complementary data remaining in M235 is read out by the address generator 233 and output as an agcin signal.

The specific configuration of the RITR 222 is shown in FIG. The basic configuration is the same as that of FIG.
In that it has a selection circuit 237 in which the complement coefficient is inverted. Since the signal input to the RITR 222 is sampling data inverted in time, the complement coefficient selection circuit 237 of the waveform complement filter 125 is temporally symmetric with respect to the complement coefficient 1-133 shown in FIG. . Using the data complemented by the waveform complementing filter 125, the phase error detector 126 calculates the phase error by calculation. Here, since the output of the waveform complement filter 125 is inverted in time, the phase error detector 126
Performs the opposite detection to the phase detection of FIG. That is, it is determined that the phase advance is a phase delay. But 127, integrator 128
Since the phase direction of the sample phase obtained by the above process is reversed, the overall phase control direction does not change at all. With the above configuration, it is possible to generate complementary data based on sampling data inverted in time. In the present embodiment, the configuration in which the selection circuit 237 is replaced with the complementary coefficient 1-133 in FIG. 9 has been described. Because of the symmetry, the coefficient given by the selection circuit 237 may be the same as the complement coefficient 1-133 or the like. Therefore, RITR222
Can be realized by the same circuit as the ITR circuit 11.

The operation of reproducing data of one sector using the RITR 222 will be described with reference to FIG. It is assumed that the same input waveform as that of FIG. 25 has been input. The phase synchronization response of the ITR circuit 11 becomes unstable from time A to time C as shown in the condition (a) due to this input signal. As a result, a data error occurs from time A to time C. When the end of the data error is detected at time C by other means (not shown), the RITR 222 calculates the complementary data from time C to time A using the phase synchronization information at time C as shown in condition B. Time A until the phase is determined to be unstable
Is stored in the RAM 235. At this time,
The RITR 222 from C to time B has a stable phase synchronization response since the input signal itself has no defect, and outputs correct complementary data. However, from time B to time A, the phase synchronization response becomes unstable due to the defective waveform of the input waveform. Finally, the RAM 235 stores the time C before the time A generated by the ITR circuit 11 and the time C
The subsequent complementary data and the complementary data from time A to time C generated by the RITR 222 are stored, and the address generator 233
Outputs the stored complementary data as an agcin signal. In the obtained agcin signal, among the complementary data of the RITR 222, the complementary data from time B to time C is correctly calculated. For this reason, a data error due to unstable phase synchronization is reduced to a period from time A to time B.
Further, the signal processing circuit using the RITR 222 does not require a plurality of repetitive processes as described above, so that data can be decoded in a short time.

In this embodiment, the case where the phase synchronization response becomes stable at the time C has been described. However, there are cases where the phase synchronization becomes inoperable due to a defective waveform. In contrast, the figure
The data decoding performance can be improved by using a sector format such as 31. In the sector format shown in FIG. 31, the PLO, SYNC, DAT
A and ECC are processed in this order. On the other hand, when a data error is detected, SYNC and POST areas are added after the ECC to enable a reproducing operation from the back of the sector. POST
It is sufficient that the region has a length equal to or less than that of the PLO region, and has a length that enables phase synchronization in the POST region. For playback from the back of the sector, POST, SYNC, EC
The C, DATA, SYNC, and PLO are read, and the RITR 222 generates all complementary data from the back of the sector. Eventually RAM235
Is output from the beginning of the sector, and the subsequent circuits perform data decoding processing. FIG. 32 shows a specific data processing method. The phase synchronization response when data decoding is performed from the head of the sector becomes unstable due to the defective waveform after time D, and the phase synchronization becomes unstable and inoperable even after passing the defective waveform. Next, when the data decoding process proceeds until time F and a data error is detected, RI
The TR 222 starts generating complementary data using the sample data stored in the RAM 234. The RITR 222 first performs phase synchronization in the POST area, and then stores, in the RAM 235, complementary data that passes from time E to time D. When the phase synchronization response becomes unstable again at time D, the writing of the complementary data to the RAM 235 is stopped here, and the address generator 233 stops writing the complementary data.
Is read from the beginning of the sector and the subsequent data decoding process is performed as an agcin signal. By the above processing, even when the phase synchronization malfunctions for some reason and the subsequent phase synchronization becomes impossible, the retry processing can be performed without reading the reproduced signal again.

In the present embodiment, the POST area length has been described as being equal to or less than the PLO area length. However, for example, the same processing can be realized even if the POST area length is equal to or less than 1 byte. Specifically, the phase synchronization operation is performed while changing the initial value of the sample phase of the RITR 222, for example, the initial value of the delay circuit 146, in the same manner as the means for changing the initial value of the ITR circuit 11 to realize the zero phase start. By doing so, the zero phase start of the RITR 222 is also possible.
As a result, it is possible to reduce an area for performing phase synchronization.

Although the present embodiment does not refer to the scrambler 62, the general scrambler 62 changes the data, ECC, and POST areas after the sync byte to random data during recording. The POST area in the data format described in this embodiment needs to be the same data as the PLO area, and the scrambler 62 needs to handle the data and the ECC area excluding the POST area as random data. Therefore, the scrambler 62 is controlled by a scramble control signal as shown in FIG. 31 for discriminating between the data, the ECC area and the POST area. Such a control signal is an indispensable signal for controlling the ECC generation and correction circuit 57 and the RAM 56 inside the controller 51, and is easily output to the recording circuit 58.

The same processing can be realized by the configuration shown in FIG. 27 in addition to the above-described embodiment. In the figure, 223 indicates the same RAM as the RAM 220, and 224 and 225 indicate the same functions as the AGC circuit 12 and the ML circuit 13, which are added for convenience of explanation. The sampling data output from the AD 4 is processed by a signal processing circuit from the As correction circuit 8 to the equalizer 10. The output of the equalizer 10 is input to the RAM 220 and the RAM 223, and based on complementary data processed by the RAM 220, the ITR circuit 11, and the RAM control circuit 221 from the beginning of the sector to the rear, the AGC circuit 12, the ML
The circuit 13 performs a data decoding process. On the other hand, the RAM 223 and the RAM control circuit 221 once store the data from the start data of the sector to the end data of the sector, and then generate the complementary data in the direction from the end data of the sector to the start data by the RITR 222. The obtained complementary data is stored in the RAM control circuit 221, RAM 223.
The AGC 224 and the ML circuit 225 perform data decoding processing in the direction from the head data to the last data of the sector. M
The two decoded data obtained from the L circuit 13 and the ML circuit 225 are:
It is equivalent to the outputs of the ML circuits 13 and 35 as shown in FIG. 4, and functions as a signal processing circuit by being connected to, for example, the inputs of the SYNC detectors 14 and 36 in FIG.

FIG. 33 shows another embodiment of a signal processing circuit using a memory. In the figure, reference numeral 245 denotes a phase locked loop (VFO), and a detailed description of the configuration will be omitted. Reference numeral 246 denotes a sampling clock selection circuit. The read gate signal is asserted during a head read operation using a reproduction signal from the recording / reproduction head 53 and during an internal retry read operation using sampling data of the FIFO 6. The sel signal that determines the sampling clock of AD4 is, for example, “0” only in the above-described head read operation, and is “1” in other states. The sampling clock of the AD4 is a clock output from the VFO 245 when sel = "0" (that is, during a head read operation). On the other hand, when the head read operation is completed and the internal retry read operation is performed, cksel = "1", and the sampling clock of AD4 is the clock output from the read synthesizer 5. Hereinafter, the operation of each unit in the head read operation will be described.

The AD 4 samples an analog signal obtained by processing the above-mentioned reproduced signal by a sampling clock generated by the VFO 245. The VFO 245 performs phase synchronization using one of the digital data obtained by processing the sampling data output from the AD 4 by the As correction circuit 8 and the DC correction circuit 9 and the digital data obtained by equalizing the processed data by the equalizer 10. . VFO2
45 performs a phase pull-in operation using the output of the DC correction circuit 9 in the PLO area at the head of the sector, and then performs a phase tracking operation in the PLO area and thereafter using the output of the equalizer 10.

The equalizer 10 includes a TA detection circuit 17, a selection circuit 7,
The TA detection circuit 17 is connected to the IFO 6 and controls the VGA 2 to keep the signal amplitude constant. The FIFO 6 sequentially stores digital data output from the equalizer 10 from the head of the sector.
The selection circuit 7 outputs the output of the equalizer 10 to ML because the sel signal is “0”.
Input to the circuit 13. The output of the equalizer 10 is decoded by the ML circuit 13, and data is processed by blocks after the SYNC detector 14. These are the same as the above-mentioned processing, and the description is omitted.

When the head read operation is completed, for example, ECC
When the generation and correction circuit 57 determines that there is an error in the sector data, the sel signal is set to "1" and the internal retry read operation is performed. This operation decodes data based on digital data stored in the FIFO 6, and does not perform processing using sampling data output from the AD 4. For this reason, it is not necessary to input the AD4 sampling clock, but generally the circuit blocks after the As correction circuit 8 often operate using the AD4 sampling clock. The configuration is switched. In internal retry read operation, FIFO6, M
The circuit block of the L circuit 13 operates with the clock of the read synthesizer 5. The output of the FIFO 6 is decoded from the beginning of the processing sector, for example, by changing the characteristics of the ML circuit 13, and is subjected to data processing by circuits after the SYNC detector 14.
If the data error is eliminated by this operation, the data reproduction operation can be performed without causing a rotation wait.

In this embodiment, if the phase synchronization response of the VFO 245 is stable over all the sectors, the probability of a data error is reduced even if the data is demodulated with the digital data of the FIFO 6,
This probability is extremely high if the VFO 245 becomes unstable and inoperable. Therefore, one embodiment for avoiding a data error in the retry operation even when the VFO 245 becomes inoperable is shown in FIG. 34 and described. In the figure, the same components as those described above are all given the same reference numerals. In the above-described head read operation, the sel signal is set to “0”, the sampling clock of AD4 is controlled to output the clock of VFO 245, and the selection circuit 7 is controlled to output the output of the equalizer 10 to the ML circuit 13. The same data decoding is performed by the circuit block.

Here, the head read operation is completed, and VFO2
As a result of the inability to phase-lock 45, for example,
When the ECC generation and correction circuit 57 determines that there is an error in the sector data, the sel signal is set to "1" and the internal retry read operation is performed. The sampling data stored in the FIFO 6 stores digital data for which phase synchronization has been disabled. This is because the data is not correctly demodulated in the ML circuit 13 because the phase is not synchronized with the input analog signal, and the data itself is not lost. Therefore, ITR circuit 11, AGC
The circuit 12 estimates complementary data that is stable in both phase and amplitude from the sampling data stored in the FIFO 6. The complementary data is decoded again by the ML circuit 13, and the subsequent processing is performed. As a result, if the data error is eliminated, the data reproducing operation can be performed without causing a rotation wait.

Next, an embodiment of a signal processing circuit capable of reproducing a lower S / N signal will be described with reference to FIG. In the figure, 250
Indicates an averaging circuit, and other blocks are denoted by the same reference numerals as those described above. The sampling data stored in the FIFO 6 is data that stores a previous read signal of the same sector. Specifically, as shown in FIG. 36, the sampling data of the FIFO 6 is stored in a rotating magnetic recording medium 54.
Stores one sector on a track. The sampling data stored in the FIFO 6 stores, for example, digital data after the sync byte detection. Next, when the magnetic recording medium 54 makes one rotation to reproduce the same sector, the averaging circuit 250 averages the sampling data of the FIFO 6 stored in the previous read operation and the digital data currently output by the AGC circuit 12. And the data is decoded by the ML circuit 13. In the averaging, the digital data after the sync byte is detected and the digital data stored in the FIFO 6 are averaged, so that the digital data after the sync byte input to the ML circuit 13 is subjected to synchronous addition processing of the same sector. You. Therefore, the signal amplitude to be processed is kept as it is, only the noise superimposed thereon is attenuated by a square root of 1/2, and as a result, the signal S / N input to the ML circuit 13 is improved by 3 dB, and the lower S / N signals can be reproduced.

Next, an embodiment of a TA removing circuit will be described with reference to FIG. Also in this embodiment, the processing is executed by the above-described two-sector data read operation. In the figure,
Reference numerals 255 and 257 denote subtracters, and reference numeral 256 denotes a DA converter. Other functions described above are denoted by the same reference numerals. The subtractor 255 subtracts the output of the DC correction circuit 9 from the output of the As correction circuit 8, and outputs a DC component of the output of the As correction circuit 8, for example, a TA baseline signal. When a TA is detected in the first sector read operation, the TA baseline signal is stored in the FIFO 6 via the subtractor 255. Next, in the second sector read operation, the FI
The TA baseline signal, which is digital data stored in FO6, is converted to an analog signal by the DA converter 256, and is subtracted by the subtractor 257.
Performs subtraction of the analog signal. Since the position of TA is generally fixed, the output of the subtracter 257 is subtracted from the TA waveform stored in the previous read operation, so that a waveform without baseline fluctuation due to TA is input to AD4. You. As a result, there is no baseline fluctuation due to TA, and a data decoding error due to a malfunction of the signal processing circuit after the equalizer 10 does not occur.

FIG. 39 shows a recording circuit 58 and a reproducing circuit 60 according to the present invention.
FIG. 1 shows an example of a chip layout of a read channel LSI in which is encapsulated in one LSI. The chip layout of a read channel LSI using the present invention is characterized in that it includes a memory circuit area, which is a main component of the FIFO, in a size that can be recognized. The conventional read channel LSI chip layout consists of only an analog circuit area where chip layout is performed by hand wiring and a digital circuit area where automatic layout is performed by a calculator or the like. Can be easily determined from the chip photograph.

In order to realize a compact layout, the memory constituting the FIFO of the present invention is regularly arranged separately from a digital circuit area composed of random circuits. In addition, since the number of input / output bits and the capacity of the memory is specialized for its use, the presence of the memory area of the present invention can be easily confirmed from the chip photograph in addition to the conventional analog circuit area and digital circuit area. You.

The specific storage capacity of the memory circuit is about 550 bytes in the sector which is the basis of the recording / reproducing operation of the disk.
The storage capacity is about 700 samples. Furthermore, since an AD circuit used in a disk drive generally outputs an analog signal as a 6-bit digital signal,
The number of input bits of the memory connected to this also becomes an integer multiple of 6 bits. The number of input / output bits of the memory is determined from the sampling frequency of the AD circuit and the operating speed limit of the memory. When the transfer speed is about 400 Mbit / s, it is generally 24 bits that are parallelized in four. Since a high-speed memory is also required, a static memory configuration is generally used.

FIG. 40 shows a controller 51, a RAM 56, an ECC generation / correction circuit 57 in addition to the recording circuit 58 and the reproduction circuit 60 described above.
This shows an example of a chip layout of a data recording / reproducing LSI in which the microcomputer 55 is sealed in one LSI. Since the controller 51, the ECC generation / correction circuit 57, and a part of the microcomputer 55 are random circuits, automatic layout is performed in the same manner as the above-described digital circuit. On the other hand, the RAM 56 is the same memory as the FIFO 6, but has a large difference in capacity and structure.
The FIFO 6 has a high-speed static memory configuration of about several kilobytes, and the RAM 56 has a dynamic memory configuration of about several megabytes. Therefore, the presence of the memory area of the present invention can be easily confirmed even from a chip photograph of a data recording / reproducing LSI having a large circuit scale.

[0100]

According to the present invention, in the signal processing circuit using the sampling data stored in the storage means, and in the magnetic recording / reproducing apparatus for executing the same, the recovery processing time of the data error caused by the defect of the recording medium or the like is obtained. Can be shortened. As a specific example, the time required for one rotation of the recording medium is 10 ms (corresponding to a rotation speed of 6000 rpm), the number of data recovery times is 10, and the processing time per sector is 250 μs.
Then, in the conventional data recovery process, about 100 ms (10
ms x 10 times), but according to the present invention, about 2.5 ms (250
μs x 10 times). Thus, the recovery time can be significantly reduced.

Similarly, the present invention can be applied to a case where repetitive processing is performed using a reproduction signal from a magnetic recording medium. For example, the present invention can be applied to optimization of circuit parameters of a signal processing circuit and the like and registration of a defect position of a recording medium of a magnetic recording / reproducing apparatus, and it is possible to reduce the processing time for these.

Further, according to the present invention, it is possible to minimize a burst-like data error length caused by a defect of a recording medium or the like. Generally, a burst error longer than the length of the defective medium occurs due to a change in the phase synchronization response caused by a defect in the recording medium. According to the present invention, there is an effect that the occurrence of a burst error longer than the length of the defective medium is suppressed by correcting the phase synchronization response fluctuation after the storage medium passes through the defect.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a magnetic recording / reproducing apparatus using a signal processing circuit of the present invention.

FIG. 2 is a configuration diagram of another signal processing circuit of the present invention.

FIG. 3 is a configuration diagram of another signal processing circuit of the present invention.

FIG. 4 is a configuration diagram of another signal processing circuit of the present invention.

FIG. 5 is a configuration diagram of another signal processing circuit of the present invention.

FIG. 6 is a configuration diagram of an embodiment of an As correction circuit according to the present invention.

FIG. 7 is a configuration diagram of an embodiment of a DC correction circuit according to the present invention.

FIG. 8 is a configuration diagram of an embodiment of an equalization circuit according to the present invention.

FIG. 9 is a configuration diagram of an embodiment of a complementary phase locked loop circuit according to the present invention.

FIG. 10 is a configuration diagram of an embodiment of an amplitude adjustment circuit according to the present invention.

FIG. 11 is a configuration diagram of an embodiment of a switching condition generation circuit according to the present invention.

FIG. 12 is a configuration diagram of an embodiment of a maximum likelihood decoding circuit according to the present invention.

FIG. 13 is another configuration diagram of the maximum likelihood decoding circuit according to the present invention.

FIG. 14 is a configuration diagram of an embodiment of a switching condition generation circuit in the maximum likelihood decoding circuit according to the present invention.

FIG. 15 is a configuration diagram of an embodiment of a sync detection circuit according to the present invention.

FIG. 16 is a configuration diagram of an embodiment of a decoder circuit according to the present invention.

FIG. 17 is a configuration diagram of an embodiment of an error detection and correction circuit according to the present invention.

FIG. 18 is a diagram showing an example of a data processing method using a FIFO.

FIG. 19 is a configuration diagram of an embodiment of a FIFO circuit according to the present invention.

FIG. 20 illustrates an example of input / output signals of a FIFO circuit.

FIG. 21 is a diagram showing a software processing procedure in the present invention.

FIG. 22 is a configuration diagram of an embodiment of a signal processing circuit using a RAM according to the present invention.

FIG. 23 is a configuration diagram of an embodiment of a RAM peripheral circuit according to the present invention.

FIG. 24 is a diagram showing an example of a RAM control procedure.

FIG. 25 is a diagram showing an operation example of the signal processing circuit in FIG. 22;

FIG. 26 is another configuration diagram of a signal processing circuit using a RAM according to the present invention.

FIG. 27 is another configuration diagram of a signal processing circuit using a RAM according to the present invention.

FIG. 28 is another configuration diagram of a RAM peripheral circuit according to the present invention.

FIG. 29 is a configuration diagram of an embodiment of an inverse complementary phase locked loop circuit according to the present invention.

FIG. 30 is a diagram showing an operation example of an inverse complementary phase locked loop circuit.

FIG. 31 is a diagram showing a data format having a reverse complementary phase synchronization circuit.

FIG. 32 is a diagram showing another operation example of the reverse complementary phase locked loop circuit.

FIG. 33 is a configuration diagram of another signal processing circuit of the present invention.

FIG. 34 is a configuration diagram of another signal processing circuit of the present invention.

FIG. 35 is a configuration diagram of another signal processing circuit of the present invention.

FIG. 36 is an operation conceptual diagram of the signal processing circuit in FIG. 35;

FIG. 37 is a configuration diagram of a TA removal circuit according to an embodiment of the present invention.

FIG. 38 is a configuration diagram of a general magnetic recording / reproducing apparatus.

FIG. 39 is a configuration diagram of an example of a chip layout of a read channel LSI according to the present invention.

FIG. 40 is a configuration diagram of an example of a chip layout of a data recording / reproducing LSI according to the present invention.

[Explanation of symbols]

1 ... HPF, 2 ... variable gain amplifier, 4 ... AD converter, 5 ... lead synthesizer, 6 ... FIFO, 7 ... selection circuit, 8 ... As correction circuit, 9 ... DC correction circuit, 10 ... Equalization circuit, 11 ... Complementary phase synchronization circuit, 12: amplitude correction circuit, 13: maximum likelihood decoding circuit, 14: SYNC detection circuit, 15: decoder, 16 ...
Descrambler, 18… coefficient learning circuit, 55… microcomputer, 57… ECC generation and correction circuit, 51… controller, 56
… RAM, 58… Recording circuit, 60… Reproduction circuit, 2
21: RAM control circuit, 222: reverse complementary phase synchronization circuit.

Claims (22)

[Claims] 1. A storage means for storing a reproduction signal from a storage medium or the like, a selection means for switching between the reproduction signal and an output signal of the storage means, a signal processing means for processing an output signal of the selection means, Decoding means for decoding the output of the signal processing means. 2. The signal processing apparatus according to claim 1, wherein an input / output characteristic of said signal processing means is changeable. 3. An apparatus according to claim 1, wherein said signal processing means or said decoding means includes an error occurrence factor analysis means for causing a data error, and a selection condition of said selection means is determined based on a result of said error occurrence factor analysis means. The signal processing device according to claim 1. 4. A procedure 1 for processing the reproduced signal by the signal processing means and the decoding means, and a procedure 2 for repeatedly processing the output of the storage means at least once by the signal processing means and the decoding means. 2. The signal processing device according to claim 1, wherein a procedure 2 is performed following the procedure 1. 5. A procedure 1 for processing the reproduced signal by the signal processing means and the decoding means, and a procedure for repeatedly processing a part of the output of the storage means at least once by the signal processing means and the decoding means. 2. The signal processing apparatus according to claim 1, wherein step (2) is provided, and step (2) is performed after step (1). 6. A procedure 1 in which a part of the reproduction signal is stored in the storage means, and the reproduction signal is processed by the signal processing means and the decoding means, and a partial reproduction signal stored in the storage means is provided. 2. The signal processing apparatus according to claim 1, further comprising: a procedure 2 for repeating the processing by the signal processing means and the decoding means at least once, and executing the procedure 2 after the procedure 1. 7. A data recording / reproducing apparatus which performs data recovery processing for decoding data in an area where a reproduced signal is abnormal by the signal processing apparatus according to claim 4, 5 or 6. . 8. A data recording / reproducing apparatus, wherein the signal processing apparatus according to claim 4, performs a defect registration process for searching for an area where a reproduced signal is abnormal. 9. The storage means comprises: first signal processing means for converting an N-bit input signal into an M-bit signal; data storage means for storing an output of the first signal processing means; 2. The method according to claim 1, further comprising a second signal processing unit that converts an M-bit output signal of the storage unit into an N-bit signal, wherein the number M of input bits of the data storage unit is smaller than N. Signal processing device. 10. A data storage medium for storing data, recording means for recording data on the data storage medium, and reproduction means for reproducing data from the data storage medium, wherein the reproduction means is as set forth in claim 1. A data recording / reproducing device, comprising: a signal processing device. 11. A data recording / reproducing apparatus according to claim 10, wherein said recording means and said reproducing means are mounted on one component. 12. A storage means for storing a reproduction signal from a storage medium or the like, a signal processing means for processing the reproduction signal stored in the storage means, and a decoding means for data decoding an output of the signal processing means. A signal processing device comprising: 13. A storage means for storing a reproduction signal from a storage medium or the like, an operation means for calculating the reproduction signal and an output signal of the storage means, and a signal processing means for processing an output signal of the operation means. And a decoding means for decoding the output of the signal processing means. 14. A data conversion means for converting M-bit data into N-bit data according to a predetermined data conversion condition, a recording / reproduction means for recording / reproducing data, and an N-bit data from the recording / reproduction means. In a signal processing apparatus provided with a data reverse conversion means for converting data to the data conversion means and converting the data to M-bit data, the N-bit data from the recording and reproduction means, the data from the recording and reproduction means A conversion unit that converts the data by the data inverse conversion unit and compares an output of the data inverse conversion unit with an N-bit output of the data conversion unit obtained as a result of inputting the output to the data conversion unit; A signal processing device characterized by the above-mentioned. 15. A processing unit for storing external data includes a first phase synchronization area for performing bit synchronization, a first byte synchronization area for performing byte synchronization, a data area for storing the external data, and a data area for storing the external data. A data format comprising a data confirmation area for detecting / correcting a data error of data, a second byte area for performing byte synchronization, and a second phase synchronization area for performing bit synchronization. 16. An external data recorded in the data format according to claim 15, wherein the external data is stored in the first phase synchronization area,
The first byte synchronization area, the data area, a first data processing means for performing data processing in the order of the data confirmation area, the second phase synchronization area, the second byte synchronization area, the data confirmation area, And a second data processing means for performing data processing in the order of the data area. 17. A data recording / reproducing apparatus for storing external data, wherein a phase synchronization area for performing bit synchronization, a byte synchronization area for performing byte synchronization, a data area for storing data, and data error detection / correction. The external data is stored in units of a data confirmation area to be processed and a processing correction area for correcting data processing delay, and a scramble process of adding a predetermined specific data sequence to the data sequence of the data region and the data confirmation region is performed. A data recording / reproducing apparatus, wherein a scrambling process is not performed in the phase synchronization area, the byte synchronization area, and the processing correction area. 18. A sequence of sampled input values.
First time-axis conversion means for converting X (n) to X (m), and a synchronous sample for outputting a sample output sequence Y (m) having a predetermined phase from the output of the first time-axis conversion means Conversion means;
A second time axis converting means for converting the output value series Y (m) of the synchronous sample converting means into Y (n) is provided, and time n is 0, 1, 2, 3 ... N
Then, the time m is N,... 3,2,1,0. 19. An amplitude adjusting means for controlling a signal amplitude to be constant, a filter means for removing a signal outside the signal band of the amplitude adjusting means, a sampling means for sampling a signal of the filter means, In a signal processing apparatus provided with a clock generation unit for generating a sampling clock, a correction unit for removing distortion of an output of the sampling unit, and a decoding unit for decoding data from an output of the correction unit, the sampling unit and the correction unit Storage means for storing an output signal of any of the means, and sample data generation means for generating sampling data of a different phase from the output signal of the storage means, a part of the signal stored in the storage means, Alternatively, sampling data is generated from the whole by the sample data generating means, and the generated Signal processing device and performs data decoded from pulling data by the data decoding means. 20. The sampling data is changed by an initial value of the sample data generating means, and the sampling data is generated by changing the initial value of the sample data generating means one or more times. 20. The signal processing device according to claim 19, wherein: 21. A first time axis conversion means for converting the sampled data input value series X (n) into X (m), and a sample time data conversion means for converting the output of the first time axis conversion means. Synchronous sample conversion means for outputting a sample output sequence Y (m) having a predetermined phase, and second time axis conversion means for converting the output value sequence Y (m) of the synchronous sample conversion means into Y (n) If time n is 0,1,2,3 ... N, time m is
20. The signal processing apparatus according to claim 19, wherein sampling data of N,... 3,2,1,0 is generated, and the sampling data is decoded by the data decoding unit. 22. A data recording apparatus comprising: a storage medium for storing data in a plurality of divided data storage areas; recording means for recording data on the storage medium; and reproduction means for reproducing data from the storage medium. In the reproducing apparatus, the reproducing means reproduces the data in the storage area of the data again during the reproduction of the data in the data storage area.