JP2754398B2 - Automatic equalization control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding an automatic equalization control method for automatically equalizing a reproduction signal by a magnetic head or the like, the purpose of which is to quickly pull in an optimum equalization state, equalization smaller than an optimum equalization constant First and second equalizers for equalizing a reproduced signal controlled by a constant and a large equalization constant, respectively.
The first and second demodulators for demodulating the equalized output signals of the first and second equalizers and outputting pseudo-demodulated data; and the first and second equalizers A third demodulation circuit that demodulates the sum of the equalized output signals of the circuit to obtain positive demodulation data, positive demodulation data of the third demodulation circuit, and pseudo demodulation data of the first and second demodulation circuits. And a first and a second data comparing circuit for comparing the first and second data comparing circuits, wherein the first and the second data comparing circuits make the error rates of the pseudo demodulated data substantially equal to each other. Is configured to control the equalization constant of.

[Industrial applications]

The present invention relates to an automatic equalization control method for automatically equalizing a reproduction signal from a magnetic head or the like.

In a magnetic storage device, an equalizing circuit is indispensable in order to improve the resolution of a reproduced signal by a magnetic head with the increase in storage density, and the characteristics of a magnetic head, a storage medium, etc. Since there is a variation or a difference in characteristics of the reproduced signal due to a position on the storage medium, equalization corresponding to the difference in the characteristics is required. Therefore, there is a demand for automatically controlling an optimal equalization state.

[Conventional technology]

In one magnetic disk device of the magnetic storage device,
It is generally stored as an RLL (Run Length Limited) code, and this code is called an RLL (2,7) code in which the interval of magnetic reversal is set to a minimum of 2 code cells and a maximum of 7 code cells. ing. When reproducing data stored on a magnetic disk with such codes, the reproduced signal read by the magnetic head has different amplitude and waveform depending on the radial position of the magnetic disk, and the reproduced signal of the inner peripheral portion of the magnetic disk is Has a waveform that causes intersymbol interference as compared with the reproduced signal in the outer peripheral portion.

Therefore, equalization is performed by using an automatic gain amplifier, an equalizing circuit, or the like to equalize the amplitude of the reproduced signal and to eliminate intersymbol interference. Then, the data is reproduced by the level identification of the equalized output signal and the detection of the zero cross point.

Various configurations are already known for the equalizing circuit for equalizing the reproduction signal. For example, the equalization circuit shown in FIG. 6 includes an input resistor 61, an equalization constant circuit 62, a delay circuit 63, and an operational amplifier.
64, and the reproduction signal of the magnetic head is applied to the + terminal of the operational amplifier 64 via the delay circuit 63 and to the-terminal via the equalization constant circuit 62, respectively.

The reproduced signal input to the + terminal of the operational amplifier 64 is reflected due to high input impedance, and is input to the − terminal of the operational amplifier 64 via the delay circuit 63 and the equalization constant circuit 62. That is, through the equalizing constant circuit 62,
After the reproduction signal is input to the terminal, and twice as long as the delay time of the delay circuit 63, the reproduction signal reflected at the + terminal is input again to the-terminal via the equalization constant circuit 62. .

Accordingly, as shown in FIG. 7, when the reproduced signal input to the + terminal of the operational amplifier 64 is A and the delay time of the delay circuit 63 is τ, the waveform of the waveform shown in B is applied to the − terminal of the operational amplifier 64. A signal will be input. That is, the level of the reproduction signal A is adjusted by the equalization constant circuit 62, and the signal B becomes a signal B having a phase advanced by τ with respect to the reproduction signal A and a phase delayed by τ. Since the signals A and B having such waveforms are input to the operational amplifier 64, a portion of the reproduced signal A that causes intersymbol interference is removed, and an equalized output signal C indicated by a dotted line is obtained.

[Problems to be solved by the invention]

When demodulating a reproduction signal, it is necessary to perform equalization processing on the reproduction signal so as to reduce the error rate. For this reason, conventionally, the reproduction signal is recorded on a magnetic disk having a specific pattern, The equalization constant of the equalization constant circuit 62 is set based on the reproduced signal. Therefore, there is a disadvantage that a storage area for desired data is reduced in order to record a specific pattern for equalization processing. Further, in order to reduce the error rate, it is necessary to check a large number of data, so that the time required for determining the equalization constant becomes long.

Further, since the equalization constant is set based on the reproduced signal at the inner peripheral portion of the magnetic disk, the equalization constant may be excessively large for the generated signal at the outer peripheral portion, and the optimum constant may be obtained. There is a disadvantage that it is not easy to set the equalization constant.

SUMMARY OF THE INVENTION An object of the present invention is to quickly bring an optimal equalization state into account.

[Means for solving the problem]

The automatic equalization control method of the present invention automatically optimizes a reproduction signal from a magnetic head or the like, and will be described with reference to FIG.

First and second equalization constants controlled by an equalization constant smaller than the optimum equalization constant and a larger equalization constant to equalize the reproduced signal.
And the first and second equalizing circuits 1, 2
First and second demodulation circuits 3 and 4 for demodulating the equalized output signal of the above and outputting pseudo demodulated data, and the first and second equalizer circuits
A third demodulation circuit 5 which obtains the sum of the equalized output signals of 1 and 2 by the adder 8 and demodulates the same to obtain the positive demodulated data, the positive demodulated data of the third demodulation circuit 5, And first and second data comparison circuits 6 and 7 for comparing the pseudo demodulation data of the second and third demodulation circuits 3 and 4 with the first and second data comparison circuits 6 and 7, respectively. The equalization constants of the first and second equalization circuits 1 and 2 are controlled so that the error rates of the demodulated data become substantially equal.

[Action]

The equalized output signals of the equalizing circuit 1 having a small equalizing constant and the equalizing circuit 2 having a large equalizing constant have relatively large errors when demodulated, and the sum signal thereof has an error. It will be small. Therefore, by demodulating the sum signal by the third demodulation circuit 5, it is possible to obtain positive demodulated data having a small error.

The pseudo demodulated data of the first and second demodulation circuits 3 and 4 and the third demodulated data
The data comparison circuits 6 and 7 compare the positive demodulation data of the demodulation circuit 5 with the data, and control the equalization constants of the equalization circuits 1 and 2 based on the comparison result. Minimum in cases, and larger in smaller and larger cases. Therefore, when the error rates of the case where the equalization constant is small and the case where the equalization constant are large become almost equal, the intermediate value of those equalization constants equivalently corresponds to the optimum equalization constant, and the equalization circuit 1 , 2 are controlled by the data comparison circuits 6 and 7, so that the third demodulation circuit 5
Are equalized by the optimum equalization constant.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention.
Are first and second equalizing circuits, 13 to 15 are first to third demodulating circuits, 16 and 17 are first and second data comparing circuits, 18 is an adder, 1
9 is an AGC amplifier, 20 is a magnetic head, 21, 25 is input resistance, 22,
26 is an equalization constant circuit, 23 and 27 are delay circuits, 24 and 28 are operational amplifiers, 29, 31, and 33 are level and zero cross detection units, and 30, 32, and 34 are pulse output units.

The equalizing circuits 11 and 12 have the same configuration as that shown in FIG.
The equalization constant circuits 22 and 26 have equalization constants controlled by control signals from the data comparison circuits 16 and 17. The equalization constant of the equalization constant circuit 22 of the equalization circuit 11 is controlled to a value smaller than the optimum equalization constant, and the equalization constant of the equalization constant circuit 26 of the equalization circuit 12 is larger than the optimum equalization constant. It is controlled by the value.

The reproduced signal from the magnetic head 20 is amplified by the AGC amplifier 19 to have a constant amplitude level, and
The equalized output signal is added to the first and second demodulation circuits.
13, 14 and an adder 18. In the first to third demodulation circuits 13 to 15, the level and zero cross detection units 29, 31,
At step 33, the equalized output signal is compared with the reference level, and the zero-cross point of the equalized output signal is detected, whereby demodulated data having a predetermined pulse width is output.

Pseudo demodulated data from the first and second demodulation circuits 13 and 14,
The normal demodulation data from the third demodulation circuit 15 is compared in the data comparison circuits 16 and 17, respectively, and the equalization constant circuits 22 and 26 of the equalization circuits 11 and 12 are equalized according to the value corresponding to the error rate. Constants are controlled.

Figure 3 is a equalizing constant setting illustration, equalization constant horizontal axis, the vertical axis indicates an error rate, next ER ₀ error rate minimum at the optimal equalization constants K _0, as shown , A symmetrical error rate characteristic curve centered on this point. Therefore, the equalization constant K ₁ (<K ₀ ) and the equalization constant K ₂ (>
At the time of K ₀ ), the same error rate ER ₁ (> ER ₀ ) is obtained.
If the equalization constant K ₃ (<K ₁ ), the error rate ER
₃ (> ER ₁ ), and if the equalization constant K ₄ (> K ₁ ), the error rate is ER ₄ (<ER ₁ ).

For example, the equalization constant of the equalization constant circuit 22 of the equalization circuit 11 is
And it is controlled to the optimum equalization constants K ₀ value less than, if the equalization constant of K _3, the error rate is degraded than in ER _3, and the equalization constants K _1. In this case, control is performed so that the equalization constants of the data comparison circuit 16 to the equalization constant circuit 22 are increased. Also if equalization constant is K _4, the error rate ER ₄ becomes, but the error rate is improved compared to the case of equalizing constants K _1, the data comparison circuit 16, equalization constant circuit 22
Is controlled so as to reduce the equalization constant of.

Similarly, in the equalization constant circuit 26 of the equalization circuit 12, the data comparison circuit 17 controls the equalization constant. Then, when the equalization constants of the equalization circuits 11 and 12 are, for example, K ₁ and K ₂ and the error rates are substantially equal to ER ₁ , the equalized output signal added by the adder 18 is optimally equalized. When the signal becomes equivalent to the signal equalized by the constant K ₀ and is demodulated by the third demodulation circuit 15, the error rate becomes the minimum ER ₀ .

FIG. 4 is a main block diagram of a data comparison circuit according to an embodiment of the present invention. Reference numerals 41 and 42 denote shift registers, reference numerals 43 and 44 denote memories, reference numeral 45 denotes counters, reference numerals 46 and 47 denote exclusive OR circuits, and reference numerals 48 and 49. Is an OR circuit, 50 is a NOR circuit, TD is positive demodulation data, PD is pseudo demodulation data, and CLK is a clock signal.

The clock signal CLK is synchronized with the demodulated data. Therefore, the count content of the counter 45 indicates the number of demodulated data, and the signal a is output from the carry terminal CR according to the predetermined count content. The positive demodulation data TD demodulated by the third demodulation circuit 15 is shifted to the shift register 41 in accordance with the clock signal CLK, and the pseudo demodulation data PD demodulated by the first or second demodulation circuit 13 or 14 is
The data is shifted to the shift register 42 according to the clock signal CLK.

The memory 43 stores a specific pattern in which an error easily occurs, and the memory 44 stores a specific pattern in which an error is predicted for the specific pattern. Therefore,
When the contents of the shift register 41 match the contents of the memory 43 and the specific demodulation data TD of a specific pattern is obtained, all the output signals of the exclusive OR circuits 46 become "0" and the shift register 42 And the contents of the memory 44 coincide with each other and an error predicted in the pseudo demodulation data PD occurs, and when all the output signals of the exclusive OR circuits 47 become "0", the NOR circuit 50 Becomes "1", the signal b of "1" is added to the reset terminal R of the counter 45, and the counter 45 is reset. The output signal b of the NOR circuit 50 and the carry signal a of the counter 45 are added for controlling the equalization constants of the equalization constant circuits 22 and 26.

The memories 43 and 44 may further be provided in a large number to store a plurality of different types of patterns and simultaneously compare the contents of the shift registers 41 and 42 with the respective exclusive OR circuits. Table 1 shows an example of the contents stored in the memories 43 and 44.

When "111" is stored in the memory 43 in the data comparison circuit 16 on the series side of the equalization circuit 11 having the smaller equalization coefficient, as shown in a of Table 1, the memory 44 is stored in the memory 43. In the pseudo demodulation data PD to detect a bit missing error. Similarly, as shown in b of Table 1, when “100... 0011” is stored in the memory 43, “100.
This is to detect the peak shift of the equalized output signal.
Also, c in Table 1 is a pattern for detecting a peak shift. The memories 43 and 44 in the data comparison circuit 17 on the series side of the equalization circuit 12 having the larger equalization coefficient have d (excessive bit generation due to over-equalization), e, f ( Jitter) is stored.

FIG. 5 is a diagram for explaining the operation of controlling the equalization constant.
(B) is the carry signal a of the counter 45 of the smaller series of equalization constants and the output signal b of the NOR circuit 50. The equalization constant of the equalization constant circuit 22 is reduced by one step by the carry signal a. And the output signal b is controlled to increase by one step. (C), (d)
Are the carry signal a of the counter 45 of the larger series of equalization constants and the output signal b of the NOR circuit 50. The equalization constant of the equalization constant circuit 26 is increased by one step by the carry signal a. It is controlled so as to be reduced by one step by the output signal b.

Therefore, in the equalization circuit 11 of the series having the smaller equalization constant, the equalization constant of the equalization constant circuit 22 is controlled as shown by EQ1, and the equalization circuit of the series having the larger equalization constant is controlled. In 12, the equalization constant of the equalization constant circuit 26 is controlled as shown by EQ2. Since the signal of the sum of the equalized output signals of the first and second equalizing circuits 11 and 12 is input to the third demodulating circuit 15,
Equalizing constant for signal of the sum is as shown in EQ that approximate equivalently optimal equalization constants K _0.

The counter 45 outputs the carry signal a by counting up P clock signals CLK. When the carry signal a is output, the error rate is 1 /.
When it is smaller than P and no carry signal a is output, it indicates that the error rate is larger than 1 / P. In the long-term average, the equalization constants of the equalization constant circuits 22, 26 are controlled according to the error rate 1 / P. Will be done. This error rate 1 / P
The, for example, can be selected to be the error rate ER ₁ of FIG. 3. In this case, for example, if P = 100, the error rate ER ₁ corresponds to the case where 10 ^-2, and the error number occur. Note that the error rate ER _{0 at} the optimum equalization constant ER ₀ is usually 10 ⁻⁹ or less, and a configuration is employed in which the error rate is further reduced by using an error correction signal or the like.

In the above-described embodiment, the error pattern of the pseudo demodulation data PD is detected only when the positive demodulation data TD has a specific pattern. , It is also possible to control the equalization constant.

〔The invention's effect〕

As described above, the present invention provides a first equalizing circuit 1 controlled by a small equalizing constant with respect to an optimal equalizing constant, and a second equalizing circuit 2 controlled by a large equalizing constant. , The equalized output signal is demodulated by the first and second demodulation circuits 3 and 4 to generate pseudo demodulated data, and the sum of the equalized output signals is demodulated by the third demodulation circuit 5. Control the equalization constants of the first and second equalization circuits 1 and 2 by comparing the positive and pseudo demodulation data by the first and second data comparison circuits 6 and 7 Even if a reproduced signal of an arbitrary pattern is used, the optimal equalization constant can be equivalently set, and it is not necessary to store a specific pattern, so that the storage area can be effectively used. .

In addition, since the equalization constants of the first and second equalization circuits 1 and 2 are controlled in a region where the error rate is relatively large, it is necessary to detect the error rate in a short time and control the equalization constant. Therefore, there is an advantage that the time required for drawing into the optimal equalized state can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram for setting an equalization constant, and FIG. FIG. 5 is a block diagram of an equalization constant control operation, FIG. 6 is a block diagram of a main part of the equalization circuit, and FIG. 7 is a diagram illustrating the operation of the equalization circuit. 1, 2 are first and second equalizers, 3, 4, and 5 are first, second, and third demodulators, 6, 7 are first and second data comparators, and 8 is an adder. It is.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kiichiro Kasai 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (1)

(57) [Claims] A first and a second equalizing circuit for equalizing a reproduced signal under the control of an equalization constant smaller than an optimum equalization constant and a larger equalization constant; First and second demodulation circuits (3, 4) for demodulating an equalized output signal of a second equalization circuit (1, 2) and outputting pseudo demodulated data; and the first and second equalizations A third demodulation circuit (5) which demodulates the sum of the equalized output signals of the circuits (1, 2) to obtain positive demodulated data;
And a first and second data comparing circuit (6) for comparing the positive demodulated data of the third demodulating circuit (5) with the pseudo demodulated data of the first and second demodulating circuits (3, 4). , 7), and the first and second equalizing circuits (1, 2) are provided by the first and second data comparing circuits (6, 7) such that the error rates of the pseudo demodulated data become substantially equal. An automatic equalization control method characterized by controlling the equalization constant of (1).