JPH05210578A - Storage device - Google Patents

Abstract

PURPOSE:To reduce the size of a peripheral circuit by selecting memory elements which are as many as rows or columns in total by rows and columns from the respective rows and columns of memory elements arrayed in an NXN matrix, and connecting their input and output sides and thus constituting an internal data bus. CONSTITUTION:The storage device where the storage elements are arrayed in the NXN matrix is provided with a data bus controller 5 and a data bus switching part 4 connects an external data bus 7 and the internal data bus 3 with the output of the data bus controller 5. The memory elements 1 which are as many as the rows or columns in total are selected from the respective rows and columns row by row and column by column and data are inputted to and outputted from the internal data bus 3 where those memory elements 1 are connected. Consequently, the memory elements 1 are selected and connected so that there is no row or column conflict in an oblique direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly to a memory device in which memory elements are arranged in a matrix of N × N.

[0002]

2. Description of the Related Art Conventionally, in a memory device of this type, when a plurality of words in a row direction or a column direction can be accessed, each of the memory elements 1 selected by a chip selector 6 as shown in FIG. N × N data buses connected to each other and a 1: N ² multiplexer 8 for each of reading and writing are required, and the peripheral circuits are enormous.

[0003]

In the conventional storage device described above, when a plurality of words in the row direction or the column direction can be accessed, N × N data buses connected to each memory element and a read operation are performed. However, there is a drawback that a 1: N ² multiplexer is required for each writing and the peripheral circuit becomes huge.

[0004]

A memory device according to the present invention is a memory device in which memory elements selected by a chip selector and input / output are arranged in a matrix of N × N, and rows and columns are selected from each row and column. A memory element for summing one memory element for each row and column to input / output data to / from an internal data bus connected by selecting the number of rows or columns, and an internal data bus input / output from the memory element And a data bus switching unit controlled by a data bus controller which is connected to and is output as an external data bus.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 shows four storage elements of the storage device of the present invention.
This is an example in the case of arranging in × 4 matrix. The output of the data bus controller 5 connects the external data bus 7 and the internal data bus 3 in the data bus switching unit 4. One signal 2A of the select signal 2 from the chip selector 6 selects one memory element for each row and column from each row and column, selects the number of rows or columns, and outputs data to the connected internal data bus 3. Is input and output. Here, as a result, the corresponding memory element 1 is selected,
The rows or columns are diagonally connected so as not to conflict with each other.

FIG. 2 is a detailed diagram of the data bus switching unit 4 of FIG. When inputting / outputting data to / from the column composed of the memory elements a2, b2, c2, d2, the memory elements a2, b2, c2, d2 are selected by the chip selector 6, and the internal data bus DB1 is set by the data bus switching unit 4. It is connected to the external data bus OD0, and similarly DB2 is OD1 and DB.
3 is connected to OD2 and DB0 is connected to OD3, respectively, so that data can be input / output to / from the column. With respect to the rows, data input / output can be performed similarly to the above.

[0008]

As described above, according to the present invention, one memory element is arranged for each row and column from each row and column of memory elements arranged in N × N matrix. By selecting only the number and connecting the input and output sides to form an internal data bus, there is an effect that the peripheral circuit can be significantly downsized.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing details of a data bus switching unit 4.

FIG. 3 is a block diagram showing an example of a conventional storage device.

[Explanation of symbols]

 1 Memory Element 2 Selector Signal 3 Internal Data Bus 4 Data Bus Switching Section 5 Data Bus Controller 6 Chip Selector 7 External Data Bus 8 Multiplexer

Claims (1)

[Claims] 1. A storage device in which memory elements selected and input / output by a chip selector are arranged in a matrix of N × N, one memory element for each row and column from each row and column. And a memory element for inputting / outputting data to / from the internal data bus connected by selecting the number of rows or columns, and data output as an external data bus connected to the internal data bus input / output from the memory element. A storage device comprising a data bus switching unit controlled by a bus controller.