JPH01293796A - Digital signal exchange - Google Patents

Abstract

PURPOSE:To execute signal transmission at a high speed and to easily increase a circuit by defining an (n)-number of fist input lines as a line for input and an (m)-number of second input lines as a line for auxiliary input, selecting the (m)-number of the lines out of the (n+m)-number of the input lines and connecting the lines to an (m)-output line. CONSTITUTION:Signal inputs I1 to I256 lines are divided into sixteen and sent through buffer drivers BD1 to BD16 to input buses IB1 to IB16. The buses IB1 to IB16 transmit the input signals to a row direction 16 input of selector modules S1 to S16 and S17 to S32, etc., which are connected to the bus. Respective modules S1 S256 connect a row direction input line, which is designated by a control signal to be inputted through a control bus, to a designated output line and the column direction input line of a same column is connected to the other output line. The signal of the column direction line is outputted through the output line of the column to an external part by the switching control of these modules S1 to S256. Thus, the signal transmission can be executed at the high speed and the circuit can be easily increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a digital signal exchanger that connects a plurality of digital signal input lines to any one of a plurality of output lines.

(Prior Art) In general, a digital signal exchanger that exchanges high-speed and continuous digital signals such as image PCM signals used in broadcasting stations etc. has an input line that is connected to multiple input lines and an input line that is connected to multiple output lines. Arrange the connected output lines in a grid pattern,
It is constructed in a matrix type with switch elements arranged at cross points between each input line and output line, and by selectively switching and connecting each switch element, any input line can be connected to any output line. .

However, in the configuration described above in which the connection of each crosspoint is controlled by a switch element, the input digital signal passes through a large number of switch elements before being output from the exchanger, so as the speed of digital signals increases, Therefore, the delay when passing through the switch element cannot be ignored. In addition, an electronic switch using a semiconductor is used as the switch element, but
The signal passing characteristics of this type of switch are generally that the rise and fall delay times are not equal. For this reason, the input digital signal accumulates distortion each time it passes through a switch element, and is output with very large distortion, which may make code identification impossible.

In order to improve this, conventional methods have been considered to perform synchronization and waveform shaping using flip-flops each time the wave passes through a crosspoint switch element, but in a simple matrix configuration, the number of flip-flops required depends on the number of lines. This is not a realistic improvement measure because it requires a huge number of chips, consumes a lot of power, and is difficult to implement.

(Problems to be Solved by the Invention) As described above, in conventional digital signal exchangers, as the speed of digital signals to be transmitted increases and the number of lines increases, the delay time difference between lines increases, and distortion occurs during signal transmission. Therefore, it is no longer possible to improve the speed of digital signals and increase the number of lines.

This invention was made in consideration of the above circumstances, so that the delay time between lines is uniform, and distortion that occurs during signal transmission can be sufficiently suppressed, thereby increasing the speed of transmitted digital signals. The purpose of the present invention is to provide a digital signal exchanger that can easily increase the number of lines.

[Structure of the Invention] (Means for Solving the Problem) In order to achieve the above object, a digital signal exchanger according to the present invention selects one line from n (n is a natural number) first input lines. The first
and a second selection section that selects one line from the output line of the first selection section and one second input line and connects it to one output line. m (m is a natural number) The present invention includes a selection module having: basic selection circuits; and an input bus that commonly connects the n first input lines of each basic selection circuit to the n input lines.

When expanding the number of lines, the selection modules are arranged in rows and columns, input buses are commonly connected in each row, and m output lines are connected to the m output lines of the selection module in the next row. Connect to the 2nd input line.

The m basic selection circuits are provided with synchronization means for synchronizing the digital signals transmitted to each other's output lines. As this synchronization means, a flip-flop is interposed between the second selection section and the output line, and the flip-flops of each basic selection circuit are driven with the same clock.

The selection module is formed of an integrated circuit device.

At this time, the first selection section of the basic selection circuit is configured by combining a plurality of two-input one-output selection switch elements.

(Function) In the digital signal exchanger having the above configuration, the n first input lines are used for input lines, the m second input lines are used for preliminary input lines, and m lines of n+m input lines are selected. It is configured using a selection module that connects to the output line. This selection module has m basic selection circuits, and n first input lines of each circuit are commonly connected to n input lines by an input bus. In this basic selection circuit, the first selection section selects one line from the first input lines and connects it to one output line, and the second selection section selects one line from the first input line and connects it to one output line. One line is selected from one second input line and connected to one output line. By using such a selection module, implementation becomes easy and miniaturization can be achieved.

Further, the selection modules are arranged in rows and columns, input buses are commonly connected in each row, and m output lines are connected in each row to m second input lines of the selection module in the next row. Then, it can be expanded to nXk input input lines m×power output line switch.

If the difference in delay time of the digital signals transmitted to the output lines is a problem, provide synchronization means for synchronizing the digital signals transmitted to the output lines of the m basic selection circuits of the selection module. Bye. As this synchronization means, a flip-flop may be interposed between the second selection section and the output line, and the flip-flops of each basic selection circuit may be driven with the same clock.

According to this synchronization means, since it is only necessary to provide a flip-flop for each basic selection circuit, the number of flip-flops can be reduced compared to the conventional one, and thereby power consumption can also be reduced.

If the selection module is formed of an integrated circuit device, further miniaturization and power saving can be achieved. In this case, if the first selection part of the basic selection circuit is configured by combining a plurality of 2-input 1-output selection gate elements, it will be easier to integrate the circuit, and the number of gate passages can be made equal between each line. Therefore, delay time can be easily controlled and distortion components generated during transmission can also be suppressed.

(Example) Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the overall configuration of a 16×16 input/16×16 output digital signal exchanger according to the present invention. However, the control system is omitted here.

In FIG. 1, 81 to S2,6 are selector modules with 32 inputs and 16 outputs (hereinafter referred to as 32×16), including 16 inputs in the row direction and 16 inputs in the column direction, and are arranged in 16 rows and 16 columns on the substrate a. IB, ~IB, 6 are each 16X16
The external input terminal (not shown) of the line is divided into 16 lines, and the digital signals input to the external input terminals of the divided 16 lines are arranged in the row direction via bus drivers BD, ~BD,, etc. 16 selector modules S, ~S16
This is an internal input bus that transmits to 16 inputs in the row direction of ゜S17 to S3□, . . . +5241 to S2, 6.

CB, ~CB240 are arranged in the column direction (
) is a natural number from 1 to 15)-th selector module S,
~S16. This is an internal common bus that transmits the 16 outputs of the 16 outputs of the 1+1 selector modules S1+4 to 5I6 (, +1.) in the same column.
96 is an internal common bus that transmits the 16 outputs of the 16th selector module S arranged in the column direction to the 16 inputs in the column direction of the selector modules 82 to S16+Sl in the next column (CB 256 is the first column). . OB.

~0B16 are selector modules 8 arranged in the row direction
The 16 outputs OB, ~OB, 6 of 241~S2,6 are connected to 1 external output terminal (not shown) of 16 x 16 lines, respectively.
This is an internal output bus that transmits data to 16 external output terminals divided into 6 parts.

Although not shown here, the board a is provided with an interface for control signal input/output and a control bus that connects this interface with each selector module S, ~S2, 6, and connects the host computer and each selector module through the interface. 81 to S2, 6 are connected, thereby each selector module SI to S2, 6
The selection can be controlled by the host computer.

That is, in the digital signal exchanger with the above configuration, 1
6x16 line digital signal input I, ~ I2, 6 to 16
The signals are divided and sent to internal input buses IB, -1B16 via buffer drivers BD, -BD, 6, respectively. The internal input buses IB, ~IB, 6 respectively transmit input digital signals to the selector modules S1~S16, S17~S, 2, . ... +5241~
It is transmitted to 16 inputs in the row direction of S2 and S6.

Each selector module 81 to S2, 6 connects a row direction input line designated by a control signal input through a control bus to a designated output line, and connects a column direction input line in the same column to another output line. Connect. The digital signal transmitted to the line in the column direction by the switching control of the selector module is output to the outside via the internal output bus line of that column unless another selector is selected.

Figure 2 shows the 32x16 selector module S mentioned above, where 1 to 116 are internal input bus lines, C
3 to C16 are internal common path lines, 0 to 0.6 are internal output bus lines, and AO-A4 is a control path line. This selector module S has 16 gate arrays G shown in FIG. 3 arranged in parallel in the row direction as shown in FIG.
Input bus lines II+ to 11 in selector module S
16 connects the input ends of each gate array G, to G16 and internal input bus lines 11 to I16.

The gate array G, as shown in FIG.
, a 2×1 second gate g2 that selects one line from the output line of the first gate g1 and the internal common path line co, and each gate array 01 to
It is composed of a synchronization circuit g using a flip-flop (F/F) for matching the output timing between G16.

Furthermore, the specific configuration of the gate array G is shown in FIG. 5 and explained below.
is constructed by arranging 2×1 games go+ to g+ on a tree: eight in the first row, four in the second, two in the third, and one in the fourth. Gate of each stage go+ ~
g 08+ g 09~ g+ 2・
g+ 3 to gz and gas are control path lines A, respectively. , AH, A2.

The selection is controlled by the selection signal from A.

In other words, the input bus lines II, ~If, 6 connected to this first gate g1 are connected to the first stage gates go+~gos.
8 lines are selected, and the second stage gate g. ,~g
4 lines are selected by +□, and the third stage gate g1.
Two lines are selected by ~g14, and one line is further selected by the fourth gate gas and connected to the 2×1 second gate g2.

Here, each gate g. l−g+, is configured to select the upper line when the selection signal is “0” and select the lower line when the selection signal is “1°.As a result, the control path line A.−A, By simply setting the selection signal to (n-1)2, it is possible to select and control the input bus line I1. For example, when selecting Il, 7, the selection signal (
A3A2AIAO)2 (0110) 2 (-(7-
1) to). This relationship facilitates setting of the selection signal. Note that the second gate g2 is controlled by a selection signal from the control path line A4, and A4 is set to "1".
'', the output line of the first gate g is selected and 0
'', internal common path line C.

is selected.

The above 2X1 gate g. 1 to g+s+g2 can be realized by the logic circuit shown in FIG. In Figure 6, A, B
is a digital signal input line, C is a control signal input line,
X is a digital signal output line. This logic circuit is
−(AOC)+(B*C) is realized. That is, C
By setting C to "0", the AND gate AND selects the A side, and by setting C to "1", the AND gate A
The B side can be selected with ND2 and connected to X via the OR gate OR.

As described above, if the gate array G is configured using 2×1 gates as basic elements, the number of times the input signal passes through the gate will be equal, so synchronization will be easy, and selection control will also be possible.
This can be easily realized with a 5-bit selection signal from 0 to A4.

FIG. 7 shows the configuration of the control system of the selector module S. The control bus connected to this module S receives the 5-bit selection signals A0 to A4, the 4-bit address data AD, and the chip select signal. Command signal WRITE including signals C8 and 4.

It is composed of each line of the load command signal LOAD.

On the other hand, the control system is provided with first and second latch circuits L1°+L21+ and an AND gate g aa for each gate array G, and further provided with an address decoder ADD for specifying the gate array to be controlled. configured.

Address decoder ADD contains 4-bit address data A.
D and the pass line of the chip select signal CS are connected, and the AND gate g1. is address decoder ADD.
Channel output AD, and write command signal WRITE
path lines are connected. In addition, the first latch circuit L
11, a 5-bit pass line for selection signals A and -A4, and an AND gate g. is connected to the output line of the second latch circuit L2. is connected to the 5\bit output line of the first latch circuit L1m and the pass line of the load command signal LOAD, and its 5bit output terminal is connected to each gate array G,
connected to the control bus.

The address decoder ADD is the chip select signal C8.
It is activated by the input of 4-bit address data AD.
Input which gate array G.

is specified, and the specified gate array G,
The designation signal AD is sent to the AND gate g.

AND gate g, which inputs the designated signal AD. sends the write command signal WRITE to the first latch circuit +t. The first latch circuit L1° to which the write command signal WRITE is input takes in the selection signals A0 to A4 and holds them until the next write command signal WRITE is input. When the second latch circuit L2g inputs the load command signal LOAD, it takes in the latch output of the first latch circuit L1g, and until the next load command signal LOAD is input, the gate array G7
Send to. As a result, the first latch circuits Ll, can be freely rewritten and can hold the next selection signal for each gate array G.

With the above configuration, the selector module S can be realized, and by combining this selector module, the digital signal exchanger shown in FIG. If the signal is latched, the specified input line will be connected to the wrong output line.

That is, in the switch having the above configuration, once a certain connection state is set, the connection state is maintained for the entire time that the exchanged signal occupies the line. A common method for monitoring this connection status is to monitor each control register (latch circuit).

There is a scanning method that sequentially reads the contents held in L2°) and confirms whether normal control information is stored. However, with this method, the number of control registers that store control information increases as the scale of the switch increases, so it takes time to read all the control registers that make up the switch. In the unlikely event that an abnormality occurs, it will take time to respond. Therefore, the correct selection signal is the latch circuit I/I @+
A check mechanism is required that can immediately determine whether L2* is latched or not.

FIG. 8 shows the configuration of a check mechanism constructed to meet the above request, and this check mechanism is provided for each gate array g. In FIG. 8, the same parts as in FIG. 7 are denoted by the same reference numerals, and only the different parts will be described here.

First, in addition to the pass lines for the parity signal P, the even/odd designation signal EVEN10DD, the read command signal READ, and the read switching signal RR, the control bus includes a six-line read output bus RB and a write output bus WB (Ao-A4.
control path line of P) and parity error signal PE, ,
Add a pass line for PE2. read output bus RB,
Write output bus WB and parity error signals PE,,P
Each path line of E2 is connected to an external host computer through the interface. Note that since writing and reading are not performed at the same time, the read output bus RB
and write output bus WB may be shared.

A 6-bit register is used for the first and second latch circuits L1□L2m. The first latch circuit Lla receives the selection signal A by inputting the write command signal from the AND gate ga. - The parity signal P is held together with A4, and the held signal A. -A, , P to the second latch circuit L2, the first parity check circuit PCI, and the first read switch circuit SW. The second latch circuit L2n is connected to the first latch circuit L1 by the input of the load command signal LOAD.
．． output signal A. -A4. Hold P and hold signal A
o-A4. P is led out to the second parity check circuit PC2 and the second readout switch circuit SW2, and the selection signal A
. - Deliver only A4 to gate array g.

first and second parity check circuits pc;

Both PO2s have the same configuration, for example, as shown in FIG. In FIG. 9, gol-go.

is an exclusive OR gate (hereinafter referred to as EX-OR gate), and go is A. -A2 is supplied to go2, A, , A4 . P and EVENloDD are supplied, g
g for o3. Each output of ++goz is supplied. In addition, in FIG. 9, EX-OR gate g Of g 02
have three inputs and four inputs, respectively, which means that two-input EX-OR gates are connected in multiple stages.

The even/odd designation signal E V E N10DD determines whether the parity signal is an even parity or an odd parity, and the parity signal P is determined based on the even/odd designation signal EVEN10DD. For example, AO-A4 is '00101', even/odd designation signal E
When V E N10 DD is "1" (even number), the parity signal P becomes "0".

Output PE of 0X-OR gate gos, (or (PE
2) becomes 1'', it means that an error has been detected, and the signal is sent to the host computer via the path line (PEI, PE2).

The read command signal READ and the read switching signal RR are sent to the first and second read switch circuits SW1 through gates g+n to g3m. SW2 is selected and its input is brought out to read output bus RB. For example, when the read command signal READ becomes 1'', the read switching signal R
When R“0” is input, gate g IIl+ g
The output of 2゜+g3□ is "1" respectively.

“1°,” becomes “0” and the first readout switch circuit SW
1 is turned on, the second readout switch circuit SW2 is turned off, and the first latch circuit L1.1 is turned on. Output A. -A4.
P to the read output bus RB.

Furthermore, when the read switching signal RR "1" is input, the outputs of the gates g++++g2, 1g31 are respectively "0".

"O", "1" and the first read switch circuit SW
1 is turned off, the second readout switch circuit S W 2 is turned on, and the second latch circuit L2 . Output A. -A
4. P to the read output bus RB.

That is, in the control system having the above configuration, the selection signal A o −
The parity signal P is transmitted together with A4, and the latch circuit L
A parity check is performed for each output of 1m + L2°, and if an error occurs, an error signal PE is sent.
,, PE2 is sent to the host computer. As a result, each latch circuit L1°, L2 . It is possible to identify whether or not a correct selection signal is held, and interrupt processing for maintenance can be executed on the host computer side. Further, by inputting the read command signal READ and the read switching signal RR, the outputs A0 to A4 of fi are activated by the first latch circuit. P or second latch circuit L2. Outputs A, -A4. Since P can be sent to the readout output bus RB and derived to the host computer, it is also possible to sequentially monitor the storage contents of all latch circuits. This can significantly shorten the response time from error occurrence to countermeasures.

[Effects of the Invention] As described above, according to the present invention, the delay time between lines is uniform, and distortion occurring during signal transmission can be sufficiently suppressed, thereby increasing the speed of transmitted digital signals. , it is possible to provide a digital signal exchanger that can easily increase the number of lines.

[Brief explanation of the drawing]

The drawings show an embodiment of a digital signal exchanger according to the present invention. Fig. 1 is a block circuit diagram showing the overall configuration (control system is omitted here), and Fig. 2 shows a selector module of the same embodiment. FIG. 3 is a block circuit diagram showing the structure of the gate array constituting the selector module; FIG. 4 is a block circuit diagram showing the internal structure of the selector module; FIG. The figure is a logic circuit diagram showing the specific configuration of the gate array.
FIG. 6 is a logic circuit diagram showing the configuration of 2×1 gates used in the gate array, FIG. 7 is a block circuit diagram showing the configuration of the control system of the selector module, and FIG. 8 is a checker diagram suitable for the control system. FIG. 9 is a block circuit diagram showing the structure of the mechanism, and FIG. 9 is a logic circuit diagram showing the structure of a parity check circuit used in the above-mentioned check mechanism. 81~S2, 6... Selector module, a... Board, IB, ~IB, 6... Internal input bus, BD, ~B
D, 6...Bus driver, CB, ~CB 256...
・Internal common bus, OB, ~0B16...Internal output bus, 11~I+6...Internal input bus line, 01~CI
6...Internal common path line, 01-016...Internal output bus line, A, -A4...Control path line, I
I, ~II, 6... Intra-module input bus line, G
l~G+6...Gate array, gl...16X1 first gate, gl...2X1 second gate, g3
...Synchronous circuit, go+~ga, ...2x1 gate,
AD...address data, C5...chip select signal, WRITE...write command signal, LOAD...
・Load command signal, L, □L2. ...Latch circuit, A
DD: address decoder, P: parity signal,
E V E N10 D D...Even number/odd number designation signal, READ...Read command signal, RR...Read switching signal, RB...Read output bus, WB...Write output bus, PE+, PE2 ... Parity error signal, PC,, PC2 ... First and second parity check circuits, SW+, sw2 ... First and second readout switch circuits, go1 to go3 ... Exclusive OR Gate. Applicant's agent Patent attorney Takehiko Suzue 01-016 017-0320CA~o256 Figure 1 Figure 2 n n Figure 3 On Figure 5 Figure 9

Claims (6)

[Claims] (1) A first selection section that selects one line from n (n is a natural number) first input lines and connects it to one output line; m (m is a natural number) basic selection circuits each including a second selection section that selects one line from the second input line and connects it to one output line; 1. A digital signal exchanger comprising a selection module having an input bus that commonly connects one input line to n input lines. (2) The selection modules are arranged in k rows and l columns, input buses are commonly connected in each row, and m output lines in each same column are connected to m second input lines of the selection module in the next row. 2. The digital signal exchanger according to claim 1, wherein the digital signal exchanger is connected to a digital signal exchanger. (3) The digital signal exchanger according to claim 1, wherein the m basic selection circuits each have synchronization means for synchronizing the digital signals transmitted to each other's output lines. (4) The synchronization means is characterized in that a flip-flop is interposed between the second selection section and the output line, and the flip-flops of each basic selection circuit are driven by the same clock. 3) Digital signal exchanger as described. (5) The digital signal exchanger according to claim (1), wherein the selection module is formed of an integrated circuit device. (6) The first selection section of the basic selection circuit includes a plurality of 2
The digital signal exchanger according to claim 1, characterized in that the digital signal exchanger is constructed by combining input and output selection switch elements.