JPH0520344U - Semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] It is an object to prevent malfunction in a circuit in which two or more bipolar transistors of the same type are arranged in the same island due to current flowing in the parasitic transistor or the parasitic circuit. [Structure] A diffusion region having a sub-potential is arranged between two or more bipolar transistors.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a semiconductor device having a circuit in which two or more bipolar transistors of the same type are arranged in the same island.

[0002]

[Prior Art]

FIG. 3 (a) is a plan view showing the layout of a diffusion region in an example of a circuit in which two bipolar transistors of the same type are arranged in the same island of a conventional semiconductor device of this type, and FIG. 3A is a sectional view showing the sectional structure, and FIG. 3C is a circuit diagram showing an example of the equivalent circuit of FIG. 3A. In the figure, 1 is a substrate, 2 is a buried layer, 3 is an epitaxial layer region, 4 is an isolation diffusion region, 5 is a P-type diffusion region, and 6 is an N-type diffusion region. In the example in which two NPN transistors Q ₁ and Q ₂ are arranged in the same island, in the conventional mask layout, a potential is applied to the N type diffusion region 9 between the NPN transistor Q ₁ and the NPN transistor Q _2. As a result, the potential of the epitaxial layer region 3 is determined. At this time, if the potential of the epitaxial layer region 3 partially or entirely decreases due to the saturation of the NPN transistor, the parasitic PNP transistor Q ₃ operates, and the parasitic PN transistor Q ₃ operates in the circuit shown in FIG. the collector current of the P-transistor Q ₃ is to flow into Mutame to the base of the NPN transistor Q _2, NPN transistor Q ₂ to malfunction become oN.

FIG. 4A is a plan view showing a layout of a diffusion region in an example of a circuit in which two lateral PNP transistors are arranged in the same island of a conventional semiconductor device of this type, and FIG. 4A is a sectional view showing the sectional structure, and FIG. 4C is a circuit diagram showing an example of the equivalent circuit of FIG. 4A. In the figure, reference numerals 1, 2, 3, and 4 denote the same or corresponding portions as those in FIG. This is the N-type diffusion region of the base of the transistor. A current mirror circuit constituted by the placement is two lateral PNP transistor are as described above in the same island, as shown in FIG. 4 (c), the P-type diffusion region 5a of the emitter for Q ₁ injected current is collected mainly by P-type diffusion region 5b of the collector portion for Q _1, but the degree also reach the collector of Q _2, the collector current of Q _2. This current changes depending on various conditions such as the distance between the emitter and collector, the potential difference, and the collector area. When the collector current of Q ₂ is sufficiently smaller than the collector current of Q ₁ , the parasitic current becomes a large error factor with respect to the original collector current of Q ₂ .

[0004]

[Problems to be solved by the device]

 In a conventional circuit in which two or more bipolar transistors of the same type are arranged in the same island, the malfunction of the parasitic transistor may occur as described above, or the emitter of one transistor may pass through the parasitic circuit to the other. There was a problem that current flows in the collector part of the transistor, causing an error. The present invention has been made to solve the above problems, and an object thereof is to provide a device that does not cause a malfunction due to the operation of a parasitic transistor or an error caused by a current flowing through a parasitic circuit. And

[0005]

[Means for Solving the Problems]

 In the semiconductor device of the present invention, when an N-type diffusion region is provided between two transistors arranged in the same island, the N-type diffusion region is removed, and the N-type diffusion region is removed between the two transistors. A diffusion region having a sub-potential is provided.

[0006]

【Example】

FIG. 1A is a plan view showing a layout of diffusion regions in a circuit in which two bipolar transistors of the same type are arranged in the same island according to an embodiment of the present invention, and FIG. ) Is a sectional view showing a sectional structure, and FIG. 1C is a circuit diagram showing an equivalent circuit of FIG. In the figure, the same reference numerals as those in FIG. 3 indicate the same or corresponding portions, and 7 is a P-type diffusion region formed by the same diffusion as the P-type diffusion region 5. This P-type diffusion region 7 is connected to the isolation diffusion region 4 and has a sub-potential. When the structure as described above, the base resistance of the parasitic PNP transistor Q ₃ is greatly parasitic PNP transistor Q ₃ is less likely to work, and by the presence of the P-type diffusion region 7 sub the same potential, parasitic Even if the PNP transistor Q ₃ operates, the collector current of the parasitic PNP transistor Q ₃ flows toward the substrate 1 and is less likely to flow toward the base of the NPN transistor Q _2. Therefore, the abnormal operation of the NPN transistor Q ₂ may occur. Can be suppressed.

FIG. 2A is a plan view showing a layout of a diffusion region in a circuit in which two lateral transistors P NP transistors are arranged in the same island according to an embodiment of the present invention, and FIG. 2 (a) is a sectional view showing a sectional structure, and FIG. 2 (c) is a circuit diagram showing an equivalent circuit of FIG. 2 (a). In the figure, the same reference numerals as those in FIG. 4 indicate the same or corresponding portions, and 7 indicates the portions corresponding to the portions indicated by the same reference numerals in FIG. When the structure as described above, the current flowing from the emitter of the lateral transistor Q ₁ to the collector portion is absorbed by the P-type diffusion region 7, which reaches the collector portion Q ₂ 'is eliminated almost, Q _2' Error in collector current is suppressed. In the embodiment of the present invention, two transistors are arranged, but in the case of two or more transistors, a similar effect can be obtained by arranging a diffusion region having a sub-potential between each transistor.

[0008]

[Effect of the device]

 As described above, according to the present invention, in a circuit in which two or more bipolar transistors of the same type are arranged in the same island, the parasitic transistor may malfunction due to the operation of the parasitic transistor or the current of the parasitic circuit may cause the current of the transistor to flow. There is no error with the design value, and the effect of contributing to the improvement of reliability is significant.

[Brief description of drawings]

FIG. 1 is a plan view, a cross-sectional view, and a circuit diagram showing the structure of a target circuit according to an embodiment of the present invention.

FIG. 2 is a plan view, a cross-sectional view, and a circuit diagram showing the structure of a target circuit according to another embodiment of the present invention.

FIG. 3 is a plan view, a cross-sectional view, and a circuit diagram showing a structure of a target circuit in an example of a conventional semiconductor device of this type.

FIG. 4 is a plan view, a sectional view, and a circuit diagram showing the structure of a target circuit in another example of the conventional semiconductor device of this type.

[Explanation of symbols]

 1 Substrate 2 Buried Layer 3 Epitaxial Layer Region 4 Isolation Diffusion Region 5 P-type Diffusion Region 6 N-type Diffusion Region 7 P-type Diffusion Region

Claims (1)

[Scope of utility model registration request] 1. In a semiconductor device having a circuit in which two or more bipolar transistors of the same type are arranged in the same island, a diffusion region having a sub-potential is arranged between the two or more bipolar transistors. A semiconductor device characterized by: