JPS5933848A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS5933848A JPS5933848A JP14413282A JP14413282A JPS5933848A JP S5933848 A JPS5933848 A JP S5933848A JP 14413282 A JP14413282 A JP 14413282A JP 14413282 A JP14413282 A JP 14413282A JP S5933848 A JPS5933848 A JP S5933848A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- island
- schottky barrier
- island region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims abstract description 17
- 230000004888 barrier function Effects 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000000926 separation method Methods 0.000 claims 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 9
- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 238000002955 isolation Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体集積回路、特にサイリスタ寄生効果を防
止した半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit that prevents thyristor parasitic effects.
従来の半導体集積回路に於いては第１図及び第２図に示
す如く、Ｐ型の半導体基板（１）上にＮ型のエピタキシ
ャル層（２）を形成し、Ｐ１型の分離領域（３）でエビ
タキシャ／Ｌ’層（２）をＰＮ分離した島領域（４）を
形成し、１つの島領域（４）にＰ型の抵抗領域（５）と
これに近接してＰ型およびＮ型の二重拡散領域（６）と
を形成すると、サイリスク寄生効果が発生する。In a conventional semiconductor integrated circuit, as shown in FIGS. 1 and 2, an N-type epitaxial layer (2) is formed on a P-type semiconductor substrate (1), and a P1-type isolation region (3) is formed on a P-type semiconductor substrate (1). An island region (4) is formed by separating the Ebitaxia/L' layer (2) by PN, and one island region (4) has a P-type resistance region (5) and a P-type and N-type resistance region (5) adjacent to it. When a double diffusion region (6) is formed, a cyrisk parasitic effect occurs.
島領域（４）は通常型ｍ （７）を介して最高電位にバ
イアスされているが、島領域（４）の持つ抵抗によシミ
圧降下をして抵抗領域（５）エピタキシャル層（２）お
よび二重拡散領域（６）で形成される寄生サイリスタを
オンさせてしまう。二重拡散領域（６）としてはトンネ
ル接続するためのトンネル領域あるいはＮＰＮトランジ
スタのベース−エミッタ領域がある。The island region (4) is biased to the highest potential through the normal type m (7), but due to the resistance of the island region (4), a pressure drop occurs and the resistive region (5) and the epitaxial layer (2) And the parasitic thyristor formed by the double diffusion region (6) is turned on. The double diffusion region (6) is a tunnel region for tunnel connection or a base-emitter region of an NPN transistor.
本発明は斯点に鑑みてなされ、従来の欠点を除去する半
導体集積回路を提供するものである。以下に第６図およ
び第４図を参照して本発明の一実施例を詳述する。なお
第１図および第２図と共通するものは同一図番を付した
。The present invention has been made in view of this point, and provides a semiconductor integrated circuit that eliminates the conventional drawbacks. An embodiment of the present invention will be described in detail below with reference to FIGS. 6 and 4. Components common to FIGS. 1 and 2 are given the same number.
本発明に依る半導体集積回路は、Ｐ型の半導体基板（１
）上にＲ型エピタキシャル層（２）を形成し、Ｐ＋型の
分Ｓ領域（３）でエピタキシャル層（２）をＰＮ分離し
た島領域（４）を形成し、１つの島領域（４）にｐ＋、
の抵抗領域（５）とこれに近接してＰ型およびＮ１型の
二重拡散領域（６）とを形成し、更に本発明の特徴とす
るショットキーバリアダイオードＧＯ＋（１１）を島領
域（４）表面に形成し抵抗領域（５）と接続するかある
いは他の島領域（１２）表面に形成し二重拡散領域（６
）と接続して構成される。The semiconductor integrated circuit according to the present invention has a P-type semiconductor substrate (1
), an R-type epitaxial layer (2) is formed on the P+ type S region (3), and an island region (4) is formed by separating the epitaxial layer (2) into PN regions. p+,
A resistive region (5) and a P-type and N1-type double diffusion region (6) are formed adjacent to the resistive region (5), and a Schottky barrier diode GO+ (11), which is a feature of the present invention, is formed in the island region (4). ) formed on the surface and connected to the resistance region (5), or formed on the surface of another island region (12) and connected to the double diffusion region (6).
).
二重拡散領域（６）はベースおよびエミッタ拡散で形成
されるトンネル領域あるいはＮＰＮ ）ランリスクのベ
ースおよびエミッタ領域が該当する。The double diffusion region (6) corresponds to a tunnel region formed by base and emitter diffusions or a base and emitter region of a run risk (NPN).
１つの′／ロットキーバリアダイオード００）は島領域
（４）の抵抗領域（５）のコンタクト孔（１３）の近傍
に島領域（４）表面を露出して点線で示す蒸着アルミニ
ウム（１４１によシ形成し、この蒸着アルミニウムで抵
に領域（５）と接続する。この結果ショットキーバリア
ダイオード００）は第４図に示す如く、抵抗領域（５）
と島領域（４）間に順方向に接続される。One '/Rottky barrier diode 00) is formed by exposing the surface of the island region (4) near the contact hole (13) of the resistance region (5) of the island region (4) and depositing aluminum (141) as shown by the dotted line. A Schottky barrier diode (00) is formed in the resistive region (5) as shown in FIG.
and the island region (4) in the forward direction.
他方のショットキーバリアダイオード（１１）は独立し
た他の島領域（１２）にｆｍのコンタクト拡散（１５）
と露出領域０６）を設け、蒸着アルミニウム０７）によ
シ露出領域０６）に形成する。そして蒸着アルミニウム
（１７）ヲ用いてショットキーバリアダイオードα１）
を二重拡散領域（６）のＰ型頭域とＮ型領域間に順方向
に接続される。The other Schottky barrier diode (11) has an fm contact diffusion (15) in another independent island region (12).
and exposed areas 06) are provided, and evaporated aluminum 07) is formed in the exposed areas 06). And Schottky barrier diode α1) using vapor-deposited aluminum (17)
is connected in the forward direction between the P-type head region and the N-type region of the double diffusion region (6).
本発明に依るショットキーバリアダイオード（１０）（
１１）はいずれか一方あるいは両方を用心）ても効果が
あり、その等価回路図は第４図に示す如くなる。Schottky barrier diode (10) according to the present invention (
11) is effective even if one or both of them are used with caution, and the equivalent circuit diagram thereof is shown in FIG.
第４図に於いてＴｒｌはＰ型抵抗価域（５）島領域（４
）および二重拡散領域（６）のＰ型頭域で形成されるＰ
ＮＰ）ランリスクであり、Ｔｒ２は島領域（４）および
二重拡散領域（６）で形成されるＮＰＮ）ランリスクで
あシ、Ｓ Ｄ Ｉは島領域（４）に形成されるショット
キーバリアダイオードで、８Ｄ２は他の島領域（１２）
に形成されるショットキーバリアダイオードである。In Figure 4, Trl is the P-type resistance region (5) and the island region (4
) and P formed by the P-type head region of the double diffusion region (6)
NP) is the run risk, Tr2 is the NPN) run risk formed by the island region (4) and the double diffusion region (6), and SDI is the Schottky barrier formed in the island region (4). In the diode, 8D2 is another island area (12)
This is a Schottky barrier diode formed in
斯る本発明の構成に依れば、ＴｒｌおよびＴｒ２０ベー
ス・エミッタ間がショットキーバリアダイオードＳＤＩ
、８Ｄ２によ、！ｌ）０．３■にクラシブされるので、
寄生サイリスタはオンすることがなく寄生効果を完全に
防止できる。According to the configuration of the present invention, the Schottky barrier diode SDI is connected between the base and emitter of Tr1 and Tr20.
, 8D2! l) Since it is classified to 0.3■,
The parasitic thyristor never turns on, completely preventing parasitic effects.
以上に詳述した如く本発明に依れば、ショットキーバリ
アダイオードを設けるのみで従来と同一構造であっても
寄生サイリスク効果を防止できる有益なものであシ、従
来と同一製造工程により達成できる利点を有する。As detailed above, according to the present invention, the parasitic cyrisk effect can be effectively prevented even if the structure is the same as the conventional one by simply providing a Schottky barrier diode, and this can be achieved by the same manufacturing process as the conventional one. has advantages.
第１図は従来例を説明する上面図、第２図は第１図のＩ
−ｌ線断面図、第６図は本発明を説明する上面図、第４
図は本発明の等価回路図である。
主な図番の説明
（１）はＰ型半導体基板、（２）はＮ型エピタキシャル
層、（４）は島領域、（５）はＰ型抵抗領域、（６）は
二重拡散領域、α０）（１１１はショットキーバリアダ
イオード、（１４）（１７）ハＭ 着アルミニウムでア
ル。
第１図
第２図Fig. 1 is a top view explaining a conventional example, and Fig. 2 is an I of Fig. 1.
6 is a top view explaining the present invention, and 4th
The figure is an equivalent circuit diagram of the present invention. Explanation of main drawing numbers: (1) is P-type semiconductor substrate, (2) is N-type epitaxial layer, (4) is island region, (5) is P-type resistance region, (6) is double diffusion region, α0 ) (111 is a Schottky barrier diode, (14) (17) is made of aluminum coated with M. Fig. 1 Fig. 2
Claims (1)
型のエピタキシャル層と該エビタキシャ／Ｌ／層を島領
域に分離する一導電型の分離領域と一つの前記島領域に
隣接して設けた一導電型の抵抗領域と一導電型および逆
導電型の二重拡散領域とを具備する半導体集積回路にお
いて、前記抵抗領域と島領域間あるいは前記二重拡散領
域間にシロットキーバリアダイオードを接続することを
特徴とする半導体集積回路。1. - A semiconductor substrate of a conductivity type, an epitaxial layer of an opposite conductivity type laminated on the substrate, and a separation region of one conductivity type that separates the epitaxial layer/L/layer into island regions, and adjacent to one of the island regions. In a semiconductor integrated circuit comprising a resistance region of one conductivity type and a double diffusion region of one conductivity type and opposite conductivity type, a Sirotchi barrier diode is provided between the resistance region and the island region or between the double diffusion region. A semiconductor integrated circuit characterized by connecting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14413282A JPS5933848A (en) | 1982-08-19 | 1982-08-19 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14413282A JPS5933848A (en) | 1982-08-19 | 1982-08-19 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5933848A true JPS5933848A (en) | 1984-02-23 |
Family
ID=15354950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14413282A Pending JPS5933848A (en) | 1982-08-19 | 1982-08-19 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5933848A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009051657A (en) * | 2007-08-29 | 2009-03-12 | Toshiba Corp | Sheet take-out apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5433681A (en) * | 1977-08-22 | 1979-03-12 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS54131890A (en) * | 1978-04-05 | 1979-10-13 | Toshiba Corp | Semiconductor device |
-
1982
- 1982-08-19 JP JP14413282A patent/JPS5933848A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5433681A (en) * | 1977-08-22 | 1979-03-12 | Hitachi Ltd | Semiconductor integrated circuit device |
| JPS54131890A (en) * | 1978-04-05 | 1979-10-13 | Toshiba Corp | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009051657A (en) * | 2007-08-29 | 2009-03-12 | Toshiba Corp | Sheet take-out apparatus |
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