JPH0520141U - Memory bank switching circuit in D-RAM - Google Patents

Abstract

(57) [Abstract] [Purpose] A large-capacity D-RAM can be added, and a circuit for bank switching is not required. A counter for counting refresh addresses and a selection circuit for selecting an upper address of a D-RAM are used as a refresh address, a last address RAS, and a CAS address CAS, respectively. The memory banks are switched by switching at the timing to increase the memory capacity per bank, and a circuit for generating the CAS signal CAS for bank switching becomes unnecessary.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a memory bank switching circuit in a D-RAM, and particularly suitable for switching a memory bank in a D-RAM access that specifies an address beyond the memory capacity of the CPU that can be directly referred to. Is.

[0002]

[Prior Art]

 As is well known, in a computer or the like, bank switching may be performed to specify an address beyond the memory capacity that can be directly referred to by the CPU. In the bank switching described above, the address space is divided into several parts, the program is virtually allocated to the addresses, and then the block containing the address pointed to by the address register is stored in the main memory. It loads and runs the program.

FIG. 3 is a circuit block diagram showing an example of a conventional D-RAM memory bank switching circuit in an 8-bit CPU. In FIG. 3, OSC1 is an oscillator for the operation of this circuit, and its oscillation output is given to the control circuit 2. The control circuit 2 is a D-RAM control signal generation circuit, and the signals output from the control circuit 2 are the CPU 3, the counter 5, the first selector 6, the second selector 7, the D-RAMs 16 to 19, the OR gate 14, 15, etc.

The CPU 3 is an 8-bit microprocessor for control, and is connected to the control circuit 2, the latch circuit 4, the second selector 7, the inverter 13, the OR gate 14, and the D-RAMs 16 to 19. The latch circuit 4 is a circuit provided for latching the lower address of the CPU 3 and is connected to the first selector 6.

The counter 5 is an 8-bit counter circuit and is connected to the first selector 6. The first selector 6 is a circuit for selecting an input signal, and is connected to the second selector 7. The second selector 7 is a circuit for selecting an input signal and is connected to the D-RAMs 16-19.

Next, 13 is an inverter, which is connected to the OR gate 15. The OR gate 15 is connected to the D-RAMs 18 and 19, respectively. An OR gate 14 is provided in addition to the OR gate 15, and the OR gate 14 is connected to the D-RAMs 16 and 17. These four D-RAMs 16 to 19 are dynamic RAMs that require a refresh operation and are connected to the CPU 3. These D-RAMs 16 to 19 have a storage capacity of 64K × 4 bits, for example.

Next, the basic operation of the circuit of FIG. 3 will be described. The oscillator output output from OSC1 is input to the input terminal CLK1 of the control circuit 2. Then, it is directly output as the clock signal CLK1 and input to the input terminal CLK1 of the CPU3. The CPU 3 synchronizes with the clock signal CLK1 and outputs the address latch enable signal ALE (hereinafter simply referred to as ALE signal) and the program sense enable signal PSEN (hereinafter simply referred to as PSE N signal) at the timing shown in the time chart of FIG. Read signal RD, write signal WR, AD0 to AD7, A8 to A15, and ports P0 and P1.

The control circuit 2 synchronizes with the clock signal CLK1 by the ALE signal and the PSEN signal, and at the timing shown in the timing chart of FIG. 5, the lath clock signal RCL K, the read / write signal R / W, and the cache address signal CADR. , Russ signal R AS and Cass signal CAS are output. The latch circuit 4 latches the lower addresses AD0 to AD7 output from the CPU 3 and outputs the addresses A0 to A7 to the first selector 6 at the falling edge of the ALE signal output from the CPU 3.

The counter 5 is an 8-bit counter that counts the refresh address of the D-RAM according to the last clock signal RCLK output from the control circuit 2, and outputs the refresh addresses FA0 to FA7 to the first selector 6. The first selector 6 inputs the refresh addresses FA0 to FA7 output from the counter 5 to the input terminals 0A to 7A, and inputs the addresses A0 to A7 output from the latch circuit 4 to the input terminals 0B to 7B. The read / write signal R / W output from the control circuit 2 is input to the input terminal S. When the read / write signal R / W is "0", the refresh addresses FA0 to FA0 are output. F A7 is output to the second selector 7 as RAS addresses RA0 to RA7. When the read / write signal R / W is "1", the addresses A0 to A7 are output to the second selector 7 as the RAS addresses RA0 to RA7.

The second selector 7 inputs the RAS addresses RA0 to RA7 output from the first selector 6 to the input terminals 0A to 7A, and outputs the addresses A8 to A14 (CAS addresses CA0 to CA6) output from the CPU 3. To the input terminals 0B to 6B. Similarly, the port P0 signal output from the CPU 3 is input to the input terminal 7B, and the cache address signal CADR output from the control circuit 2 is input to the input terminal S. When the cache address signal CADR is "0", the RAS addresses RA0 to RA7 are output to the D-RAMs 16 to 19 as the memory addresses MA0 to MA7. When the cache address signal CADR is "1", the addresses A8 to A14 (CAS addresses CA0 to CA6) and the port P0 signal are output to the D-RAMs 16 to 19 as memory addresses MA0 to MA7.

The inverter 13 inverts the logic of the port P1 signal output from the CPU 3 and outputs the inverted signal to the OR gate 15. The OR gate 14 outputs a logical sum of the port P1 signal output from the CPU 3 and the CAS signal CAS output from the control circuit 2 to the D-RAMs 16 and 17. On the other hand, the OR gate 15 outputs the logical sum of the output signal of the inverter 13 and the CAS signal CAS output from the control circuit 2 to the D-RAMs 18 and 19.

The D-RAMs 16 and 17 input the memory addresses MA0 to MA7 output from the second selector 7 to the input terminals A0 to A7, and input the read signal RD and the write signal WR output from the CPU 3. Input to terminals OE and WR, respectively. Further, the lath signal RAS output from the control circuit 2 is input to the input terminal RAS, and the CAS signal CAS0 output from the OR gate 14 is input to the input terminal CAS0. Then, it is specified by the RAS addresses A0 to A7 specified by the input terminals A0 to A7 at the falling edge of the glass signal RAS and the CAS addresses A0 to A7 specified by the input terminals A0 to A7 at the falling edge of the CAS signal CAS0. When the input terminal OE is "0", the data in the stored memory area is output to the CPU 3 via the data buses AD0 to AD7.

When the input terminal WR is "0", the data D0 to D7 on the data buses AD0 to AD7 output from the CPU 3 are written in the designated memory area. In the cycle in which the CAS signal CAS0 remains "1" and only the last signal RAS falls, the areas of the refresh addresses FA0 to FA7 designated by the input terminals A0 to A7 are refreshed (RAS only refresh). The D-RAMs 18 and 19 are all the same as the D-RAMs 16 and 17 except that the CAS signal CAS1 output from the OR gate 15 is input to the input terminal CAS1.

Next, the operation of the circuit of FIG. 3 will be described with reference to the D-RAM access time chart of FIG. First, at the time of refreshing, the count value counted up by the rising of the last clock signal RCL K output from the control circuit 2 is output from the counter 5 as the refresh addresses FA0 to FA7. At this time, since the read / write signal R / W output from the control circuit 2 is "0", the first selector 6 outputs the refresh addresses FA0 to FA7 as RAS addresses RA0 to RA7. Since the cache address signal CADR output from the control circuit 2 is "0", the second selector 7 outputs the RAS addresses RA0 to RA7 as the memory addresses MA0 to MA7. Then, the D-RAMs 16 to 19 refresh the memory area specified by the memory addresses MA0 to MA7 at the fall of the last signal RAS output from the control circuit 2.

Next, at the time of D-RAM read, the lower addresses AD0 to AD7 (b) output from the CPU 3 are latched by the latch circuit 4 at the falling edge of the ALE signal output from the CPU 3, and the addresses A0 to A7 are read. Is output as. Then, since the read / write signal R / W output from the control circuit 2 becomes "1", the output of the first selector 6 switches from the refresh address FA0 to FA7 to the address A0 to A7. At this time, since the cache address signal CADR output from the control circuit 2 is "0", the second selector 7 outputs the addresses A0 to A7 as the memory addresses MA0 to MA7. Then, the RAS address is fixed in the D-RAMs 16 to 19 at the fall of the last signal R AS output from the control circuit 2.

Next, since the cache address signal CADR output from the control circuit 2 becomes "1", the second selector 7 switches from the RAS address RA0 to RA7 to the CAS address CA0 to CA6 and outputs the same. , CAS addresses are confirmed in the D-RAMs 16 to 19 at the fall of the CAS signals CAS0 and CAS1 output from the control circuit 2. When the read signal RD output from the CPU 3 is "0", the D-RAMs 16 to 19 output the data D0 to D7 in the designated memory area to the data buses AD0 to AD7. Similarly, at the time of D-RAM write, when the write signal WR output from the CPU 3 is "0", the D-RAMs 16 to 19 write the data D0 to D7 of the data buses AD0 to AD7 in the designated memory area. ..

Next, the bank switching method of the D-RAM will be described with reference to FIG. 4 and Table 2. FIG. 4 is a conventional memory map in which a 32K.times.8-bit memory area is divided into four banks # 0 to # 3. The addresses for the respective banks are as shown in FIG. 4, and the correspondence between the port P1 signal output from the CPU 3 and the banks # 0 to # 3 is set as shown in Table 2.

[Table 2]

As is clear from Table 2, the CAS signal CAS0 is output from the OR gate 14 in the bank # 0 and the bank # 1. Further, in the case of banks # 2 and # 3, the CAS signal CAS1 is output from the OR gate 15, and the D-RAM corresponding to each bank is selected.

Further, the correspondence between the port P0 signal output from the CPU3 and the banks # 0 to # 3 is as shown in Table 2. The port P0 signal causes the CAS address A7, which is the most significant bit in FIG. The banks # 0 and # 1 and the banks # 2 and # 3 are separated by being controlled. In this case, the timing of each signal is as shown in the time chart of FIG. Conventionally, the four banks # 0 to # 3 are switched by controlling the CAS signal CAS of the D-RAM in this way.

[0020]

[Problems to be solved by the device]

 However, since the bank switching circuit described above is 32 × 8 bits × 4 banks, it can only support a memory capacity of 128 × 8 bits. Moreover, since only a 64 × 8-bit D-RAM can be added, the mounting space increases and the CAS signal CAS must be selected and applied to the D-RAM for bank switching. -Each time the number of RAMs is increased, a circuit for generating the CAS signals CAS2 to CASn has to be newly added, which causes various problems such as a large number of parts. In view of the above problems, it is an object of the present invention to add a large-capacity D-RAM and eliminate the need for a circuit for switching banks.

[0021]

[Means for Solving the Problems]

 The memory bank switching circuit in the D-RAM of the present invention is a circuit in which the memory bank switching of the D-RAM is performed by an 8-bit CPU, and by generating and outputting various signals as a reference of circuit operation. A control circuit for controlling the D-RAM, a counter for counting the refresh address of the D-RAM, and a selection circuit for selecting the refresh address, the last address RAS, and the CAS address CAS. By selecting the high-order address signal states "1" and "0" in the CAS address CAS and the high-order address signal states "1" and "0" in the last address RAS. -Switching means for switching the memory banks of the RAM are provided.

[0022]

[Action]

 A counter for counting the refresh address and a selection circuit for selecting the upper address of the D-RAM select the upper address of the D-RAM for the refresh address, the last address RAS, and the CAS address CAS at respective timings. By switching the memory banks, the memory capacity per bank can be increased and the circuit for generating the CAS signal CAS for bank switching becomes unnecessary.

[0023]

【Example】

 FIG. 1 is a circuit block diagram showing an embodiment of the present invention. In FIG. 1, OS C1 is an oscillator circuit for the operation of this circuit, and its output is given to the control circuit 2. The control circuit 2 is a circuit provided to create a D-RAM control signal, and includes a CPU 3, a counter 5, a first selector 6, a second selector 7, a third selector 9, and a fourth selector 4. Is connected to the selector 10 and D-RAMs 11 and 12.

The CPU 3 is an 8-bit microprocessor for control, and is connected to the control circuit 2, the latch circuit 4, the second selector 7, the third selector 9, the fourth selector 10, and the D-RAMs 11 and 12. Has been done. The latch circuit 4 is a circuit for latching the lower address of the CPU 3 and is connected to the first selector 6.

The counter 5 is an 8-bit counter circuit and is connected to the first selector 6 and the flip-flop F / F8. The first selector 6 is a circuit that selects an input signal, and is connected to the second selector 7. The second selector 7 is a circuit that selects an input signal and is connected to the D-RAMs 11 and 12.

The F / F 8 is a flip-flop and is connected to the third selector 9. The third selector 9 is a circuit that selects an input signal and is connected to the fourth selector 10. Similarly, the fourth selector 10 is a circuit for selecting an input signal and is connected to the D-RAMs 11 and 12. The D-RAMs 11 and 12 are dynamic RAMs that require a refresh operation, have a storage capacity of 256K × 4 bits, and are connected to the CPU 3.

Next, the basic operation of the circuit of this embodiment will be described. The oscillator output output from OSC1 is input to the input terminal CLK1 of the control circuit 2. Then, it is directly output as the clock signal CLK1 and input to the input terminal CLK1 of the CPU3. The CPU 3 synchronizes with the clock signal CLK1 and outputs each signal of the ALE signal, PSEN signal, read signal RD, write signal WR, AD0 to AD7, A8 to A15, P0 and P1 at the timing shown in the time chart of FIG. Output.

The control circuit 2 is synchronized with the clock signal CLK1 by the ALE signal and the PSEN signal, and at the timing shown in the timing chart of FIG. 5, the last clock signal RCL K, the read signal R / write signal W, and the cache address signal CADR. , Las signal RAS and CAS signal CAS are output. The latch circuit 4 latches the lower addresses AD0 to AD7 output from the CPU 3 and outputs the addresses A0 to A7 to the first selector 6 at the falling edge of the ALE signal output from the CPU 3.

The counter 5 is an 8-bit counter that counts the refresh addresses FA0 to FA7 of the D-RAM according to the last clock signal RCLK output from the control circuit 2, and the refresh addresses FA0 to FA7 are supplied to the first selector 6. And outputs the signal NFA7 to the flip-flop F / F8. The first selector 6 inputs the refresh addresses FA0 to FA7 output from the counter 5 to the input terminals 0A to 7A, inputs the addresses A0 to A7 output from the latch circuit 4 to the input terminals 0B to 7B, and controls them. When the read / write signal R / W output from the circuit 2 is input to the input terminal S and the read / write signal R / W is "0", the refresh addresses FA0 to FA7 are output as RAS addresses RA0 to RA7. Then, when the read / write signal R / W is "1", the addresses A0 to A7 are output to the second selector 7 as the RAS addresses RA0 to RA7.

The second selector 7 inputs the RAS addresses RA0 to RA7 output from the first selector 6 to the input terminals 0A to 7A, and outputs the addresses A8 to A15 (CAS addresses CA0 to CA7) output from the CPU 3. To the input terminals 0B to 7B, and the port P0 signal output from the CPU 3 is input to the input terminal 7B. Similarly, when the cache address signal CADR output from the control circuit 2 is input to the input terminal S and the cache address signal CADR is "0", the RAS addresses RA0 to RA7 are used as the memory addresses MA0 to MA7 in the D-RAM11. , 12 is output.

When the cache address signal CADR is “1”, the addresses A8 to A15 (CAS addresses CA0 to CA7) and the port P0 signal are output to the D-RAMs 11 and 12 as memory addresses MA0 to MA7. .. The flip-flop F / F8 is a flip-flop that counts the refresh address FA8 of the D-RAM by the signal NFA7 output from the counter 5, and outputs the refresh address FA8 to the third selector 9.

The refresh address FA8 output from the flip-flop F / F8 and the port P0 signal output from the CPU 3 are input to the third selector 9, and the read address output from the control circuit 2 is input. When the write signal R / W is “0”, the refresh address FA8 is output to the fourth selector 10 as the RAS address RA8. When the read / write signal R / W output from the control circuit 2 is "1", the port P0 signal is output to the fourth selector 10 as the RAS address RA8.

The RAS address RA8 output from the third selector 9 and the port P1 signal output from the CPU 3 are input to the fourth selector 10, and the cache address output from the control circuit 2 is input. When the signal CADR is "0", the RAS address RA8 is output to the D-RAMs 11 and 12 as the memory address MA8. When the cache address signal CADR output from the control circuit 2 is "1", the port P1 signal output from the CPU 3 is output to the D-RAMs 11 and 12 as the memory address MA8.

The D-RAMs 11 and 12 receive the input terminals A0 to A7 to which the memory addresses MA0 to MA7 output from the second selector 7 are input and the memory addresses MA8 output from the fourth selector 10, respectively. There are provided an input terminal A8 to be input and input terminals OE and WR to which the read signal RD and the write signal WR output from the CPU 3 are input. Further, input terminals RAS and CAS to which the lath signal RAS and the CAS signal CAS output from the control circuit 2 are input are provided, and the falling of the lath signal RAS designates the input terminals A0 to A8. When the input terminal OE is "0", the data in the memory area specified by the RAS addresses RA0 to RA8 and the CAS addresses A0 to A7 specified by the input terminals A0 to A8 at the falling edge of the CAS signal CAS, It outputs to CPU3 via data bus AD0-AD7.

When the input terminal WR is “0”, the data D0 to D7 on the data buses AD0 to AD7 output from the CPU 3 are written in the designated memory area. On the other hand, in the cycle in which the CAS signal CAS remains "1" and only the last signal RAS falls to "0", the memory areas of the refresh addresses FA0 to FA8 designated by the input terminals A0 to A7 are refreshed (RAS only. Refresh).

Next, the overall operation of the circuit will be described with reference to the D-RAM access time chart of FIG. First, at the time of refreshing, the count value counted up by the rising of the last clock signal RCL K output from the control circuit 2 is output as the refresh address FA0 to FA8 from the counter 5 and the flip-flop F / F8. It At this time, since the read / write signal R / W output from the control circuit 2 is "0", the first selector 6 and the third selector 9 set the refresh addresses FA0 to FA8 as RAS addresses RA0 to RA8. Output.

Since the cache address signal CADR output from the control circuit 2 is “0”, the second selector 7 and the fourth selector 10 output the RAS addresses RA0 to RA8 as the memory addresses MA0 to MA8. To do. Then, the D-RAMs 11 and 12 refresh the memory area specified by the memory addresses MA0 to MA8 at the fall of the last signal RAS output from the control circuit 2.

Next, during D-RAM read, the lower addresses AD0 to AD7 (b) output from the CPU 3 are latched by the latch circuit 4 at the falling edge of the ALE signal output from the CPU 3, and the addresses A0 to A7 are read. Is output as. Then, since the read / write signal R / W output from the control circuit 2 becomes "1", the outputs of the first selector 6 and the third selector 9 are from the refresh addresses FA0 to FA8 and the addresses A0 to FA8. It switches to A7 and P0. At this time, the second selector 7 and the fourth selector 10 output the addresses A0 to A7 and P0 as the memory addresses MA0 to MA8 because the cache address signal CADR output from the control circuit 2 is "0". .. Then, at the fall of the last signal RAS output from the control circuit 2, the D-RAMs 11 and 12 determine the RAS address.

Next, in the second selector 7 and the fourth selector 10, since the cache address signal CADR output from the control circuit 2 becomes “1”, the RAS address RA0 to RA8 changes to the CAS address CA0 to CA8. The CAS address is fixed to the D-RAMs 11 and 12 at the falling edge of the CAS signal CAS output from the control circuit 2 by switching and outputting. When the read signal RD output from the CPU 3 is "0", the D-RAMs 11 and 12 output the data D0 to D7 of the designated memory area to the CPU 3 via the data buses AD0 to AD7. Similarly, at the time of D-RAM write, when the write signal WR output from the CPU 3 is "0", the D-RAMs 11 and 12 store the data D0 to D7 on the data buses AD0 to AD7 in the designated memory area. Write.

Next, a bank switching method of the D-RAM will be described with reference to FIG. 2 and Table 1. First, FIG. 2 is a memory map of this embodiment and shows an example in which a 64K.times.8-bit memory area is divided into four banks # 0 to # 3 and set. The address of the D-RAM corresponding to each bank is as shown in the memory map of FIG. 2, and the correspondence between the port P0 signals and P1 output from the CPU3 and the banks # 0 to # 3 is as follows. It is set as shown in Table 1.

[Table 1]

The state of the port P0 signal is output from the fourth selector 10 as the RAS address RA8, and the state of the port P1 signal is output from the fourth selector 10 as the CAS address CA8. As a result, the RAS address RA8 and the CAS address CA8, which are the most significant bits in the memory map of FIG. 2, are controlled and divided into banks # 0 to # 3. The timing of each signal is as shown in FIG. In this way, banks # 0 to # 3 are switched by controlling the upper bit address of the D-RAM.

[0042]

[Effect of the device]

 As described above, according to the present invention, since the memory banks are switched by controlling the upper bit address of the D-RAM, the memory capacity per bank can be increased. For example, 512K × 8 bits, 1M It becomes possible to easily add a large capacity D-RAM such as × 8 bits. Therefore, it is possible to configure the D-RAM with only two chips or to eliminate the need for providing a circuit for generating the CAS signal CAS for bank switching, and to use a large-capacity D-RAM. In addition to making it possible, the number of parts and mounting space can be minimized.

[Brief description of drawings]

FIG. 1 is a block diagram of a D-RAM access circuit showing an embodiment of the present invention.

FIG. 2 is a memory map of this embodiment.

FIG. 3 is a block diagram of a conventional D-RAM access circuit.

FIG. 4 is a conventional memory map diagram.

FIG. 5 is an access time chart of D-RAM.

[Explanation of symbols]

2 control circuit 3 CPU 4 latch circuit 5 counter 6 first selector 7 second selector 8 flip-flop 9 third selector 10 fourth selector 11, 12 D
-RAM RA0-RA7 Last address MA0-MA7
Memory address AD0 to AD7 Data bus FA8 Refresh address

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor ▲ Yoshi ▼ Kotaro Mura 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (1)

[Scope of utility model registration request] 1. A circuit in which a memory bank of a D-RAM is switched by an 8-bit CPU, and the D-RAM is controlled by generating and outputting various signals as a reference of circuit operation. A control circuit, a counter for counting the refresh address of the D-RAM, a selection circuit for selecting the refresh address, the last address RAS, and the CAS address CAS, and a high-order address signal "" of the CAS address CAS. 1 ”and“ 0 ”states and the last address RAS
Switching between the memory banks of the D-RAM by selecting the "1" and "0" states of the upper address signal in the D-RAM. circuit.