JPH05190379A - Capacitance adjustment of laminated capacitor - Google Patents

Capacitance adjustment of laminated capacitor

Info

Publication number
JPH05190379A
JPH05190379A JP4002965A JP296592A JPH05190379A JP H05190379 A JPH05190379 A JP H05190379A JP 4002965 A JP4002965 A JP 4002965A JP 296592 A JP296592 A JP 296592A JP H05190379 A JPH05190379 A JP H05190379A
Authority
JP
Japan
Prior art keywords
capacitance
laminated
electrode
dielectric
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4002965A
Other languages
Japanese (ja)
Inventor
Hisao Yuasa
久夫 湯浅
Hideo Nozu
秀雄 野津
Tetsuhiro Shioda
哲寛 塩田
Katsuhiko Hashimoto
克彦 橋本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP4002965A priority Critical patent/JPH05190379A/en
Publication of JPH05190379A publication Critical patent/JPH05190379A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To raise environment resistance and to reduce the number of manufacturing processes of a laminated capacitor. CONSTITUTION:A lamination adding part 4 constituted by alternately laminating capacitance adjustment adding electrodes 6 and a dielectric body internal part is integrally provided on the outer layer of a laminated body 3 consisting of a dielectric body 1 and an internal electrode 2, and the adding electrode 6 is buried between dielectric bodies 7 and 1 in the entire laminate body including the lamination adding part 4. A laminated capacitor having a portion facing the internal electrode 2 through only the dielectric bodies 7 and 1 is provided, and the lamination adding part 4 of the laminated capacitor is ground parallel to the laminated surface so as to delete a specified number of adding electrodes 6, thus capacitance is adjusted.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、積層コンデンサにおけ
る容量調整方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitance adjusting method for a multilayer capacitor.

【0002】[0002]

【従来の技術】積層コンデンサの容量調整方法として
は、従来、図6に示すようなものが知られている。同図
の(A)は縦断面図、(B)は平面図である。
2. Description of the Related Art As a method for adjusting the capacitance of a multilayer capacitor, the one shown in FIG. 6 is conventionally known. In the figure, (A) is a longitudinal sectional view and (B) is a plan view.

【0003】まず、積層コンデンサとして、誘電体21
と内部電極22とを交互に積層してなる積層体23の積
層上面もしくは下面に、容量調整用電極24を設けたも
のを形成しておく。そして、この容量調整用電極24を
サンドブラストもしくはレーザ照射により削ることによ
り、容量の調整を行う。なお、図中、符号25は外部電
極である。
First, a dielectric 21 is used as a multilayer capacitor.
The capacitor 23 is formed by alternately stacking the internal electrode 22 and the internal electrode 22, and the capacitance adjusting electrode 24 is formed on the upper surface or the lower surface of the stacked body 23. Then, the capacitance adjustment electrode 24 is ground by sandblasting or laser irradiation to adjust the capacitance. In the figure, reference numeral 25 is an external electrode.

【0004】[0004]

【発明が解決しようとする課題】ところで、従来の積層
コンデンサの容量調整方法では、容量調整用電極24が
外部に露出しているので、耐環境性に問題があり、湿気
の影響でマイグレーションが発生したり、フラッシュオ
ーバーが起きたりする。
By the way, in the conventional method for adjusting the capacitance of the multilayer capacitor, since the capacitance adjusting electrode 24 is exposed to the outside, there is a problem in environment resistance and migration occurs due to the influence of moisture. Or a flashover occurs.

【0005】そして、マイグレーション等の不具合を防
止するためには、容量調整の後に絶縁加工する必要があ
り、そのため、加工工程が多く、コスト高になるという
問題がある。
In order to prevent problems such as migration, it is necessary to perform insulation processing after the capacitance adjustment, which results in many processing steps and high cost.

【0006】本発明は、上記の従来の問題に鑑み、積層
コンデンサの耐環境性を高め信頼性を向上させるととも
に、製造の工程数を削減してコストの低減を図ることが
できる積層コンデンサの容量調整方法を提供することを
課題とする。
In view of the above-mentioned conventional problems, the present invention improves the environment resistance and reliability of the multilayer capacitor, reduces the number of manufacturing steps, and reduces the cost of the multilayer capacitor. It is an object to provide an adjustment method.

【0007】[0007]

【課題を解決するための手段】本発明は、上記の課題を
達成するために、次のようにして積層コンデンサの容量
調整方法を構成した。すなわち、誘電体と内部電極とか
らなる積層体の外層に積層付加部を一体に設け、積層付
加部は、容量調整用の付加電極と誘電体とが交互に積層
されたものであり、付加電極は積層付加部を含む積層体
全体の内部で誘電体間に埋設されて、誘電体のみを介し
て内部電極と対向する部分を有するものである積層コン
デンサを用意し、この積層コンデンサの積層付加部を積
層面と平行に研磨して所要枚数の付加電極を削除するも
のである。
In order to achieve the above object, the present invention has a method for adjusting the capacitance of a multilayer capacitor as follows. That is, a laminated addition portion is integrally provided on an outer layer of a laminated body including a dielectric and an internal electrode, and the laminated addition portion is formed by alternately laminating additional electrodes for capacitance adjustment and dielectrics. Is a multilayer capacitor that is embedded between the dielectrics inside the entire laminated body including the laminated addition portion and has a portion facing the internal electrode through only the dielectric, and the laminated addition portion of this laminated capacitor is prepared. Is polished parallel to the laminated surface to remove the required number of additional electrodes.

【0008】[0008]

【作用】上記構成の積層コンデンサの容量調整方法で
は、容量調整前には付加電極が外部に露出しないばかり
でなく、容量調整後も、表層側の付加電極が削除されて
その内側の誘電体が露出するだけで、内層側の付加電極
が露出することはなく、容量調整用の電極(付加電極)
を別工程で絶縁する必要がない。
In the method of adjusting the capacitance of the multilayer capacitor having the above structure, not only the additional electrode is not exposed to the outside before the capacitance adjustment, but also after the capacitance adjustment, the additional electrode on the surface layer side is removed and the dielectric inside the electrode is removed. The electrode for capacitance adjustment (additional electrode) does not expose the additional electrode on the inner layer side only by exposing it.
Does not need to be insulated in a separate process.

【0009】[0009]

【実施例】以下、本発明の詳細を図示の実施例に基づい
て説明する。図1は、本発明の第1実施例の容量調整方
法に用いられる積層コンデンサを示し、(A)はその容
量調整前の縦断面図、(B)はその平面図、(C)は容
量調整後の縦断面図、(D)はその平面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments. 1A and 1B show a multilayer capacitor used in a capacitance adjusting method according to a first embodiment of the present invention. FIG. 1A is a vertical sectional view before the capacitance adjustment, FIG. 1B is a plan view thereof, and FIG. A later vertical sectional view, (D) is a plan view thereof.

【0010】図1の(A),(B)に示すように、この
積層コンデンサは、誘電体1と内部電極2とを交互に積
層してなる積層体3の外層に、積層付加部4を一体に設
けたものである。積層付加部4を含めた積層体全体の左
右両端には、それぞれ外部電極5,5’が設けられ、積
層体3内の各内部電極2は交互に左右の外部電極5,
5’に接続されている。
As shown in FIGS. 1A and 1B, in this multilayer capacitor, a stacking addition portion 4 is provided on the outer layer of a stacking body 3 in which dielectrics 1 and internal electrodes 2 are stacked alternately. It is provided integrally. External electrodes 5 and 5 ′ are provided on both left and right ends of the entire laminated body including the laminated body adding portion 4, and each internal electrode 2 in the laminated body 3 is alternately arranged on the left and right external electrodes 5.
It is connected to 5 '.

【0011】積層付加部4は、容量調整用の付加電極6
と誘電体7とが交互に積層されたもので、付加電極6を
誘電体7(もしくは1)の間に埋設する形で、積層体3
に積層一体化されている。付加電極6は、通常、複数
枚、この実施例では3枚の付加電極6があって、いずれ
も一方の外部電極5に接続されている。これらの付加電
極6は、表層のものほど、他方の外部電極5’の側に長
く延出しており、これによって、いずれの付加電極6
も、他方の外部電極5’に接続された内部電極2と誘電
体7,1のみを介して対向する部分を有し、該内部電極
2との間で対向部分に応じた容量を生じるようになって
いる。図1の(A)に即して言えば、内層の付加電極6
はE1の部分で、また中間層の付加電極6はE2の部分
で、表層の付加電極6はE3の部分で、それぞれ直近の
内部電極2と対向している。
The stacking addition section 4 includes an additional electrode 6 for adjusting the capacitance.
And the dielectric 7 are alternately laminated, and the additional electrode 6 is embedded between the dielectrics 7 (or 1) to form the laminated body 3
It is laminated and integrated. There are usually a plurality of additional electrodes 6, three additional electrodes 6 in this embodiment, all of which are connected to one external electrode 5. These additional electrodes 6 extend to the side of the other external electrode 5 ′ toward the surface layer so that any of the additional electrodes 6 can be extended.
Also has a portion facing the internal electrode 2 connected to the other external electrode 5 ′ via only the dielectrics 7 and 1, so that a capacitance corresponding to the facing portion is generated between the internal electrode 2 and the internal electrode 2. Is becoming According to FIG. 1A, the additional electrode 6 in the inner layer
Is the portion of E 1 , the additional electrode 6 of the intermediate layer is the portion of E 2 , and the additional electrode 6 of the surface layer is the portion of E 3 , which faces the nearest internal electrode 2.

【0012】このように、容量調整前の状態では、容量
調整用の付加電極6は、誘電体7の間に埋設されてい
て、外部には露出していない。
As described above, in the state before the capacitance adjustment, the additional electrode 6 for capacitance adjustment is buried between the dielectrics 7 and is not exposed to the outside.

【0013】次に、容量調整方法を説明する。容量調整
は、図1の(A)(B)に示した未調整の積層コンデン
サについて行うのであって、その積層付加部4を積層面
と平行に、外層側からいずれかの内層の誘電体7,1ま
で研磨して所要枚数の付加電極6を削除する。図示の例
では、外から2層目の誘電体7まで研磨して、表層の付
加電極6を削除し、(C)(D)に示すような調整済み
の積層コンデンサを得ている。この容量調整では、表層
の付加電極6が削除されることで、その付加電極6のE
3の部分に対応する容量分だけ、全体の容量が減少す
る。
Next, a capacity adjusting method will be described. Capacitance adjustment is performed on the unadjusted multilayer capacitor shown in FIGS. 1A and 1B, and the stacking addition portion 4 is parallel to the stacking surface, and the dielectric 7 of any inner layer from the outer layer side. , 1 is removed and the required number of additional electrodes 6 are removed. In the illustrated example, the second layer dielectric 7 is ground from the outside, the additional electrode 6 on the surface layer is removed, and an adjusted multilayer capacitor as shown in (C) and (D) is obtained. In this capacitance adjustment, by removing the additional electrode 6 on the surface layer, E of the additional electrode 6 is removed.
The total capacity is reduced by the capacity corresponding to the part of 3 .

【0014】図2は、本発明の第2実施例の容量調整方
法に用いられる積層コンデンサを示し、(A)はその容
量調整前の縦断面図、(B)はその平面図、(C)は容
量調整後の縦断面図、(D)はその平面図である。
2A and 2B show a multilayer capacitor used in a capacitance adjusting method according to a second embodiment of the present invention. FIG. 2A is a vertical sectional view before the capacitance adjustment, FIG. 2B is its plan view, and FIG. Is a vertical sectional view after capacity adjustment, and (D) is a plan view thereof.

【0015】この積層コンデンサが、誘電体1と内部電
極2とからなる積層体3の外層に、容量調整用の付加電
極6と誘電体7とを交互に積層してなる積層付加部4を
積層一体化したものである点は、第1実施例のものと同
じで、第1実施例のものと対応する部分には同一の符号
を付している。
In this laminated capacitor, a laminated addition portion 4 formed by alternately laminating an additional electrode 6 for capacitance adjustment and a dielectric 7 is laminated on an outer layer of a laminated body 3 composed of a dielectric 1 and an internal electrode 2. The point of being integrated is the same as that of the first embodiment, and the portions corresponding to those of the first embodiment are designated by the same reference numerals.

【0016】この実施例の積層コンデンサが第1実施例
と異なる点は、付加電極6の形成の仕方にある。すなわ
ち、付加電極6は、いずれも一方の外部電極5に接続さ
れているが、図2の(B)に示すように、積層体3の幅
に比べ細幅で、それぞれ他の付加電極6と互いに異なる
幅位置に形成されており、これによって、いずれの付加
電極6も、他方の外部電極5’に接続された内部電極2
と誘電体7,1のみを介して対向し、該内部電極2との
間で容量を生じるようになっている。
The multilayer capacitor of this embodiment is different from that of the first embodiment in the way of forming the additional electrode 6. That is, although each of the additional electrodes 6 is connected to one of the external electrodes 5, as shown in FIG. 2B, the additional electrode 6 has a width narrower than that of the laminated body 3 and is different from that of each of the other additional electrodes 6. The additional electrodes 6 are formed at different width positions from each other, so that any of the additional electrodes 6 is connected to the other external electrode 5 '.
Are opposed to each other via only the dielectrics 7 and 1, and a capacitance is generated between the internal electrodes 2 and.

【0017】この第2実施例の積層コンデンサにおける
容量調整方法は、第1実施例の場合と同様であって、図
2の(A)(B)に示した未調整の積層コンデンサの積
層付加部4を積層面と平行に、外層側からいずれかの内
層の誘電体7,1まで研磨して所要枚数の付加電極6を
削除する。図示の例では、外から2層目の誘電体7まで
研磨して、表層の付加電極6を削除し、(C)(D)に
示すような調整済みの積層コンデンサを得ている。この
容量調整では、表層の付加電極6に対応する容量分だ
け、全体の容量が減少する。
The capacitance adjusting method in the multilayer capacitor of the second embodiment is the same as that of the first embodiment, and the lamination adding portion of the unadjusted multilayer capacitor shown in FIGS. 2A and 2B. 4 is polished in parallel with the laminated surface from the outer layer side to any of the inner layer dielectrics 7 and 1 to remove the required number of additional electrodes 6. In the illustrated example, the second layer dielectric 7 is ground from the outside, the additional electrode 6 on the surface layer is removed, and an adjusted multilayer capacitor as shown in (C) and (D) is obtained. In this capacitance adjustment, the overall capacitance is reduced by the amount corresponding to the additional electrode 6 on the surface layer.

【0018】図3は、本発明の第3実施例の容量調整方
法に用いられる積層コンデンサを示し、(A)はその容
量調整前の縦断面図、(B)はその平面図、(C)は容
量調整後の縦断面図、(D)はその平面図である。
FIG. 3 shows a multilayer capacitor used in a capacitance adjusting method according to a third embodiment of the present invention. (A) is a longitudinal sectional view before the capacitance adjustment, (B) is a plan view thereof, and (C). Is a vertical sectional view after capacity adjustment, and (D) is a plan view thereof.

【0019】この第3実施例の積層コンデンサは、基本
的には第1および第2実施例と同様に、積層体3の外層
に積層付加部4を設けたものであるが、積層体3と積層
付加部4のそれぞれの内部構成が第1および第2実施例
とは異なる。すなわち、この実施例の積層体3では、外
部電極5,5’に接続された内部電極2と、いずれの外
部電極5,5’にも接続されない中間の内部電極2Aと
が誘電体1を間にして積層されている。また、積層付加
部4では、容量調整用の付加電極6Aが、いずれの外部
電極5,5’にも接続されない中間電極の形で、誘電体
7と交互に積層されている。
The multilayer capacitor of the third embodiment is basically the same as the first and second embodiments except that the lamination addition portion 4 is provided on the outer layer of the lamination body 3. The internal structure of each stacking addition unit 4 is different from that of the first and second embodiments. That is, in the laminated body 3 of this embodiment, the inner electrode 2 connected to the outer electrodes 5, 5'and the intermediate inner electrode 2A not connected to any of the outer electrodes 5, 5'interpose the dielectric 1 between them. Are stacked. Further, in the stacking addition portion 4, the additional electrode 6A for capacitance adjustment is stacked alternately with the dielectric 7 in the form of an intermediate electrode which is not connected to any of the external electrodes 5 and 5 '.

【0020】そして、中間電極としての付加電極6A
は、表層のものほど、両外部電極5,5’の間に長く広
がっており、これによって、いずれの付加電極6Aも、
外部電極5,5’に接続された内部電極2と誘電体7,
1のみを介して対向する部分を有しており、該内部電極
2との間で対向部分に応じた中間容量を生じるようにな
っている。
The additional electrode 6A as an intermediate electrode
Of the surface layer, the longer it spreads between the outer electrodes 5 and 5 ′, so that any additional electrode 6 A is
The internal electrode 2 and the dielectric 7, which are connected to the external electrodes 5 and 5 ',
It has a portion facing each other via only 1 and produces an intermediate capacitance corresponding to the facing portion with the internal electrode 2.

【0021】この第3実施例の積層コンデンサにおける
容量調整方法は、第1実施例や第2実施例の場合と同様
であって、図2の(A)(B)に示した未調整の積層コ
ンデンサの積層付加部4を積層面と平行に、外層側から
いずれかの内層の誘電体7,1まで研磨して所要枚数の
付加電極6Aを削除する。図示の例では、外から2層目
の誘電体7まで研磨して、表層の付加電極6Aを削除
し、(C)(D)に示すような調整済みの積層コンデン
サを得ている。この容量調整では、両外部電極5,5’
にそれぞれ接続された一対の内部電極2,2の間に、表
層の付加電極6Aが介在しないことになって、その中間
容量分だけ全体の容量が減少する。
The capacitance adjusting method in the multilayer capacitor of the third embodiment is the same as that of the first and second embodiments, and the unadjusted multilayer shown in FIGS. 2A and 2B is used. The laminated addition portion 4 of the capacitor is polished in parallel with the laminated surface from the outer layer side to any one of the inner layer dielectrics 7 and 1 to remove the required number of additional electrodes 6A. In the illustrated example, the second layer dielectric 7 is polished from the outside, the additional electrode 6A on the surface layer is removed, and an adjusted multilayer capacitor as shown in (C) and (D) is obtained. In this capacitance adjustment, both external electrodes 5, 5 '
Since the additional electrode 6A on the surface layer is not interposed between the pair of internal electrodes 2 and 2 respectively connected to, the total capacitance is reduced by the intermediate capacitance.

【0022】図4は、本発明の第4実施例の容量調整方
法に用いられる積層コンデンサの容量調整前の状態を示
す縦断面図である。この実施例のように、積層付加部4
は、誘電体1と内部電極2とからなる積層体3の上下両
外層に、それぞれ設けてもよい。この例では、積層体3
の内部電極2は、第1もしくは第2実施例におけるよう
に、いずれも外部電極5,5’に接続され、各積層付加
部4の付加電極6も、いずれか一方の外部電極5
(5’)に接続されている。
FIG. 4 is a longitudinal sectional view showing a state before the capacitance adjustment of the multilayer capacitor used in the capacitance adjusting method of the fourth embodiment of the present invention. As in this embodiment, the laminating unit 4
May be provided in both upper and lower outer layers of the laminated body 3 including the dielectric 1 and the internal electrode 2. In this example, the stack 3
The internal electrodes 2 are both connected to the external electrodes 5 and 5'as in the first or second embodiment, and the additional electrode 6 of each laminated additional portion 4 is also connected to either one of the external electrodes 5.
It is connected to (5 ').

【0023】図5は、本発明の第5実施例の容量調整方
法に用いられる積層コンデンサの容量調整前の状態を示
す縦断面図である。この実施例では、第3実施例におけ
るように中間の内部電極2Aを有する積層体3の上下両
外層に、いずれの外部電極5,5’にも接続されない付
加電極6Aを有する積層付加部4を設けている。
FIG. 5 is a longitudinal sectional view showing a state before the capacitance adjustment of the multilayer capacitor used in the capacitance adjusting method of the fifth embodiment of the present invention. In this embodiment, as in the third embodiment, the stacking addition portion 4 having the additional electrode 6A which is not connected to any of the outer electrodes 5 and 5'is provided on both upper and lower outer layers of the stack 3 having the intermediate inner electrode 2A. It is provided.

【0024】上記の第4もしくは第5実施例に用いられ
る積層コンデンサでの容量調整方法は、第1実施例や第
2実施例の場合と特に異なるわけではなく、積層体3の
上下各外層で、それぞれの積層付加部4を積層面と平行
に研磨して所要枚数の付加電極6(6A)を削除すれば
よい。
The method of adjusting the capacitance in the multilayer capacitor used in the above-mentioned fourth or fifth embodiment is not particularly different from the case of the first or second embodiment, and the upper and lower outer layers of the laminated body 3 are the same. It is sufficient to grind each of the laminated addition portions 4 in parallel with the laminated surface and remove the required number of additional electrodes 6 (6A).

【0025】[0025]

【発明の効果】以上詳述したように、本発明によれば、
容量の調整前も調整後も、容量調整用の付加電極が誘電
体の間に埋設されていて、従来の積層コンデンサの容量
調整方法のように容量調整用電極が外部に露出しないか
ら、耐環境性に優れ、信頼性が向上する。
As described in detail above, according to the present invention,
Before and after the capacitance is adjusted, the additional electrode for capacitance adjustment is embedded between the dielectrics, and the capacitance adjustment electrode is not exposed to the outside like the conventional capacitance adjustment method of a multilayer capacitor. Excellent in reliability and improved in reliability.

【0026】また、容量調整用の付加電極が外部に露出
しないことから、事後の絶縁加工が不要となり、製造工
程が簡略化する。
Further, since the additional electrode for adjusting the capacitance is not exposed to the outside, the subsequent insulation processing is unnecessary, and the manufacturing process is simplified.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例に用いられる積層コンデン
サ、およびその容量調整方法を示し、(A)はその容量
調整前の縦断面図、(B)はその平面図、(C)は容量
調整後の縦断面図、(D)はその平面図である。
1A and 1B show a multilayer capacitor used in a first embodiment of the present invention and a method for adjusting the capacitance thereof, where FIG. 1A is a longitudinal sectional view before the capacitance adjustment, FIG. 1B is a plan view thereof, and FIG. A vertical cross-sectional view after capacity adjustment, (D) is a plan view thereof.

【図2】本発明の第2実施例に用いられる積層コンデン
サ、およびその容量調整方法を示し、(A)はその容量
調整前の縦断面図、(B)はその平面図、(C)は容量
調整後の縦断面図、(D)はその平面図である。
2A and 2B show a multilayer capacitor used in a second embodiment of the present invention and a method for adjusting the capacity thereof, where FIG. 2A is a longitudinal sectional view before adjusting the capacity, FIG. 2B is its plan view, and FIG. A vertical cross-sectional view after capacity adjustment, (D) is a plan view thereof.

【図3】本発明の第3実施例に用いられる積層コンデン
サ、およびその容量調整方法を示し、(A)はその容量
調整前の縦断面図、(B)はその平面図、(C)は容量
調整後の縦断面図、(D)はその平面図である。
3A and 3B show a multilayer capacitor used in a third embodiment of the present invention and a method of adjusting the capacitance thereof, where FIG. 3A is a vertical sectional view before the capacitance adjustment, FIG. 3B is its plan view, and FIG. A vertical cross-sectional view after capacity adjustment, (D) is a plan view thereof.

【図4】本発明の第4実施例に用いられる積層コンデン
サ、およびその容量調整方法を示す縦断面図で、容量調
整前の状態を示す。
FIG. 4 is a vertical sectional view showing a multilayer capacitor used in a fourth embodiment of the present invention and a capacitance adjusting method thereof, showing a state before capacitance adjustment.

【図5】本発明の第5実施例に用いられる積層コンデン
サ、およびその容量調整方法を示す縦断面図で、容量調
整前の状態を示す。
FIG. 5 is a vertical sectional view showing a multilayer capacitor used in a fifth embodiment of the present invention and a capacitance adjusting method thereof, showing a state before capacitance adjustment.

【図6】従来の積層コンデンサの容量調整方法を示し、
(A)は縦断面図、(B)はその平面図である。
FIG. 6 shows a method of adjusting the capacitance of a conventional multilayer capacitor,
(A) is a longitudinal sectional view and (B) is a plan view thereof.

【符号の説明】[Explanation of symbols]

1 誘電体 2 内部電極 2A 内部電極(中間電極) 3 積層体 4 積層付加部 6 付加電極 6A 付加電極(中間電極) 7 誘電体 DESCRIPTION OF SYMBOLS 1 Dielectric 2 Internal electrode 2A Internal electrode (intermediate electrode) 3 Laminated body 4 Laminated addition part 6 Additional electrode 6A Additional electrode (intermediate electrode) 7 Dielectric

フロントページの続き (72)発明者 橋本 克彦 京都府長岡京市天神二丁目26番10号 株式 会社村田製作所内Front page continuation (72) Inventor Katsuhiko Hashimoto 2-10-10 Tenjin, Nagaokakyo-shi, Kyoto Murata Manufacturing Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 誘電体(1)と内部電極(2)とからな
る積層体(3)の外層に積層付加部(4)を一体に設
け、この積層付加部(4)は、容量調整用の付加電極
(6)と誘電体(7)とが交互に積層されたものであ
り、付加電極(6)は、積層付加部(4)を含む積層体
全体の内部で誘電体(7,1)間に埋設されて、誘電体
(7,1)のみを介して内部電極(2)と対向する部分
を有するものである容量調整型コンデンサを用意し、こ
の積層コンデンサの積層付加部(4)を積層面と平行に
研磨して所要枚数の付加電極(6)を削除することを特
徴とする積層コンデンサの容量調整方法。
1. A stacking addition part (4) is integrally provided on an outer layer of a stacking body (3) comprising a dielectric (1) and an internal electrode (2), and the stacking addition part (4) is for capacity adjustment. The additional electrodes (6) and the dielectrics (7) are alternately laminated, and the additional electrodes (6) are disposed inside the entire laminated body including the laminated addition portion (4). ), A capacitance adjustment type capacitor having a portion facing the internal electrode (2) via only the dielectric (7, 1) is prepared, and a laminated addition portion (4) of this laminated capacitor is prepared. A method for adjusting the capacitance of a multilayer capacitor, characterized in that the required number of additional electrodes (6) are removed by polishing in parallel with the laminated surface.
JP4002965A 1992-01-10 1992-01-10 Capacitance adjustment of laminated capacitor Pending JPH05190379A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4002965A JPH05190379A (en) 1992-01-10 1992-01-10 Capacitance adjustment of laminated capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4002965A JPH05190379A (en) 1992-01-10 1992-01-10 Capacitance adjustment of laminated capacitor

Publications (1)

Publication Number Publication Date
JPH05190379A true JPH05190379A (en) 1993-07-30

Family

ID=11544083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4002965A Pending JPH05190379A (en) 1992-01-10 1992-01-10 Capacitance adjustment of laminated capacitor

Country Status (1)

Country Link
JP (1) JPH05190379A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162063A (en) * 1995-12-13 1997-06-20 Matsushita Electric Ind Co Ltd Layered ceramic capacitor
EP0860842A1 (en) * 1997-02-24 1998-08-26 Taiyo Yuden Co., Ltd. Laminated capacitor and trimming method thereof
US7394646B2 (en) * 2005-03-28 2008-07-01 Tdk Corporation Laminated ceramic electronic component
JP2010034308A (en) * 2008-07-29 2010-02-12 Tdk Corp Multilayer capacitor
JP2019050468A (en) * 2017-09-08 2019-03-28 株式会社村田製作所 Multilayer resonance circuit component, packaged multilayer resonance circuit component, and method of manufacturing multilayer resonance circuit component

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09162063A (en) * 1995-12-13 1997-06-20 Matsushita Electric Ind Co Ltd Layered ceramic capacitor
EP0860842A1 (en) * 1997-02-24 1998-08-26 Taiyo Yuden Co., Ltd. Laminated capacitor and trimming method thereof
JPH10241991A (en) * 1997-02-24 1998-09-11 Taiyo Yuden Co Ltd Laminated capacitor and its trimming method
US6069786A (en) * 1997-02-24 2000-05-30 Taiyo Yuden Co., Ltd. Laminated capacitor and trimming method thereof
US7394646B2 (en) * 2005-03-28 2008-07-01 Tdk Corporation Laminated ceramic electronic component
JP2010034308A (en) * 2008-07-29 2010-02-12 Tdk Corp Multilayer capacitor
JP2019050468A (en) * 2017-09-08 2019-03-28 株式会社村田製作所 Multilayer resonance circuit component, packaged multilayer resonance circuit component, and method of manufacturing multilayer resonance circuit component
US10594288B2 (en) 2017-09-08 2020-03-17 Murata Manufacturing Co., Ltd. Multilayer resonant circuit component, packaged multilayer resonant circuit component, and multilayer resonant circuit component manufacturing method

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