JPH05189366A - Channel request prioirity judging circuit - Google Patents

Abstract

PURPOSE:To shorten time for waiting for a data transfer request so as to pre vent a retrial caused by overrunning and to improve the throughput of an input/ output controller by detecting a channel which is necessary to be operated in high speed and increasing the priority of the data transfer request from the channel. CONSTITUTION:In the input/output controller where plural channels are connected, the priority is put in the order of the short interval of the reuest by counters a4, b5 and c6 counting the interval of the transfer requests from the channels a1, b2 and c3 connected with a peripheral controller, registers a7, b8 and c9 storing the request interval of each channel and a request interval comparing circuit 10 comparing the request interval.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel request priority determination circuit in an input / output control device to which a plurality of channels are connected, and more particularly to data from a channel controlling a peripheral device in an input / output control unit of an information processing device. The present invention relates to a channel request priority determination circuit having a transfer request priority determination function.

[0002]

2. Description of the Related Art A conventional priority determination circuit employs a method of fixing the priority order of channels in the order of channel numbers and processing a data transfer request, or a method of changing the priority order of each channel in order.

[0003]

In the above-mentioned conventional priority determination circuit, the priority order is fixed or is changed at regular time intervals regardless of the operating conditions of the peripheral devices connected to the channel. However, when the number of channels increases, there is a problem that the waiting time until a request is accepted becomes long even in a channel that requires a high data transfer rate, and the data transfer capability is reduced as a whole.

[0004]

SUMMARY OF THE INVENTION A channel request priority determination circuit of the present invention is for an input / output control device to which a plurality of channels are connected, and which corresponds to a plurality of channels for measuring intervals of data transfer requests from the channels. A counter,
A first request interval register corresponding to a plurality of channels, which stores the value of this counter, and a first request interval register corresponding to each channel.
According to the request interval comparison circuit that compares the value of the request interval register of each channel and outputs the priority of each channel, and the priority of each channel output from this request interval comparison circuit, It has a channel request control circuit for selecting a high data transfer request. A channel request priority determination circuit according to another invention of the present invention is
In the above, a plurality of second request interval registers for storing intervals of past data transfer requests, and a plurality of channels corresponding to a plurality of channels for calculating the values of the plurality of second request interval registers. It has an arithmetic unit and a request interval comparison circuit for determining the priority of the next data transfer request from the arithmetic result of the arithmetic unit corresponding to each channel. A channel request priority determination circuit according to yet another invention of the present invention is the same as the first invention, except that the counter and the request interval comparison circuit are replaced by the type of the next data transfer request based on the content of the data transfer request from the channel. And a priority prediction circuit corresponding to a channel for predicting the priority and a priority for determining a high-priority data transfer request from the data transfer requests of the respective channels based on the priority of each channel determined by the priority prediction circuit. It has a degree determination circuit.

[0005]

In the present invention, the priority of the next request is determined from the data transfer request interval or the type of data transfer request for each channel.

[0006]

1 is a block diagram showing an embodiment of the present invention, showing an embodiment of the first invention. In FIG. 1, reference numerals 1, 2, and 3 denote a channel a, a channel b, and a channel c, to which peripheral control devices are connected, respectively, counters a, b, and c, which are channel a1, channel c. It is a counter corresponding to a channel for measuring the interval of data transfer requests from b2 and channel c3. 7, 8, and 9 are registers a, b, and c
These are counter a4, counter b5, counter c
A request interval register corresponding to a channel that stores the value of 6 is configured. Reference numeral 10 denotes a request interval comparison circuit that compares the values of the request interval registers corresponding to the respective channels and outputs the priority of each channel. Reference numeral 11 denotes each channel according to the priority of each channel output from the request interval comparison circuit 10. It is a channel request control circuit that selects a data transfer request having a high priority from the data transfer requests.

Next, the operation of the embodiment shown in FIG. 1 will be described. First, the channel a1 is the data transfer request a1.
2 is output to the channel request control circuit 11. The counter a4 sets the normal counter value a15 to "1" at regular intervals.
Add one by one. Here, when the data transfer request a12 is input, the register a7 stores the value of the counter value a15 and outputs it to the request interval value a18, and the counter a
The counter value a15 output by 4 is set to "0". Then, channel b2, counter b5, register b
8 and channel c3, counter c6, register c9 operate similarly.

Next, the request interval value a18, the request interval value b19, and the request interval value c20 output from the register a7, the register b8, and the register c9 are input to the request interval comparison circuit 10, and the requests are output in ascending order (requests are issued). The priority order of each channel is determined in the order from the shortest time until the next request is issued), and the priority order information 21 is output. Then, the channel request control circuit 11 uses the channels a1, b2, and c.
Among the data transfer requests output from 3, the accept signal a22,
Either the accept signal b23 or the accept signal c24 is output to start data transfer.

Here, it is assumed that the request interval value a18, the request interval value b19, and the request interval value c20 output from the register a7, the register b8, and the register c9 are "30", "20", and "50", respectively. At this point, the priority of each channel is channel b2> channel a1>
It is the channel c3. Further, the values of the counter a4, the counter b5, and the counter c6 are “20”, “40”,
It is "30". Here, channel a1 and channel b2
Simultaneously outputs the data transfer request a12 and the data transfer request b13, the channel request control circuit 11 outputs the accept signal b23 to the channel b2 according to the above priority order, and the data transfer of the channel b2 is started. After that, the accept signal a22 is output to the channel a1 and data transfer is performed. At this point, the values of the request interval value a18, the request interval value b19, and the request interval value c20 output from the register a7, the register b8, and the register c9 are “35”, “40”, and
Set to "50". At this point, the priority of each channel is channel a1> channel b2> channel c3.

Here, again, channel a1 and channel b
When 2 simultaneously outputs the data transfer request a12 and the data transfer request b13, the channel request control circuit 11 outputs the accept signal a22 to the channel a1 according to the above priority order, and the data transfer of the channel a1 is started.

FIG. 2 is a block diagram showing another embodiment of the present invention, showing an embodiment of the second invention. This Figure 2
, 25, 26 and 27 are channels a, b, c and 2 to which peripheral control devices are respectively connected.
8, 29, 30 are counter a, counter b, counter c
Is. Reference numerals 32, 34 and 36 are primary registers a, primary registers b and primary registers c, 31, 33 and 35 are secondary registers a, secondary registers b and secondary registers c. A plurality of request interval registers for storing transfer request intervals are configured. 37,
Reference numerals 38 and 39 denote arithmetic units a, b and c, respectively, which are arithmetic units corresponding to a plurality of channels for arithmetically operating the values of a plurality of request interval registers (31 to 36). Four
Reference numeral 0 is a request interval comparison circuit that determines the priority of the next data transfer request from the calculation results of the arithmetic units 37 to 39 corresponding to each channel, and 41 is a channel request control circuit.

Next, the operation of the embodiment shown in FIG. 2 will be described. First, the channel a25 is the data transfer request a.
42 is output to the channel request control circuit 41. The counter a28 is reset to "0" by the data transfer request a42. At this time, the counter a28
Is output from the primary register a32.
Memorized in. At this time, the request interval value a49 output from the primary register a32 is the secondary register a31.
Memorized in. Here, the request interval value a49 output from the primary register a32 and the previous request interval value a48 output from the secondary register a31 are input to the calculator a37, and the average value is output to the request interval average value a54. Then, the channel b26, the counter b29, the primary register b34, the secondary register b33, the request interval average value b55 and the channel c27, the counter b30, 1
The next register b36, the secondary register b35, and the request interval average value c56 operate similarly.

Next, the request interval comparison circuit 40 compares the values of the request interval average values a54, b55, and c56, in ascending order of values (in order from the time when a request is issued to the time when the next request is issued, in ascending order). ), The priority order is determined, and the priority order information 57 is output. Then, the channel request control circuit 41 uses the channels a25 and b.
26, the accept signal a58, the accept signal b59, or the accept signal c60 is output to the channel having the highest priority from the data transfer requests output from the channel 26 and the channel c27 to start the data transfer.

FIG. 3 is a block diagram showing still another embodiment of the present invention, showing an embodiment of the third invention. In FIG. 3, 61, 62 and 63 are channels a, b, and c to which peripheral control devices are connected, respectively, 64, 65 and 66 are types of the next data transfer request based on the contents of the data transfer request from the channel. Of the channel-based priority predicting circuits a, b, c, 67, 68 and 69 for predicting the priority and the priorities of the channels are determined by the register a, the register b and the registers c and 70, respectively. Reference numeral 71 denotes a channel request control circuit, which determines a high-priority data transfer request from the data transfer requests of each channel according to the channel priority.

Next, the operation of the embodiment shown in FIG. 3 will be described. First, the channel a61 is the data transfer request a.
72 is output to the channel request control circuit 71. The priority prediction circuit a64 predicts the priority of the next data transfer from the data transfer request a72, and outputs the predicted value a75. The register a67 stores this predicted value a75,
The priority signal a78 is output. And channel b6
2. The priority prediction circuit b65, the register b68, the channel c63, the priority prediction circuit c66, and the register c69 operate in the same manner.

Next, register a67 and register b6
8, the priority signal a78, the priority signal b79, and the priority signal c80 output from the register c69 are the priority determination circuit 70.
Entered in. The priority determination circuit 70 uses the priority signal a
The values of 78, the priority signal b79, and the priority signal c80 are compared, the priority order is determined in descending order of priority, and the priority order information 81 is output. The channel request control circuit 71 uses the channels a61, b62, and c6.
The accept signal a82, the accept signal b83, and the accept signal c are assigned to the channel having the highest priority among the channels issuing the data transfer request among the three.
Any one of 84 is output to start data transfer.

Here, the value of the predicted value output by the priority prediction circuit for the content of the request output by the channel is set as follows. (1) When the request is “start / during data transfer”, it can be expected that the next data transfer request will be output immediately thereafter, so the predicted value is set to “1”. (2) If the request is "end of data transfer (during input / output processing)", it can be expected that the next data transfer request will be output relatively early, so the predicted value is "2".
And (3) When the request is “end of data transfer (end of input / output processing)”, the next request can be expected to be “transfer of end report”, and the time until data transfer may be long Therefore, the predicted value is set to "3". (4) When the request is “transfer of end report”, it means that a series of input / output processing from the central processing unit has ended, and it can be predicted that it will take a considerable time until the next request arrives, so the predicted value is set to “4”. To do.

At this time, register a67 and register b
68, the priority signal a78, the priority signal b79, and the priority signal c80 output from the register c69 are "3", "4", and "1", respectively, and the channel a61, the channel b62, and the channel c63 is data transfer request a72 and data transfer request b7 at the same time
3. It is assumed that the data transfer request c74 is output. Since the priority determination circuit 70 outputs the priority of each channel from the priority signal of each channel as channel c63> channel a61> channel b62 to the priority information 81, the channel request control circuit 71 has the highest priority. The accept signal c84 is output to the channel c63.

At this time, the priority prediction circuit a6
4, the priority prediction circuit b65, the priority prediction circuit c66 fetches the request of each channel, and the priority signal a78,
The priority signal b79 and the priority signal c80 are output and stored in the register a67, the register b68, and the register c69, and the priority of the next request is set.

[0020]

As described above, according to the present invention, the priority of the next request is determined based on the data transfer request interval or the type of data transfer request for each channel. By determining and raising the priority, the waiting time of the data transfer request can be reduced and the occurrence rate of retries due to command overrun / data overrun can be reduced. Therefore, there is an effect that the throughput of the entire input / output control unit can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing another embodiment of the present invention.

FIG. 3 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

1-3 channels a, b, c 4-6 counters a, b, c 7-9 registers a, b, c (request interval register) 10 request interval comparison circuit 11 channel request control circuit 31, 33, 35 secondary register (Request interval register) 32, 34, 36 Primary register (Request interval register) 37-39 Operation unit a, b, c 40 Request interval comparison circuit 64-66 Priority prediction circuit a, b, c 70 Priority determination circuit

Claims (3)

[Claims] 1. An input / output control device to which a plurality of channels are connected, a counter corresponding to a plurality of channels for measuring an interval between data transfer requests from the channels, and a plurality of channels corresponding to the values of the counters. Of the first request interval register and the request interval comparison circuit for comparing the values of the first request interval register corresponding to each channel and outputting the priority order of each channel, and for each channel output from this request interval comparison circuit. A channel request priority determination circuit having a channel request control circuit for selecting a data transfer request having a high priority from data transfer requests of respective channels according to a priority. 2. The channel request priority determination circuit according to claim 1, wherein a plurality of second request interval registers for storing an interval of past data transfer requests and a plurality of second request intervals. The present invention is characterized by having a plurality of channel-corresponding arithmetic units for calculating register values and a request interval comparison circuit for determining the priority of the next data transfer request from the arithmetic results of the respective channel-corresponding arithmetic units. Channel request priority judgment circuit. 3. The channel request priority determination circuit according to claim 1, wherein the type of the next data transfer request is predicted from the contents of the data transfer request from the channel instead of the counter and the request interval comparison circuit, and the priority is set. A priority predicting circuit corresponding to a channel to be determined, and a priority determining circuit for determining a data transfer request having a high priority from the data transfer requests of the respective channels based on the priority of each channel determined by the priority predicting circuit. Channel request priority determination circuit characterized by.