JP2000122963A - Interruption controller and interruption control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change the priority of an interruption request to CPU in accordance with the operation state of a system and to simplify a control processing. SOLUTION: Plural interruption request signals S1-S6 and a status signal S7 showing the operation state of CPU 2 are inputted to an interruption controller 1. The priority of the interruption request signals inputted by the interruption request mask registers 3 and 4 is decided. The outputs of the interruption request mask registers 3 and 4, the status signal and the inversed signal are inputted to AND gates 6-9, the outputs of the interruption request mask registers 3 and 4 are switched in accordance with the status signal S7 and an interruption request output signal is inputted to CPU 2 from OR gates 10 and 11. CPU 2 executes a processing from the interruption cause of the higher priority.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device and a method for controlling an interrupt to a CPU in an information processing apparatus.

[0002]

2. Description of the Related Art In an information processing apparatus, interrupt control is generally used to control processing items that occur irregularly, such as DMA transfer, which operate independently of a CPU. This is to accept a processing request when necessary, as compared to the control for constantly monitoring the state, and thus to reduce the load on the CPU. Accordingly, there are many cases where there are a plurality of interrupt factors to be controlled.

Since each of these interrupt causes independently generates an interrupt request, a plurality of interrupt requests may be simultaneously generated. For this reason, a priority is assigned to each interrupt factor, and when interrupt requests overlap, processing is performed sequentially from the one with the highest priority. The priority of this interrupt factor is usually fixed in many cases.

[0004] Here, each interrupt request does not always occur at the same frequency, and also varies depending on the operation state of the system. Then, in a specific operation situation, it may be necessary to prioritize an interrupt factor having a lower priority. In such a case, such interrupt requests are prohibited so that interrupt factors with higher priority do not enter, so that interrupt factors with lower priority to be processed can be preferentially processed.

In such a case, with respect to the interrupt factor for which the interrupt request is prohibited, the status is monitored sequentially so that the interruption of the interrupt process does not occur. It takes a complicated procedure such as performing a process when it becomes a state.

[0006]

Since the conventional interrupt control is performed as described above, the priorities of the interrupt requests cannot be changed according to the operation state of the system, which results in a complicated control process. However, there is a problem that the processing speed is reduced.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and can change the priority of an interrupt request according to the operation state of the system, thereby simplifying the control processing. It is an object of the present invention to provide an interrupt control device and an interrupt control method capable of improving the processing speed of a CPU.

[0008]

An interrupt control apparatus and an interrupt control method according to the present invention are configured as follows.

(1) An interrupt control device for receiving a plurality of interrupt requests and notifying the central processing unit of the plurality of interrupt requests, wherein a plurality of priorities are determined for each of the plurality of input interrupt requests for each arbitrary group. And priority switching means for switching these priority determining means according to the operation state of the central processing unit.

(2) In the configuration of (1), a plurality of operating states of the central processing unit are identified and a plurality of priority order determining means are switched.

(3) In the configuration of the above (1) or (2), the priority determining means is constituted by an interrupt mask register, and the priority switching means is constituted by an AND gate.

(4) An interrupt control method for receiving a plurality of interrupt requests and notifying the central processing unit of the interrupt request, wherein priorities are determined for each of the plurality of input interrupt requests for each arbitrary group, and the priorities are determined. The determined interrupt request of each group is switched according to the operation state of the central processing unit.

(5) In the configuration of (4), a plurality of operating states of the central processing unit are identified, and the interrupt request of each group is switched.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an interrupt controller (control device) that manages an interrupt request and notifies the CPU (central processing unit) 2 of the interrupt request.
2. Input ports INT1 and I of two interrupt request signals
NT2 is present, input port INT1 is I
The priority is higher than NT2.

Reference numerals 3 and 4 denote interrupt request mask registers for permitting and prohibiting notification of the plurality of interrupt request signals S1 to S6 received by the interrupt request input unit to the CPU 2, and a plurality of interrupt factor registers respectively received for each group. First priority determining means and second priority determining means for setting the priority order. That is, the interrupt request mask register 3 stores the input port A,
In response to the interrupt request signals S1 to S3 input to B and C, only those signals for which interrupt requests are permitted are output from the Q terminal, and the interrupt request mask register 4 stores the input ports A, B and C In response to the interrupt request signals S4 to S6 input to the CPU, only those signals for which interrupt requests are permitted are output from the Q terminal.

Reference numeral 5 denotes an inverter for inverting a status signal S7 indicating an operation state of a system (information processing apparatus system) in which the interrupt controller 1 is mounted. The status signal S7 is a state information input unit for knowing the operation state of the CPU 2. Accepted at Reference numerals 6, 7, 8 and 9 denote AND gates 10 and 1 which constitute priority order switching means for switching between the two interrupt request mask registers 3 and 4 as the above-mentioned priority order determining means according to the status signal S7.
An OR gate 1 causes the CPU 2 to input the interrupt request output signals S8 and S9.

In the above configuration, when a plurality of interrupt requests occur simultaneously, the CPU 2 processes the interrupt factors according to the above-mentioned priorities. The interrupt controller 1 outputs two interrupt request output signals S8 and S9 to the input ports INT1 and INT2 of the CPU 2. At this time, the interrupt controller 1 has six interrupt request signals S1 to S6 which are equal to or more than the two interrupt request signals of the input ports INT1 and INT2 of the CPU 2.
To three.

The AND gate 6 receives the output of the interrupt request mask register 3 and the status signal S7, and
The ND gate 7 receives the output of the interrupt request mask register 3 and the output of the inverter 5 which is obtained by inverting the status signal S7. Therefore, when the status signal 3 is "High", the interrupt request of the interrupt request signals S1, S2, and S3 via the interrupt request mask register 3 is output from the AND gate 6, and the status signal S7 is "Low".
In this case, the interrupt request is output from the AND gate 7.

On the other hand, the AND gate 9 receives the output of the interrupt request mask register 4 and the status signal S7, and
The ND gate 8 receives the output of the interrupt request mask register 4 and the output of the inverter 5 obtained by inverting the status signal S7. Therefore, as described above, when the status signal S7 is "High", the interrupt request mask register 4
Are output from the AND gate 9, and when the status signal S7 is "Low", the interrupt request is AND
Output from the gate 8.

The output of the AND gate 6 and the output of the AND gate 8 are input to the OR gate 10, and the output is input to the input port IN of the CPU 2 as an interrupt request output signal S8.
Input to T1. The output of the AND gate 7 and the output of the AND gate 9 are input to the OR gate 11, and the output is input to the input port INT2 of the CPU 2 as an interrupt request output signal S9.

That is, depending on the status of the status signal S7, one of the combination of the AND gate 6 and the AND gate 9 or the combination of the AND gate 7 and the AND gate 8 becomes valid. The CPU 2 preferentially processes the interrupt request of the input port INT1, but the interrupt source to be processed is not fixed, but the interrupt request signals S1, S2, S3, S4, and S4 depending on the status of the status signal S7.
S5 and S6 are interchanged.

As described above, it becomes possible for the interrupt controller 1 to instantaneously change the priority of the processing of the interrupt factor in accordance with the state of the system, so that the control processing can be simplified and the generation of the interrupt request can be achieved. This leads to an improvement in the processing speed of the CPU 2 and efficient use of CPU resources.

This embodiment is merely an example, and does not limit the number of interrupt request signals and the number of status signals for changing the priority of interrupt request signals. That is, the state information input unit can identify a plurality of operation states of the CPU 2, and also has a plurality of priority order determining means, and the priority order switching means switches the plurality of priority order determining means based on the information of the state information input unit. It is also possible to switch.

In this embodiment, the means for changing the priority order when the CPU 2 has a plurality of interrupt request signals has been described. However, a vector system indicating a jump destination address when an interrupt occurs may be used.

[0026]

As described above, according to the present invention,
The priority order of the interrupt request can be changed according to the operation state of the system, the control processing can be simplified, and the processing speed of the CPU can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

[Description of Signs] 1 interrupt controller 2 CPU (central processing unit) 3 interrupt request mask register (first priority determination means) 4 interrupt request mask register (second priority determination means) 5 inverter 6 AND gate (priority) 7 AND gate (priority switching means) 8 AND gate (priority switching means) 9 AND gate (priority switching means) 10 OR gate 11 OR gate

Claims (5)

[Claims] 1. An interrupt control device for receiving a plurality of interrupt requests and notifying a central processing unit of a plurality of interrupt requests, wherein a plurality of priority order determining means for determining a priority order for each of the plurality of input interrupt requests for an arbitrary group. And a priority switching means for switching these priority determining means according to the operation state of the central processing unit. 2. The interrupt control device according to claim 1, wherein a plurality of operation states of the central processing unit are identified and a plurality of priority order determination means are switched. 3. The interrupt control device according to claim 1, wherein said priority order determining means comprises an interrupt mask register, and said priority order switching means comprises an AND gate. 4. An interrupt control method for receiving a plurality of interrupt requests and notifying the central processing unit of the interrupt request, wherein priorities of input interrupt requests are determined for each arbitrary group, and the priorities are determined. Wherein the interrupt request of each group is switched according to the operation state of the central processing unit. 5. The interrupt control method according to claim 4, wherein a plurality of operating states of the central processing unit are identified and an interrupt request of each group is switched.