JPH05183421A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To suppress the fluctuation of a power supply voltage without reducing the operating speed by interposing a MOS transistor(TR) receiving a drain voltage to its gate and receiving an output of a gate circuit via an inverter between a charging side of the logic gate circuit and a gate and between the discharge side and ground respectively. CONSTITUTION:When the rising of the input to a CMOS inverter 2 is started, a PMOS transistor(TR) P0 is turned OFF from ON and an NMOS TR N0 is turned ON from OFF. Since a 1st NMOS TR N1 receives a gate at its own drain side voltage, the NMOS TR N1 is turned on and since a 2nd NMOS TR N2 receives an output of the CMOS inverter 2 at its gate via an inverter 6, the NMOS TR N2 is turned off. Thus, the stored charge at the inverter side is discharged to a GND side via the NMOS TRs N1, N2 and the potential is rapidly decreased. Since the potential at the drain side of the TR N1 is higher than the GND by the threshold level VTHN of the NMOS TR N1, the potential is rapidly decreased up to the level VTHN. On the other hand, the drain voltage of the NMOS TR N1 is decreased up to the GND.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit,
In particular, logic gate circuits (NOT, AND, OR, NAN
It is possible to suppress fluctuations in the power supply voltage that occur when switching a large number of bits at the same time without lowering the switching speed of D, NOR, etc.).

[0002]

2. Description of the Related Art For example, a NAN forming a semiconductor integrated circuit
It is desirable that a logic gate circuit such as a D circuit or a NOR circuit be as small as possible and operate at high speed.
Along with the improvement of fine processing technology and the like, there is a tendency that the number of bits and the speed of semiconductor integrated circuits have increased in recent years.

[0003]

However, as the number of bits and the speed of the semiconductor integrated circuit increase, the problem that the power supply voltage fluctuates when a large number of bits are simultaneously switched occurs. In order to solve such a problem, conventionally, the amplitude of the fluctuation of the power supply voltage is inversely proportional to the rise time and the fall time of the signal.Therefore, delay the rise time or fall time of the transistor in the final output stage. However, this has a drawback that the speed is lowered and the characteristics are deteriorated.

The present invention has been made by paying attention to the unsolved problem in the prior art as described above, and provides a semiconductor circuit capable of suppressing the fluctuation of the power supply voltage without causing a decrease in speed or the like. The purpose is to

[0005]

In order to achieve the above object, a semiconductor circuit according to the present invention has a first gate having its drain voltage supplied between a charging side of a logic gate circuit and a power supply. And a second P-channel MOS transistor whose gate is supplied with the output of the logic gate circuit through an inverter, in parallel, and between the discharge side of the logic gate circuit and ground. A first N-channel MOS transistor whose gate is supplied with its own drain voltage and a second N-channel MOS transistor whose gate is supplied with the output of the logic gate circuit through an inverter. It was

According to a second aspect of the present invention, in addition to the first aspect of the invention, the driving power of the first P-channel MOS transistor and the first N-channel MOS transistor is large, and the second P-channel MOS transistor is large. Also, the driving power of the second N-channel MOS transistor is reduced.

[0007]

When the output of the logic gate circuit rises from "L" to "H", the output side of the logic gate circuit and the power supply are connected and charging is performed. Is still low, the gate voltage of the second P-channel MOS transistor (hereinafter referred to as PMOS transistor) whose output is supplied through the inverter is at “H” level, and the second PMOS transistor is Since it is in the off state, charging is performed only through the first PMOS transistor.

However, the first PMOS transistor is
Since its drain is supplied to its gate, the output of the logic gate circuit is lower than the power supply voltage V _CC by the threshold value V _THP of the first PMOS transistor (V _CC -V _THP ). Is only charged until. Then, when the output of the logic gate circuit becomes high, this time the second PM
Since the OS transistor is turned on, the charge side of the logic gate circuit is connected to the power supply through the second PMOS transistor, and when the second PMOS transistor is turned on, the gate voltage of the first PMOS transistor becomes high. Since the first PMOS transistor of the lever is turned off, the output side of the logic gate circuit is charged by the second P transistor.
This is done only via MOS transistors.

At this time, the second PMOS transistor is
Since the output of the logic gate circuit is supplied through the inverter, it constitutes a positive feedback circuit and is used in the saturation region. The output side of the logic gate circuit is charged to the power supply voltage V _CC . On the other hand, when the output of the logic gate circuit falls from "H" to "L", the output side of the logic gate circuit is connected to the ground to discharge, contrary to the rising time. , When the output of the logic gate circuit is still high, the output of the second N-channel MOS transistor (hereinafter referred to as N
It is a MOS transistor. The gate voltage of) is "L" and the second NMOS transistor is in the off state, so that discharging is performed only through the first NMOS transistor.

However, the first NMOS transistor is
Since its gate is supplied with its own drain voltage, the output of the logic gate circuit is discharged only up to the threshold value V _THN of the first NMOS transistor. And
When the output of the logic gate circuit becomes low, this time the second N
Since the MOS transistor is turned on, the discharge side of the logic gate circuit is connected to the ground via the second NMOS transistor, and when the second NMOS transistor is turned on, the gate voltage of the first NMOS transistor becomes low. Since the first NMOS transistor is turned off, discharge on the output side of the logic gate circuit is performed only through the second NMOS transistor.

At this time, the second NMOS transistor is
Since the output of the logic gate circuit is supplied through the inverter, it constitutes a positive feedback circuit, so it is used in the saturation region, and the output side of the logic gate circuit drops to the ground level. That is, according to the invention of claim 1, when the output of the logic gate circuit rises, first,
Via the first PMOS transistor (V _CC -V _THP ).
Is charged up to the power supply voltage V _CC through the second PMOS transistor, and then, when the output of the logic gate circuit falls, first, it is discharged up to V _THN through the first NMOS transistor. And then the second
Is discharged to the ground level through the NMOS transistor of.

Therefore, as in the second aspect of the present invention, the driving force of the first PMOS transistor and the second NMOS transistor is increased (for example, the channel width W and the channel width W of the first PMOS transistor and the first NMOS transistor are increased). Increase the ratio W / L of the channel length L) to the second P
If the driving force of the MOS transistor and the second NMOS transistor is made small (for example, the ratio W / L of the channel width W and the channel length L of the second PMOS transistor and the second NMOS transistor is made small), charging and discharging can be performed. From the start to the time when the second PMOS transistor or the second NMOS transistor is turned on, charging and discharging are performed at high speed, and after the second PMOS transistor or the second NMOS transistor is turned on, , Charging and discharging are performed at low speed.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention, in which a semiconductor circuit according to the present invention is applied to a signal output device 1 of a semiconductor integrated circuit. First, the configuration will be described. This signal output device 1 has a CMOS inverter 2 as a logic gate circuit, the input side of the CMOS inverter 2 is connected to a signal output line 3 of a semiconductor integrated circuit, and the output of the CMOS inverter 2 is output. The side is connected to the output pad 4.

The source of the PMOS transistor P ₀ on the charging side which constitutes the CMOS inverter 2,
A first PMOS transistor P ₁ and a second PMOS transistor P ₂ are interposed in parallel with the power source V _CC, and C
NMOS as discharge side that constitutes MOS inverter 2
The first NMOS transistor N ₁ and the second NMOS transistor N ₂ are interposed in parallel between the source of the transistor N ₀ and the ground GND.

[0015] The first gate of the PMOS transistor P _1, the first drain voltage of the PMOS transistor P ₁ is supplied to the second gate of the PMOS transistor P _2, the output of the CMOS inverter 2 is the driving force Is supplied via a small inverter 5. In addition, the gate of the first NMOS transistor N ₁ has its first N
The drain voltage of the MOS transistor N ₁ is supplied, and the gate of the _second NMOS transistor N ₂ has a CMOS
The output of the inverter 2 is supplied via the inverter 6 having a small driving force.

Then, the first PMOS transistor P ₁
The first NMOS transistor N ₁ is a transistor having a large ratio W / L of the channel width W and the channel length L (large driving force), and the second PMOS transistor P _{2 and} the second PMOS transistor P ₂ Is a transistor having a small ratio (W / L) of the channel width W and the channel length L.

Next, the operation of this embodiment will be described. Figure 2
1A to 1F are waveform diagrams showing waveforms at points a to f in FIG. 1, respectively, where point a is the input side of the CMOS inverter 2, point b is the output side of the CMOS inverter 2, and point c is the The output side of the inverter 5, the point d is the output side of the inverter 6, the point e is the drain side of the first PMOS transistor P ₁ , and the point f is the drain side of the first NMOS transistor N ₁ .

That is, when the input to the CMOS inverter 2 starts to rise at time t ₁ (see FIG. 2A), the PMOS transistor P ₀ shifts from the on state to the off state, and the NMOS transistor N ₀ turns off. To the ON state. At this time, the potential of the drain side of the first NMOS transistor N ₁ is supplied to the gate, so that the first NMOS transistor N ₁ is in the ON state, and the second NMOS transistor N ₂ receives the output of the CMOS inverter 2 at its gate. Since it is supplied through the inverter 6, it is in the off state.

Therefore, the charges accumulated on the output side of the CMOS inverter 2 are grounded through the NMOS transistor N ₀ and the first NMOS transistor N _1.
However, since the first NMOS transistor N ₁ is a transistor having a large driving force, the potential on the output side of the CMOS inverter 2 drops relatively steeply (FIG. 2).
(See (b)).

[0020] However, the drain side of the potential of the first NMOS transistor N ₁ at this time, since the first voltage drop at the NMOS transistor N ₁ is generated, by the amount of the threshold V _THN of the NMOS transistor N ₁ , Showing a potential higher than the ground GND level (see FIG. 2 (f)).
Therefore, the potential on the output side of the CMOS inverter 2 drops sharply until the threshold value V _THN is reached (until time t ₂ is reached) (see FIG. 2B). ..

On the other hand, when the potential on the output side of the CMOS inverter 2 drops, the output of the inverter 6 rises, so that the gate voltage of the _second NMOS transistor N ₂ becomes high (see FIG. 2 (d)), and the second thereof. NMOS transistor N ₂ of the first N
The drain voltage of the MOS transistor N ₁ drops (see FIG. 2 (f)), but with the drop of the drain voltage of the first NMOS transistor N ₁ , the potential on the output side of the CMOS inverter 2 further drops, and Since the positive feedback that the output of the inverter 6 further rises is formed, the drain voltage of the _first NMOS transistor N ₁ is eventually grounded.
It drops to the ND level (see FIG. 2F), and the potential on the output side of the CMOS inverter 2 also drops to the ground GND level (see FIG. 2B).

Then, the first NMOS transistor N ₁
When the drain voltage of the first NMOS transistor N ₁ drops, the first NMOS transistor N ₁ shifts from the on state to the off state.
The discharge on the output side of the CMOS inverter 2 between the times t ₂ and t ₃ is relatively gentle because it is performed only through the _second NMOS transistor N ₂ having a small driving force (see FIG. See b)).

Also, like the inverter 6, the inverter 5
2 also rises (see FIG. 2C), the second PMOS transistor P ₂ whose output is supplied to the gate of the inverter 5 shifts from the ON state to the OFF state, whereby the first PMOS transistor P ₂ is turned off. since P ₁ is changed from the oFF state to the oN state, the potential of the first drain side of the PMOS transistor P ₁ becomes a low value by the threshold V _THP of the PMOS transistors P ₁ than the power supply V _CC level (Fig. 2 (e)).

From this state, when the input to the CMOS inverter 2 starts to fall at time t ₄ (see FIG. 2A), the PMOS transistor P ₀ shifts from the off state to the on state. Then, the NMOS transistor N ₀ shifts from the on state to the off state. At this time, the potential of the drain side of the first PMOS transistor P ₁ is supplied to the gate, so that the first PMOS transistor P ₁ is in the ON state, and the second PMOS transistor P ₂ receives the output of the CMOS inverter 2 at its gate. Since it is supplied through the inverter 5, it is in the off state.

Therefore, the output side of the CMOS inverter 2 is charged through the first PMOS transistor P ₁ and the PMOS transistor P ₀ , but since the first PMOS transistor P ₁ is a transistor having a large driving force, the CMOS inverter The potential on the output side of 2 rises relatively steeply (see FIG. 2B). However, the first
As described above, the drain side potential of the PMOS transistor P ₁ of the PMOS transistor P ₁ is equal to the threshold value V of the PMOS transistor N ₁ .
_The potential is lower than the power supply V _CC level by the amount of _THP (see FIG. 2E).

Therefore, the potential on the output side of the CMOS inverter 2 sharply rises until the threshold value V _THP is reached (until time t ₅ is reached) (FIG. 2 (b)). )reference). On the other hand, when the potential on the output side of the CMOS inverter 2 rises, the output of the inverter 5 falls, so the gate voltage of the _second PMOS transistor P ₂ becomes low (see FIG. 2C), and the second PMOS Although the transistor P ₂ shifts from the off state to the on state and the drain voltage of the _first PMOS transistor P ₁ rises (see FIG. 2E), the first PMOS transistor P 1
_As the drain voltage of ₁ rises, the potential on the output side of the CMOS inverter 2 further rises, and then the output of the inverter 5 further drops, forming positive feedback, so that the first PMOS transistor P ₁ The drain voltage rises to the power supply V _CC level (see FIG. 2 (f)), and CMO
The potential on the output side of the S inverter 2 also rises to the power supply V _CC level (see FIG. 2B).

Then, the first PMOS transistor P ₁
When the drain voltage of the first PMOS transistor P ₁ rises, the first PMOS transistor P ₁ shifts from the on state to the off state.
The charging of the output side of the CMOS inverter 2 between times t ₅ and t ₆ is performed relatively slowly because it is performed only through the _second PMOS transistor P ₂ having a small driving force (see FIG. See b)).

Also, like the inverter 5, the inverter 6
2 rises (see FIG. 2 (d)), the second NMOS transistor N ₂ whose output is supplied to the gate of the inverter 6 shifts from the ON state to the OFF state, whereby the first NMOS transistor N ₂ is turned off. Since N ₁ shifts from the off state to the on state, the drain side potential of the first NMOS transistor N ₁ becomes the threshold value V _THN (see FIG. 2 (f)).

That is, the output of the CMOS inverter 2 is
As is clear from FIG. 2B, which is the waveform diagram, at the time of the fall and rise, a relatively steep change period (t ₁ → t ₂ , t ₄ → t ₅ ) and a relatively gentle change are provided. After changing periods (t ₂ → t ₃ , t ₅ → t ₆ ),
Finally, the power supply V _CC level or the ground GND level is reached.

Since the output voltage of the CMOS inverter 2 has reached the power supply V _CC level or the ground GND level at the end of the abruptly changing period, there is no problem in driving the logic circuit in the next stage. Therefore, the high-speed operation of the CMOS inverter 2 is achieved, and moreover, the final potential is settled after a gradual change period.
The power supply voltage of the power supply line and the ground line due to the switching of the OS inverter 2 is hardly affected.

Therefore, even if a large number of bits are switched at the same time, the fluctuation of the power supply voltage is extremely small, and the malfunction of the logic circuit due to the fluctuation of the power supply voltage is prevented. The output device 1 is suitable as a signal output device for a recent semiconductor integrated circuit, which has been designed to have multiple bits and high speed. In addition, the CMOS inverter 2
Finally, the output of the power supply settles down to the level of the power supply V _CC or the level of the ground GND. Therefore, even if the logic circuit of the next stage is constituted by the CMOS logic, it is possible to prevent a large through current from flowing.

FIG. 3 is a diagram showing a second embodiment of the present invention, in which the present invention is applied to a 2-input NAND circuit 7 as a logic gate circuit. The same components as those of the circuit shown in FIG. 1 are designated by the same reference numerals. That is, this NA
The ND circuit 7 includes two Ps arranged in parallel on the power supply V _CC side.
It is composed of MOS transistors P ₃ and P ₄ and two NMOS transistors N ₃ and N ₄ arranged in series on the ground GND side, and one input A has a PMOS transistor P ₃ and an NMOS transistor N _3. And the other input B is supplied to the gates of the PMOS transistor P ₄ and the NMOS transistor N ₄ ,
The output F is on the drain side of the MOS transistor P ₃ .

The first PMOS transistor P ₁ and the second P transistor P ₁ are connected between the sources of the PMOS transistors P ₃ and P ₄ on the charging side of the NAND circuit 7 and the power supply V _CC.
The MOS transistor P ₂ is provided, and the first NMOS transistor N ₁ and the second NMOS transistor N ₂ are provided between the source of the NMOS transistor N ₄ on the discharge side of the NAND circuit 7 and the ground GND. ing. Other configurations are similar to those of the first embodiment.

With such a structure, when the output F of the NAND circuit 7 changes, it has a relatively steep change period and a relatively gentle change when the output F of the NAND circuit 7 changes due to the same operation as in the first embodiment. through the period, because finally it reaches the power supply V _CC level or ground GND level, as in the first embodiment, together with a high speed operation can be achieved, it is possible to suppress supply voltage.

In each of the above embodiments, the semiconductor circuit according to the present invention is applied to the CMOS inverter 2 or the NAND circuit 7 as a logic gate circuit.
The application target of the present invention is not limited to these,
It may be another logic gate circuit, for example, an OR circuit, an AND circuit, a NOR circuit, or the like.

[0036]

As described above, according to the present invention,
When the output of the logic gate circuit changes, the final level is reached after a relatively steep change period and a relatively gentle change period. While achieving the above, there is an effect that the fluctuation of the power supply voltage can be suppressed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a waveform diagram showing waveforms at points a to f of the circuit shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of a second exemplary embodiment of the present invention.

[Explanation of symbols]

1 Signal Output Device (Semiconductor Circuit) 2 CMOS Inverter (Logic Gate Circuit) 5, 6 Inverter 7 NAND Circuit (Logic Gate Circuit) P ₁ First PMOS Transistor P ₂ Second PMOS Transistor N ₁ First NMOS Transistor N ₂ Second NMOS transistor

Claims (2)

[Claims] 1. A first P having its gate supplied with its own drain voltage between a charge side of a logic gate circuit and a power supply.
A channel MOS transistor and a second P whose gate is supplied with the output of the logic gate circuit through an inverter.
A first N-channel MOS transistor having its gate supplied with its own drain voltage between the discharge side of the logic gate circuit and ground and a logic gate circuit A semiconductor circuit in which a second N-channel MOS transistor whose output is supplied via an inverter is interposed in parallel. 2. The first P-channel MOS transistor and the first N-channel MOS transistor have a large driving force, and the second P-channel MOS transistor and the second N-channel MOS transistor.
The driving force of the channel MOS transistor is small.
The semiconductor circuit described.