JPH05181708A - Cpu monitoring circuit - Google Patents

Abstract

PURPOSE:To enable monitoring a main CPU and sub-CPUs only by the addition of a little firmware processing without increasing the size of a hardware even when the number of sub-CPUs is increased. CONSTITUTION:A CPU monitoring part 4 sends monitoring pulse signals to sub-CPU parts 2, 3 at the same timing to interrupt them. sub-CPU parts 2, 3 inform the generation of the monitoring interruptions to the main CPU part 1. At the time of receiving the generation of the monitoring interruptions, the main CPU part 1 executes the AND operation of respective interruptions generated from the sub-CPU parts 2, 3, and only when the interruptions are received from both of the sub-CPUs 2, 3, inverts the monitoring pulse signal and returns the inverted signal to the CPU monitoring part 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU monitoring circuit, and more particularly to a monitoring system for a CPU unit composed of a plurality of CPUs (central processing units).

[0002]

2. Description of the Related Art Conventionally, in this type of CPU monitoring system, as shown in FIG. 2, when the main CPU unit 5 has one sub CPU unit 2, the monitoring pulse generating circuit 41 of the CPU monitoring unit 4 is used. To the interrupt circuit 22 of the sub CPU unit 2
To the CPU 20 of the sub CPU unit 2 to interrupt the CPU 20 of the sub CPU unit 2.

When the CPU 20 is notified by the interrupt circuit 22 that a monitoring pulse signal has been received, the CPU 20 receives a DPM (dual port memory).
y) Notify that an interrupt has occurred to the interrupt circuit 52 of the main CPU section 5 via 21.

When the CPU 50 of the main CPU unit 5 is notified by the interrupt circuit 52 that a monitoring interrupt has occurred, the CPU 50 of the CPU monitoring unit 4 inverts the monitoring pulse signal from the monitoring pulse generation circuit 41 and outputs the signal from the CPU monitoring unit 4 via the output port 51. Inversion pulse detection circuit 4
Return to 0.

The inverted pulse detection circuit 40 has an output port 51.
When the inverted pulse signal is returned via the
It is confirmed that the PU unit 5 and the sub CPU unit 2 are operating normally.

Further, if the inversion pulse detection circuit 40 does not return the inversion pulse signal via the output port 51 within one cycle of the monitoring pulse signal from the monitoring pulse generating circuit 41, the main CPU section 5 and the sub CPU It is judged as an abnormality of the section 2, and an alarm is given. Here, the normal operation or the abnormal operation of the main CPU unit 5 and the sub CPU unit 2 is notified as a monitoring result of the inversion pulse detection circuit 40.

On the other hand, as shown in FIG. 3, when the main CPU unit 6 has two sub CPU units 2 and 3, the C
The monitoring pulse generation circuits 72 and 73 of the PU monitoring unit 7 send monitoring pulse signals of a fixed cycle to the interrupt circuits 22 and 32 of the sub CPU units 2 and 3, and the CPU 20 of the sub CPU units 2 and 3
Each 30 is independently interrupted.

Each of the CPUs 20 and 30 has an interrupt circuit 22 or 3.
2 notifies that the monitoring pulse signal has been received, the DPM2
The interrupt circuit 62 of the main CPU unit 6 is notified of the occurrence of the monitoring interrupt via 1, 31.

When the CPU 60 of the main CPU unit 6 is notified by the interrupt circuit 62 that a monitoring interrupt has occurred in each of the sub CPU units 2 and 3, the monitoring pulse signals from the monitoring pulse generation circuits 72 and 73 are inverted and output. It is returned to the inverted pulse detection circuits 70 and 71 of the CPU monitoring unit 7 via the port 61 and the signal lines 111 and 112.

When the inverted pulse signal is returned via the output port 61 and the signal lines 111 and 112, the inverted pulse detection circuits 70 and 71 return the main CPU section 6 and the sub CP.
Check that U parts 2 and 3 are operating normally.

Further, the inversion pulse detection circuits 70 and 71 are one of the monitoring pulse signals from the monitoring pulse generation circuits 72 and 73.
If the inverted pulse signal is not returned via the output port 61 and the signal lines 111 and 112 within the cycle, it is determined that the main CPU unit 6 and the sub CPU units 2 and 3 are abnormal,
Notify as an alarm.

The OR circuit 74 ORs the detection results of the inversion pulse detection circuits 70 and 71 and outputs the result as a monitoring result. Therefore, the inverted pulse detection circuits 70 and 71
On the other hand, when an abnormal operation of the main CPU unit 5 and the sub CPU unit 2 is detected, the main CPU unit 6 and the sub CPU units 2 and 3 are notified as an alarm.

In such a conventional CPU monitoring system, when the main CPU unit 6 has a plurality of sub CPU units 2 and 3, the monitoring pulse generating circuit 72, 73 and inverted pulse detection circuits 70 and 7
1 and hardware such as the signal lines 111 and 112 for sending the inverted pulse signal increases.

Further, the CPU 60 of the main CPU section 6 and the CPU 2 of the sub CPU sections 2 and 3 by the interrupt circuit 62.
There is a problem in that processing for interrupts from 0 and 30 must be individually performed, and firmware processing for these processing must be added.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned problems of the conventional ones. Even if the number of sub CPUs increases, the hardware scale is not increased and a small amount of firmware processing is added. Main CPU and Sub C
It is an object of the present invention to provide a CPU monitoring circuit capable of monitoring PU.

[0016]

A CPU monitoring circuit according to the present invention comprises a plurality of sub CPUs for outputting an interrupt signal in response to a monitoring pulse signal sent from each monitoring means, and the interrupt signal from each of the plurality of sub CPUs. C of an information processing system including a main CPU which sends an inverted pulse signal which is the inverted pulse signal to the monitoring means in response to
A PU monitoring circuit, wherein the generating means generates a common monitoring pulse signal for each of the plurality of sub CPUs, and the interrupt signal from each of the plurality of sub CPUs for the common monitoring pulse signal generated by the generating means. And a sending means for sending the inversion pulse signal to the monitoring means according to the result of the calculation by the calculating means.

[0017]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. The figure shows a case where the main CPU unit 1 has two sub CPU units 2 and 3. The monitoring pulse generation circuit 41 of the CPU monitoring unit 4 is a sub C
The monitoring pulse signals at the same timing are sent to the interrupt circuits 22 and 32 of the PU units 2 and 3 to interrupt the CPUs 20 and 30 of the sub CPU units 2 and 3, respectively.

When the CPUs 20 and 30 are notified by the interrupt circuits 22 and 32 that the monitoring pulse signal has been received, the DPM 21 and
The interrupt circuit 12 of the main CPU unit 1 is notified via 31 that a monitoring interrupt has occurred.

When the CPU 10 of the main CPU unit 1 is notified by the interrupt circuit 12 that a monitoring interrupt has occurred, the sub CPU
Takes the AND of interrupts from parts 2 and 3
Only when the interrupts from both units 2 and 3 are received, the supervisory pulse signal from the supervisory pulse generation circuit 41 is inverted, and the inverted pulse detection circuit 40 of the CPU supervisory unit 4 is instructed via the output port 11 and one signal line 101. Send it back. Where CP
In U10, AND of interrupts from each of the sub CPU units 2 and 3 is taken by an AND circuit (not shown) or firmware processing.

The inverted pulse detection circuit 40 has an output port 11
When the inverted pulse signal is returned via the signal line 101, the normal operation of the main CPU unit 1 and the sub CPU units 2 and 3 is confirmed.

For example, for the main CPU unit 1, a sub C
Unless either one of the PU units 2 and 3 is notified of the occurrence of the monitoring interrupt, the monitoring pulse signal is not inverted and returned to the inversion pulse detection circuit 40 of the CPU monitoring unit 4. In this case, the inverted pulse detection circuit 4 of the CPU monitoring unit 4
When 0, the return of the inversion pulse signal cannot be detected within one cycle of the monitor pulse signal from the monitor pulse generating circuit 41, and it is determined that the main CPU unit 1 and the sub CPU units 2 and 3 are abnormal and notified as an alarm. To do.

In this way, from the monitoring pulse generation circuit 41 of the CPU monitoring unit 4 to the interrupt circuit 22 of the sub CPU units 2 and 3,
An AND of interrupts from the CPUs 20 and 30 of the sub CPU units 2 and 3 by a monitor pulse signal of the same timing sent to 32, and a monitor pulse signal only when the interrupts from both sub CPU units 2 and 3 are received. Invert C
By returning the signal to the inverted pulse detection circuit 40 of the PU monitoring unit 4, the inverted pulse signal obtained by inverting the monitoring pulse signal through the single signal line 101 can be transmitted to the CPU monitoring unit 4. Therefore, even if the number of the sub CPU units 2 and 3 increases, the main CPU unit 1 and the sub CPUs 2 and 3 can be monitored by adding a small amount of circuit or firmware processing, and the hardware scale can be reduced or the diversion efficiency can be improved. Can be promoted.

[0024]

As described above, according to the present invention, the logical operation of the interrupt signal from each of the plurality of sub CPUs with respect to the monitoring pulse signal commonly generated in each of the plurality of sub CPUs is performed, and the operation result is obtained. In response to this, by sending an inverted pulse signal to the monitoring means, the sub CPU
There is an effect that the main CPU and the sub CPU can be monitored by adding a small amount of firmware processing without increasing the hardware scale even if the number of CPUs increases.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional example.

FIG. 3 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1 Main CPU 2, 3 Sub CPU 4 CPU Monitoring Unit 10, 20, 30 CPU 12, 22, 32 Interrupt Circuit 40 Inversion Pulse Detection Circuit 41 Monitoring Pulse Generation Circuit

Claims (1)

[Claims] 1. A plurality of sub-Cs, each of which outputs an interrupt signal in response to a monitoring pulse signal sent from the monitoring means.
A CPU monitoring circuit of an information processing system comprising a PU and a main CPU which sends an inverted pulse signal obtained by inverting the monitoring pulse signal to the monitoring means in response to the interrupt signal from each of the plurality of sub CPUs. Generating means for generating a monitoring pulse signal common to each of the plurality of sub CPUs, and operation for performing a logical operation of the interrupt signal from each of the plurality of sub CPUs with respect to the common monitoring pulse signal generated by the generating means A CPU monitoring circuit comprising: means and a sending means for sending the inversion pulse signal to the monitoring means in accordance with a calculation result of the calculating means.