JPH05175238A - Junction type field-effect transistor - Google Patents

Abstract

PURPOSE:To prevent increase of leak current at the time of reversed bias of a gate to a source or a drain when a junction type FET is irradiated with radiation. CONSTITUTION:In a junction type FET which has a source region 4 of a second conductivity type and a drain region 5 of a second conductivity type in a semiconductor layer 3 of a first conductivity type, and has a thermal oxide film 9 and a nitride film 10 as insulating films, high concentration regions 11 and 12 of a second conductivity type are arranged in the source region 4 and the drain region 5, respectively. When positive holes as positive charges are generated in the thermal oxide film by the irradiation of radiation, the high concentration regions 11 and 12 in the source region 4 and the drain region 5 are not inverted, so that increase of leak current at the time of backward bias is restrained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a junction type field effect transistor (hereinafter
Abbreviated as junction type FET).

[0002]

2. Description of the Related Art Conventionally, a junction type FET having radiation resistance of this kind has a thin thermal oxide film and a nitride film of about 100 Å to 300 Å as an insulating film on the surface. Figure 3 shows a conventional bonded FE
FIG. 6A is a plan view and FIG. 6B is a sectional view taken along line CC of FIG. As shown in the figure, an N-type buried layer 2 is selectively formed on the surface of the P-type semiconductor substrate 1.
An N-type epitaxial layer 3 is formed on the P-type semiconductor substrate 1 including. A P-type source region 4 and a P-type drain region 5 are formed on the surface of the N-type epitaxial layer 3 immediately above the N-type buried layer 2. Also, the P-type source region 4
A P-type channel region 6 and an N-type gate region 7 are formed between the and P-type drain regions. The N type gate region 7 is formed around the P type source region 4 and the P type drain region. Furthermore, 100Å-300Å thermal oxide film 9 on the surface
And a nitride film 10 having a thickness of about 1000Å is formed thereon, and the aluminum electrodes 8 connected to the source region, the drain region and the gate region are connected through the contact windows formed in the insulating films 9 and 10. Has been done.

[0003]

In such a conventional junction type FET, the radiation resistance is enhanced by the thermal oxide film 9 and the nitride film 10. However, the holes generated by the irradiation of the radiation are P
There is a problem that a positive charge is captured in the thermal oxide film 9 on the type source region 4, and the effect causes N inversion on the P type source region 4 to increase a leak current when the source and the gate are reverse biased. is there. This also occurs when the drain and gate are reverse biased. An object of the present invention is to provide a junction-type FET that prevents such an increase in leak current when the source or drain and the gate are reverse biased.

[0004]

Junction type FET of the present invention
Has a second-conductivity-type high-concentration region in the second-conductivity-type source / drain regions formed in the first-conductivity-type semiconductor layer. For example, an N-type semiconductor element has P-type source / drain regions, and P-type high-concentration regions are provided in these source / drain regions.

[0005]

[Function] Even if holes are generated as positive charges in the thermal oxide film by irradiation of radiation, the high-concentration regions in the source / drain regions are not inverted, and an increase in leak current during reverse bias is suppressed. To do.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1A and 1B show a junction type FET according to a first embodiment of the present invention. FIG. 1A is a plan view and FIG. 1B is a sectional view taken along line AA. The same parts as those in FIG. 3 are designated by the same reference numerals and detailed description thereof will be omitted. In this structure, as shown in FIG. 1, the high-concentration P-type source region 11 and the high-concentration P-type drain region 12 are formed in the P-type source region 4 and the P-type drain region 5, respectively. The structure is different.

Next, the junction type FET having such a structure
The manufacturing method of is explained. First, the impurity concentration is 10 ¹⁴
An oxide of antimony is selectively deposited on the P-type semiconductor substrate 1 having a size of 10 ¹⁶ cm ^-3 by, for example, a spin coating method, and impurities are diffused from the oxide layer to the surface of the P-type semiconductor substrate 1. An N-type buried layer 2 having a sheet resistance of 20 to 30Ω / □ is formed. Then, the N-type epitaxial layer 3 having an impurity concentration of 10 ¹⁴ to 10 ¹⁶ cm ⁻³ is formed on the P-type semiconductor substrate 1 including the N-type buried layer 2.

Next, for example, Bcl ₃ is selectively diffused on the surface of the N-type epitaxial layer 3 immediately above the N-type buried layer 2 to have a P-type source region 4 having a sheet resistance of 100 to 300Ω / □, The P-type drain region 5 is formed to have a junction depth of about 2 to 3 μm. Then, Bcl ₃ is selectively diffused into the P-type source region 4 and the P-type drain region to reduce the sheet resistance to 20-40Ω.
A P-type high-concentration source region 11 and a P-type high-concentration drain region 12 of / □ are formed with a junction depth of approximately 1 to 2 μm.

Next, a P-type channel region 6 and an N-type gate region 7 are formed between the P-type source region 4 and the P-type drain region 5. The N-type gate region 7 and the P-type source region 4 are
It is formed so as to surround the periphery of the mold drain region 5. Furthermore,
100 on the surface of the N type epitaxial layer 3 including each diffusion region.
A thin thermal oxide film 9 of about 300Å is formed, and a nitride film 10 of about 1000Å is formed thereon. After that, a contact window in each region is opened by using a known photolithography technique to form an aluminum electrode 8.

According to this structure, the P-type source region 4 and the P-type source region
Since the high-concentration P-type source region 11 and the high-concentration P-type drain region 12 are provided in each region of the type drain region 5, holes are generated by irradiation of radiation and are present in the thermal oxide film 9 as positive charges. However, even if the P-type source region 4 and the P-type drain region 5 are N-inverted, they are not N-inverted because the P-type high-concentration regions 11 and 12 are formed in each. As a result, even when the source or drain and the gate are reverse biased, the leak current does not increase.

2A and 2B show a junction type FET according to a second embodiment of the present invention, FIG. 2A is a plan view and FIG. 2B is a sectional view taken along the line BB. 2, the same parts as those in FIG. 1 are designated by the same reference numerals, and the detailed description thereof will be omitted. As shown in FIG. 2, in this embodiment, the high-concentration P-type source region 1 included in the P-type source region 4 and the P-type drain region 5 is used.
1 and the high concentration P-type drain region 12 are formed in an annular shape so as to avoid contact with the aluminum electrode 8 in each region.

Also in this embodiment, holes are generated in the thermal oxide film 9 due to radiation irradiation and exist as positive charges in the thermal oxide film 9 so that the P-type source region 4 and the P-type drain region 5 are inverted in N. Even if it becomes, each P type high concentration region 11,
N-inversion does not occur in the portion 12 and no increase in leak current is observed. Further, in this embodiment, since the P-type high concentration regions 11 and 12 are not in contact with the aluminum electrode 8, the same effect can be obtained without changing the designed contact resistance.

[0013]

As described above, according to the present invention, since the high-concentration region of the same conductivity type as that of the source / drain region is provided in the source / drain region, the thermal oxidation film in the source / drain region is exposed to the radiation. Even if holes are generated in the thermal oxide film and exist as positive charges on the thermal oxide film, the conductivity type of the high-concentration regions in the source and drain regions is not inverted and an increase in leak current during reverse bias can be prevented. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a plan view of a first embodiment of a junction type FET of the present invention and a sectional view taken along the line AA.

FIG. 2 is a plan view of a second embodiment of the present invention and a sectional view taken along line BB thereof.

FIG. 3 is a plan view of a conventional junction type FET and a cross-sectional view taken along the line CC of FIG.

[Explanation of symbols]

 1 P-type semiconductor substrate 2 N-type buried layer 3 N-type epitaxial layer 4 P-type source region 5 P-type drain region 6 P-type channel region 7 N-type gate region 8 Aluminum electrode 9 Thermal oxide film 10 Nitride film 11, 12 High Concentration area

Claims (2)

[Claims] 1. A semiconductor layer of the first conductivity type has a second conductivity type source / drain region, and a channel region of the second conductivity type and a gate region of the first conductivity type between the source and drain regions. And a junction type field effect transistor having a laminated film of a thermal oxide film and a nitride film as an insulating film on the surface, characterized by having a high concentration region of the second conductivity type in the source / drain regions. Effect transistor. 2. An N-type semiconductor device having P-type source / drain regions, a P-type channel region and an N-type gate region between the source / drain regions, and the P-type source / drain regions. The junction field effect transistor according to claim 1, wherein the junction has a P-type high concentration region.