JPH05175229A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To obtain a method for manufacturing an MISFET excellent in driving force while hot carrier resistance is ensured under a low power supply voltage. CONSTITUTION:A gate electrode 4 is formed on a semiconductor substrate 1 via an insulating film 3. After low concentration impurities 5 are introduced in the semiconductor substrate 1, heat treatment is performed in an oxidizing atmosphere, thereby obtaining a gentle impurity profile due to acceleration diffusion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device, especially MI.
The present invention relates to a method for manufacturing an SFET.

[0002]

2. Description of the Related Art As the degree of integration of semiconductor integrated circuits increases, the power consumption per chip tends to increase, so that lower power consumption is required. The gate length of the MISFET used in the chip is 0.5
When the thickness is less than μm, it becomes difficult to secure reliability against hot carriers with the conventional 5V power source.

Due to the demand for low power consumption and ensuring reliability against hot carriers, the power supply voltage of the design rule 0.5 μm or later is finally from 5 V to 3.0 V.
It is lowered to ~ 3.3V. Under a low power supply voltage of 3.0 to 3.3 V, transistor design is required to enhance the driving force of a single MISFET while ensuring reliability against hot carriers.

FIG. 3 shows a conventional MISFET structure which has been used up to the design rule 0.8 μm generation. As the drain structure, a sidewall 1 made of an oxide film or the like is used.
LDD (Lightly Doped D) using 5
A rain: lightly doped drain) structure has been used.

[0005]

However, even if only the gate length is shortened without changing the sidewall length in order to satisfy the speed requirement of the integrated circuit under a low power supply voltage,
There is a problem that the N ⁻ layer (or P ⁻ layer) under the side wall is long and the parasitic resistance in that portion lowers the driving force of the transistor.

In addition, the sidewall length is simply shortened to N
^- Although the driving ability to reduce the parasitic resistance of the layer increases, there is a problem of securing reliability since the deterioration of the transistor characteristics due to hot carriers occurs at low power supply voltage becomes difficult.

Therefore, it is necessary to devise some means in order to increase the driving power of the transistor and to secure the reliability against hot carriers under a low power supply voltage.

[0008]

In order to solve the above problems, the present invention provides a method of manufacturing a MISFET having an LDD structure, which comprises forming a gate electrode on a semiconductor substrate with an insulating film interposed between the gate electrode and the gate electrode. Is used as a mask, and a step of introducing impurities into the semiconductor substrate at a low concentration and a step of performing heat treatment in an oxidizing atmosphere after that are sequentially performed.

[0009]

According to the present invention, since the above-described steps are introduced in the method of manufacturing a semiconductor element, the concentration profile of the low concentration impurity layer, for example, the N ⁻ layer becomes gentle due to the oxidation enhanced diffusion. Therefore, it becomes possible to shorten the sidewall length to obtain a sufficient driving force, and at the same time, to secure the reliability against hot carriers. Therefore, the above problems can be eliminated.

[0010]

1 is a process sectional view showing a manufacturing method according to the present invention, taking an N-channel type MISFET as an example. The steps will be described below.

(A) First, the field oxide film 2 is formed on the P-type substrate 1 to a thickness of about 6000 Å according to a general manufacturing method, and then the gate oxide film 3 is formed to a thickness of about 150 Å.
A gate electrode 4 made of polysilicon is formed on the gate oxide film 3 by a conventional method to a thickness of about 3000 Å, and phosphorus (P ⁺ ) 5 is deposited at 30 K by ion implantation.
Injection is performed under the conditions of eV and 2 to 5 × 10 ¹³ pieces / cm ² .

(B) Next, CVD using TEOS (tetra-ethyl-ortho-silicate) system or the like as a source on the entire surface
A silicon oxide film 6 is deposited to a thickness of about 500 Å by the method, and thereafter, heat treatment is performed at 900 ° C. in an oxidizing atmosphere of DryO ₂ for about 60 minutes to form an N ⁻ layer.

(C) Next, for example, arsenic (As ⁺ ) is passed through the silicon oxide film 6 at 100 KeV, 5 × 10 ¹⁵
It is ion-implanted under the conditions of the individual / cm ^2, the source and the drain 8
Then, a high-concentration impurity layer (N ⁺ layer) is formed.

After that, although omitted, an intermediate insulating film is deposited, heat treatment for activating the implanted impurities is performed, contact holes are opened to form a wiring layer, and finally a protective film is formed to complete a semiconductor element. To do.

FIG. 2 shows that when the heat treatment in the step (b) is performed in an oxidizing atmosphere of DryO ₂ and an inert gas atmosphere of N ₂ , V _D = 3.3V and V _G = 1. 6
The substrate current (I _sub ) was compared under the conditions of 5 V, V _B = 0 V, N ⁻ ion implanter of phosphorus (P ⁺ ) 4.0 × 10 ¹³ / cm ² and 30 KeV, and the sidewall insulating film of 500 Å. It is a thing. In both cases, the heat treatment was performed at a temperature of 900 ° C. for 60 minutes. The horizontal axis represents the gate length (Lpoly).

It is generally known that the substrate current (hole current) is a measure of hot carrier generation due to impact ionization. As is clear from FIG. 2, when the heat treatment is carried out in the oxidizing atmosphere of DryO ₂ , the substrate current is about 1 / about that of the heat treatment in the inert gas atmosphere of N _2.
It turns out that it will be about 2 less.

When heat treatment is carried out in an oxidizing atmosphere, the silicon surface to be the source / drain is oxidized. In the situation where the silicon surface is oxidized, generally the diffusion of impurities becomes faster and the oxidation enhanced diffusion occurs. Therefore, when heat treatment is performed in an oxidizing atmosphere, diffusion is accelerated, the concentration profile of impurities becomes gentle, and the electric field is relaxed. Therefore, the generation of the substrate current is suppressed.

Further, it is known that if this heat treatment is performed after implanting arsenic (As) to be the source / drain, accelerated diffusion does not occur in the situation where high-concentration arsenic exists. After the low-concentration impurity implantation as described above,
It is effective to perform heat treatment before implanting arsenic at a high concentration.

Although the N-channel type MISFET has been described above as an example, the same can be applied to the P-channel MISFET.

[0020]

As described above in detail, according to the present invention, by making the heat treatment atmosphere oxidizing, the substrate current, which is a measure of hot carrier generation, can be reduced even if the low concentration impurity layer is shortened. Can be significantly reduced.

Therefore, it becomes possible to sufficiently secure the hot carrier resistance while shortening the side wall length, have a sufficient driving force even under a low power supply voltage, and further secure the hot carrier reliability. Can be realized.

[Brief description of drawings]

FIG. 1 is a process sectional view of a manufacturing method according to the present invention.

FIG. 2 is a graph showing the difference in substrate current between O ₂ / N ₂ heat treatments.

FIG. 3 Conventional MISFET structure

[Explanation of symbols]

1, 11 P-type silicon substrate 2, 12 field 3, 13 gate oxide film 4, 14 polysilicon 5 phosphorus 6 silicon oxide film 7, 16 N ⁻ layer 8, 17 N ⁺ layer 15 sidewall

Claims (1)

[Claims] 1. A method of manufacturing a MISFET having an LDD structure, comprising the steps of forming a gate electrode on a semiconductor substrate via an insulating film, and introducing impurities into the semiconductor substrate at a low concentration using the gate electrode as a mask. And a step of forming a thin insulating film on the surface of the gate electrode and the surface of the semiconductor substrate, a step of performing a heat treatment in an oxidizing atmosphere, and then using the thin insulating film on the gate electrode and the side wall of the gate electrode as a mask. And a step of introducing a high concentration of impurities into the semiconductor substrate, which are sequentially performed.
Method of manufacturing FET.