JPH05173185A - Manufacture of thin film transistor panel - Google Patents

Abstract

PURPOSE:To prevent interlayer short circuit between a capacitor line and a data line from occurring by short-circuiting both ends of the capacitor line to a voltage applying line in advance, and applying a voltage from both its ends to the capacitor line at the time of anodic oxidation of a gate line and the capacitor line. CONSTITUTION:On a substrate 1, a gate line GL and a capacitor line CL, and a pair of voltage applying lines 10 passing through the outside of both ends of these lines are provided, one end of the line GL is short-circuited to one of the pair of voltage applying lines 10, and also, both ends of the line CL are short-circuited to the voltage applying line 10. Subsequently, a voltage is applied to the line GL through the voltage applying line 10 from one end thereof, and to the line GL, a voltage is applied from both ends thereof and the anodic treatment is executed, and an oxide film is generated on the surface of the line GL and the line CL. Thereafter, a thin film transistor, a picture element electrode a date line and a ground line are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor panel used in an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art A thin film transistor panel (hereinafter referred to as a TFT panel) used for an active matrix liquid crystal display device has the following structure.

FIG. 15 is a plan view of a conventional TFT panel. This TFT panel has a plurality of gate lines GL, a plurality of data lines DL, and a plurality of thin film transistors on a transparent substrate 1 made of glass. 2 and a plurality of pixel electrodes 6 are formed.

The thin film transistor 2 is generally of an inverted stagger structure, and the thin film transistor 2 of the inverted stagger structure has the gate line G formed on the substrate 1.
With L as a gate electrode, an i-type semiconductor layer is formed on the gate insulating film 3 that covers the gate electrode.
A source / drain electrode is formed on top of this via an n-type semiconductor layer.

The gate insulating film 3 of the thin film transistor 2
Are formed on the entire surface of the substrate 1 so as to cover the gate lines GL. This gate insulating film 3 is Si N (silicon nitride)
The pixel electrode 6 is formed on the gate insulating film 3. The pixel electrode 6 is formed of a transparent conductive film made of ITO or the like, and is connected to the source electrode of the thin film transistor 2 at one end thereof.

The thin-film transistor 2 is covered with a protective insulating film 7 made of Si and formed on the entire surface of the gate insulating film 3, and the data line DL is formed on the protective insulating film 7. Has been done. The data line DL is connected to the drain electrode of the thin film transistor 2 through a contact hole provided in the protective insulating film 7. It should be noted that the protective insulating film 7 is formed with an opening that exposes each pixel electrode 6.

Further, one ends of the gate line GL and the data line DL are led out to the outside of the display area (display area of the liquid crystal display element) A within the outline shown by the chain double-dashed line in the figure, and the gate line GL A wide gate line terminal GLa is formed at the leading end, and a wide data line terminal DLa is formed at the leading end of the data line DL. The gate line terminal GLa is exposed by forming an opening in the gate insulating film 3 and the protective insulating film 7 thereabove.

Although not shown, the thin film transistor 2 and the data line DL are formed on the surface of the TFT panel.
Overcoat insulating film is formed, and the surface is subjected to orientation treatment.

In the active matrix liquid crystal display element, the display area A is surrounded by the TFT panel and a counter panel (not shown) having a counter electrode (transparent electrode) formed on a transparent substrate and having an alignment treatment applied thereon. It is manufactured by adhering it through a frame-shaped sealing material and enclosing a liquid crystal between the both panels. The substrate 1 is a plurality of TFTs.
A large-sized substrate from which a panel can be taken, and each TFT panel formed on this substrate 1 is cut along the dividing line B shown by a dashed line in the figure after its manufacture or after assembling a liquid crystal display element. By doing so, it is separated into individual TFT panels.

Further, in the active matrix liquid crystal display element, in order to reduce the fluctuation of the potential held in the pixel electrode during the non-selection period, the TFT panel is made to correspond to each pixel electrode 6 and a storage capacitor is provided. Is provided.

In FIG. 15, CL is a capacitor line for forming the storage capacitor, and this capacitor line CL is a gate line G on the substrate 1.
The same metal as L (Al, Al alloys, Ta, W, Mo, etc.)
Is formed by. The capacitor line CL is formed in parallel with the gate line GL, and the gate line GL
It faces one side edge of each pixel electrode 6 arranged along the line.

The storage capacitor is composed of the capacitor line CL, the pixel electrode 6 and the gate insulating film 3 between them. This storage capacitor is used when the pixel electrode 6 is selected (when the thin film transistor 2 is turned on).
Charge) applied to the pixel electrode 6 at
The storage capacitor holds the potential of the pixel electrode 6 during the non-selected period.

Both ends of the capacitor line CL are led out to the outside of the display area A, and the respective capacitor lines CL are commonly connected by the ground line EL at both ends thereof. The ground line EL is formed on the protective insulating film 7 in parallel with the data line DL, and is connected to the end of each capacitor line CL in the contact hole provided in the protective insulating film 7 and the gate insulating film 3. ..
This ground line EL is connected to the reference potential at its terminal ELa.

By the way, in the above TFT panel,
When the gate insulating film 3 and the protective insulating film 7 have defects such as pinholes and cracks, the gate line GL and the source / drain electrodes are short-circuited in the thin film transistor portion, the gate line GL, the capacitor line CL and the data line D are short-circuited.
An interlayer short circuit such as a short circuit between both lines at an intersection with L occurs.

Therefore, in the above TFT panel, the surfaces of the gate line GL and the capacitor line CL are oxidized to generate an oxide film, and the oxide film insulates the surfaces of the gate line GL and the capacitor line CL.
The occurrence of the interlayer short circuit is prevented.

The TFT panel in which the oxide film is formed on the surfaces of the gate line GL and the capacitor line CL as described above is manufactured by the following manufacturing method.

First, on the substrate 1, Al, Al-based alloy, Ta
, W, Mo and the like are formed, and the metal film is patterned to form the gate line GL and the capacitor line CL, and the pair of left and right voltage application paths 10. The voltage application paths 10 are formed outside the portion to be the TFT panel (outside the dividing line B).

In this case, each gate line GL is patterned into a shape in which an extension is formed at the outer end of its terminal GLa, and at this extension, one of the pair of voltage application paths 10 (the voltage application path on the left side in the figure) is formed. ) To short circuit.
Further, each capacitor line CL is patterned into a shape in which one end of the capacitor line CL is extended to the side opposite to the side where the gate line terminal GLa is formed, and at the extended portion, the other voltage application path 10 (left side in the drawing) is formed. Keep short circuited.

A conductive path 10a connected to the voltage application path 10 via a plurality of connecting paths 10b is formed in the voltage application path 10 for short-circuiting the capacitor line CL.
The end of each capacitor line CL is short-circuited to the conductive path 10a.

Next, a voltage is applied to the gate line GL and the capacitor line CL through the pair of voltage application paths 10 to perform anodization, thereby forming an oxide film on the surfaces of the gate line GL and the capacitor line CL. ..

In this anodic oxidation treatment, the substrate 1 is immersed in an electrolytic solution so that the gate line GL and the capacitor line CL are opposed to a counter electrode (platinum electrode) in the electrolytic solution, and these lines GL and CL are used as anodes. , The counter electrode is used as a cathode, and a voltage is applied between both electrodes. Thus, when a voltage is applied between both electrodes in the electrolytic solution, the surfaces of the gate lines GL and the capacitor lines CL, which are the anodes, undergo a chemical conversion reaction and are oxidized, and an oxide film is formed on the surfaces of these lines GL and CL. ..

The anodic oxidation process is performed with the resist mask covering the terminal GLa of the gate line GL and the portion connecting the ground line EL of the capacitor line CL. By doing so, the portion covered with the resist mask is not anodized because it does not come into contact with the electrolytic solution, so that the surface of the ground line connecting portion between the gate line terminal GLa and the capacitor line CL is also conductive. You can leave it as it is.

After that, the gate insulating film 3 is formed, and the i-type semiconductor layer, the n-type semiconductor layer and the source and drain electrodes are formed on the gate insulating film 3 by a known method, and the thin film transistor 2 is formed.
And the pixel electrode 6 and the data line DL.
And the ground line EL are formed to complete the TFT panel.

In this state, the gate line GL and the capacitor line CL remain short-circuited to one of the left and right voltage application paths 10 at one end thereof, but the portion where the voltage application path 10 is formed is the TFT panel. After being manufactured or after assembling the liquid crystal display element, the substrate 1 is cut off along the dividing line B to be cut off from the TFT panel. At this time, therefore, the gate line GL and the capacitor line CL are cut off from the voltage applying path 10. ..

[0025]

However, in the above-mentioned conventional method for manufacturing a TFT panel, the gate lines GL and the capacitor lines CL are anodized by applying a voltage to each of the lines GL and CL from one end thereof. Therefore, if there is a disconnection in the capacitor line CL,
An oxide film cannot be formed on the surface of the portion beyond the disconnection point of the capacitor line CL, so that an interlayer short circuit with the data line DL occurs at the portion beyond the disconnection point of the capacitor line CL. There was something that happened.

This is due to the above-mentioned anodizing treatment.
The voltage is applied to the portion between the junction with the short-circuit of the voltage application path of the capacitor line CL and the disconnection point, but the voltage is not applied to the portion from the disconnection point to the tip, so that the portion from the disconnection point to the tip is disconnected. This is because it cannot be anodized.

Therefore, when the gate insulating film and the protective insulating film have defects such as pinholes and cracks as described above, the data line DL formed on the protective insulating film is covered with the oxide film of the capacitor line CL. At the intersection with the unbroken part, the capacitor line CL is short-circuited, and the manufactured TFT panel becomes a defective product.

The disconnection of the above line may occur not only in the capacitor line CL but also in the gate line GL. In that case, the gate line GL also has a portion which is not anodized on the surface. Since the disconnection causes a display defect of the liquid crystal display element, the gate line GL
The TFT panel in which the line is broken is a defective product regardless of whether the oxidation state of the gate line GL is good or bad.

On the other hand, the capacitor line CL is
Since it is connected to the reference potential through the ground line EL connected to both ends thereof, even if there is a disconnection in this capacitor line CL, if there is only one disconnection site, the capacitor line CL and each pixel electrode 6 It is possible to accumulate charges in all the storage capacitors formed between and and hold the potential of all the pixel electrodes 6 during the non-selection period.

However, in the conventional manufacturing method, when the capacitor line CL has a disconnection, the data line DL is provided in a portion ahead of the disconnection point of the capacitor line CL as described above.
Therefore, even if all the gate lines GL are not broken, the manufactured TFT panel becomes a defective product having the above-mentioned interlayer short circuit, and therefore TF is generated.
The manufacturing yield of the T panel is deteriorated.

According to the present invention, even if there is a break in the capacitor line, an oxide film can be formed on the entire surface of the capacitor line, and an interlayer short circuit between the capacitor line and the data line is prevented from being produced. It is an object of the present invention to provide a method for manufacturing a TFT panel that can improve the yield.

[0032]

According to the method of manufacturing a TFT panel of the present invention, the gate line and the capacitor line, and a pair of voltage application paths respectively passing outside the both ends of the line are formed on the substrate. One end of the line is short-circuited to either one of the pair of voltage application paths, and both ends of the capacitor line are short-circuited to the pair of voltage application paths, respectively, and then the capacitor line is formed through the pair of voltage application paths. A voltage is applied to the gate line from one end thereof, and a voltage is applied to the capacitor line from both ends thereof to perform anodization, thereby forming an oxide film on the surfaces of the gate line and the capacitor line,
After that, the thin film transistor, the pixel electrode, the data line, and the ground line are formed.

Both ends of the capacitor line may be directly short-circuited to the pair of voltage application paths, or the gate line may be alternately short-circuited to the pair of voltage application paths, and the capacitor line may have both ends respectively. It may be short-circuited to the gate line and short-circuited to the pair of voltage application paths via the gate line. In the latter case,
The gate line short-circuit portion of the capacitor line may be separated and separated after at least anodizing treatment.

[0034]

According to this manufacturing method, since voltage is applied to the capacitor line from both ends when anodizing the gate line and the capacitor line, even if the capacitor line is broken, the voltage is applied to the entire capacitor line. It can be applied to produce an oxide film over its entire surface.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS. In addition, in FIGS.
Components corresponding to those of the conventional TFT panel shown in are denoted by the same reference numerals, and description of the same parts as those of the conventional TFT panel will be omitted.

In this embodiment, the TFT is manufactured by the following steps.
Manufacture panels.

[Step 1] First, as shown in FIG. 1, Al, Al-based alloy, Ta, W,
A metal film made of Mo or the like is formed, and this metal film is patterned to form a plurality of gate lines GL, a plurality of capacitor lines CL, and a pair of left and right voltage application paths 10. The voltage application path 10 is formed outside the portion to be the TFT panel (outside the dividing line B) as in the conventional manufacturing method.

In this case, each gate line GL is patterned into a shape in which an extension portion extending to the outside of the dividing line B is formed at the outer end of the terminal GLa, and one (left side in the figure) voltage application path is formed in this extension portion. Short to 10.

Further, each capacitor line CL is patterned so that both ends thereof are led out to the outside of the dividing line B, and one end thereof is short-circuited to the other (right side in the drawing) voltage applying path 10 and the other end thereof is The gate line GL is short-circuited to the one of the short-circuited voltage application paths 10 through the gate line terminals GLa. In this example,
The voltage applying path 10 on the right side, which short-circuits one end of the capacitor line CL, is connected to the voltage applying path 1 via a plurality of connecting paths 10b.
0 forms a conductive path 10a connected to 0, and this conductive path 10a
Each capacitor line CL is short-circuited.

[Step 2] Next, on the terminal GLa of the gate line GL and the connection portion of the ground line EL connected to both ends of the capacitor line CL in the subsequent step, respectively, a resist mask covering these portions, respectively. In this state, a voltage is applied from the pair of voltage application paths 10 to the gate line GL and the capacitor line CL to perform anodization, and the gate line GL and the capacitor line C are formed.
An oxide film is formed on the surface of L.

In the anodizing process, the substrate 1 is immersed in an electrolytic solution to form the gate line GL and the capacitor line CL.
Facing the counter electrode (platinum electrode) in the electrolyte,
These lines GL and CL are used as anodes and the counter electrode is used as a cathode, and an oxidation voltage is applied between the two electrodes. The oxidation voltage is applied to the end of the voltage application path 10 via a clip-type connector or the like. When a voltage is applied to the voltage application path 10 in this manner, the voltage is applied from the voltage application path 10 to each gate line GL and each capacitor line CL.

Then, in the electrolytic solution, the gate line G
When a voltage is applied between L and the capacitor line CL and the counter electrode, the surfaces of the gate line GL and the capacitor line CL, which are anodes, undergo a chemical conversion reaction and are oxidized,
An oxide film is formed on these surfaces. This oxide film is generated only in the portion not covered with the resist mask, and is covered with the resist mask (the portion not in contact with the electrolytic solution), that is, the gate line terminal GLa and the ground line of the capacitor line CL. The surface of the connection part is left to be conductive. Further, at this time, the surface of the portion of the voltage application path 10 immersed in the electrolytic solution is also oxidized.

In this case, since the capacitor line CL is short-circuited to the left and right voltage application paths 10 at both ends,
Even if there is a disconnection in the capacitor line CL, if there is only one disconnection point, the voltage is applied to the entire capacitor line.
An oxide film can be formed on the entire surface.

[Step 3] Next, as shown in FIG. 2, the thin film transistor 2, the pixel electrode 6, and the data line DL.
And a ground line EL commonly connecting the respective capacitor lines CL at both ends thereof to complete a TFT panel.

FIG. 3 is a cross-sectional view of the thin film transistor and pixel electrode portion of the completed TFT panel, FIGS. 4 and 5
FIG. 4 is a cross-sectional view of a capacitor line common connection portion of a completed TFT panel. 3 to 5, a is an oxide film formed on the surfaces of the gate lines GL and the capacitor lines CL by the anodizing process.

The thin film transistor 2 has an inverted staggered structure, and the thin film transistor 2 uses the gate line GL formed on the substrate 1 as a gate electrode, and the gate insulating film 3, the i-type semiconductor layer 4, and the n layer on the gate line GL. Type semiconductor layer 5
The source and drain electrodes S and D are formed.

This thin film transistor 2 is composed of a gate insulating film 3 made of SiN and a-Si (amorphous silicon) on a substrate 1 whose gate lines GL and capacitor lines CL are formed and whose surfaces are anodized. An i-type semiconductor layer 4, an n-type semiconductor layer 5 made of n-type impurity-doped a-Si, and a source / drain metal film made of Cr, Al-based alloy or the like are sequentially formed, and these are formed as a transistor element. After patterning to the outer shape of the region, the source / drain metal film is separated at the portion corresponding to the channel region of the i-type semiconductor layer 4 to form the source / drain electrodes S and D, and the n-type semiconductor layer 5 is formed.
Then, the portion between the source and drain electrodes S and D is removed to manufacture.

On the other hand, the pixel electrode 6 is formed by forming a transparent conductive film such as ITO on the gate insulating film (transparent film) 3 and patterning the transparent conductive film. One end of the pixel electrode 6 is the source electrode S of the thin film transistor 2.
It is connected to the source electrode S by being formed overlying. Further, the pixel electrode 6 is formed with the edge portion on the other end side facing the capacitor line CL, and a storage capacitor is formed in this portion.

On the thin film transistor 2,
A protective insulating film 7 made of Si N is formed. An opening for exposing the pixel electrode 6 and a contact hole for exposing the data line connecting portion of the drain electrode D are formed in the protective insulating film 7, and the protective insulating film 7 and the gate insulating film 3 thereunder are further formed. Then, a contact hole for exposing the ground line connecting portion of the capacitor line CL and an opening for exposing the gate line terminal GLa are formed.

The data line DL and the ground line EL commonly connecting the capacitor lines CL are formed on the protective insulating film 7, and the data line DL is formed in the contact hole provided in the protective insulating film 7 at the drain. Electrode D
And the ground line EL is connected to each capacitor line CL through a contact hole formed in the protective insulating film 7 and the gate insulating film 3.

The data line DL and the ground line EL
Is formed at the same time by forming a metal film of Al or an Al-based alloy on the protective insulating film 7 and patterning the metal film. In this case, since the surface of the ground line connecting portion of the capacitor line CL is not oxidized, the ground line EL can be conductively connected to the capacitor line CL in the contact hole.

In the TFT panel manufactured as described above, each gate line GL remains short-circuited to one voltage application path 10 at the end portion on the terminal forming side. After assembling the liquid crystal display element, the substrate 1 is broken along the dividing line B, and the portions where the left and right voltage application paths 10 are formed are separated from the TFT panel, whereby the gate lines GL can be separated into individual lines.
Further, when the portion where the voltage application path 10 is formed is separated from the TFT panel, each capacitor line CL is also separated from the left and right voltage application paths 10.

That is, in the method of manufacturing the TFT panel, a voltage is applied from both ends to the capacitor line CL when the gate line GL and the capacitor line CL are anodized. According to this manufacturing method, the capacitor line CL is used. Even if there is a disconnection in the capacitor, a voltage is applied to the entire capacitor line to cover the entire surface of the oxide film a.
Can be generated.

Therefore, according to this manufacturing method, even if a defect such as a pinhole or a crack occurs in the gate insulating film 3 and the protective insulating film 7, the data formed on the capacitor line CL and the protective insulating film 7 will be described. The line DL can be insulated from each other by the oxide film a covering the surface of the capacitor line CL, and an interlayer short circuit at the intersection of the capacitor line CL and the data line DL can be prevented.

When one capacitor line CL is disconnected at two or more places, this capacitor line C
Since only the portions on both ends of the disconnection point of L are anodized and the portions on the inner side of the disconnection point are not oxidized, an interlayer short circuit with the data line DL may occur at this section, but one capacitor is formed. It is extremely rare that the line CL is broken at two or more places.

Therefore, in most cases, the manufactured TFT panel becomes defective only when the gate line GL is broken. Therefore, according to the above-described manufacturing method, the conventional manufacturing method is not possible. In comparison, the manufacturing yield of the TFT panel can be significantly improved.

In the first embodiment, the terminals GLa of all the gate lines GL are formed on the same side.
The present invention can also be applied to the manufacture of a TFT panel in which the terminals GLa of the gate lines GL are alternately formed on the opposite side.

FIG. 6 shows a second embodiment of the present invention. This embodiment is applied to the manufacture of a TFT panel in which the number of gate lines is increased in order to increase the resolution of the liquid crystal display element. In this TFT panel, in order to secure a space between each gate line terminal, Each gate line GL
Terminals GLa are alternately formed on the opposite side.

In this embodiment, the gate lines GL having terminals GLa alternately formed on opposite sides are short-circuited alternately to the voltage application paths 10 on the left and right at the ends on the terminal formation side, and the capacitor lines CL are The gate lines GL and the capacitor lines CL are anodized by short-circuiting both ends thereof to the left and right voltage application paths 10. After the anodization of the lines GL and CL, the first embodiment is performed. A TFT panel is completed in the same manner as in the example.

In this embodiment, each of the left and right voltage application paths 10 is a line. Further, in this embodiment, the adjacent capacitor lines CL are alternately short-circuited at one end or the other end thereof to connect all the capacitor lines CL in a meandering line shape, and the short-circuited portion of the adjacent capacitor lines CL is applied with a voltage. By connecting to the path 10, both ends of each capacitor line CL are short-circuited to the left and right voltage application paths 10.

Further, in the first and second embodiments,
Both ends of the capacitor line CL are directly short-circuited to the left and right voltage application paths 10, but the terminals GL of each gate line GL are connected.
When manufacturing a TFT panel in which a is alternately formed on the opposite side, both ends of the capacitor line CL may be short-circuited to the gate line GL and short-circuited to the left and right voltage application paths 10 via the gate line GL. ,In that case,
After performing at least the anodic oxidation treatment, the short-circuited portion of the capacitor line DL and the gate line GL may be separated and separated.

7 to 13 show a third embodiment of the present invention. In this embodiment, both ends of the capacitor line CL are short-circuited to the left and right voltage application paths 10 via the gate line GL and anodization is performed, and an FT panel is manufactured by the following steps.

[Step 1] First, as shown in FIG. 7, a metal film is formed on the substrate 1, and the metal film is patterned to form a plurality of gate lines in which terminals GLa are alternately formed on opposite sides. GL, a plurality of capacitor lines CL, and a pair of left and right voltage application paths 10 are formed.

In this case, each gate line GL is patterned into a shape in which an extension extending outside the dividing line B is formed at the outer end of the terminal GLa, and the left and right voltage application paths 10 are alternately short-circuited at this extension. I will let you.

Each end of each capacitor line CL is connected to the side edge of the display area A and the gate line terminal GL.
The portion between a and a is patterned into a shape short-circuited to the gate line GL. In this embodiment, between the one side edge of the display area A and each gate line terminal GLa arranged on this side, and between the other side edge of the display area A and each gate line terminal GLa arranged on this side. In between, a short circuit 11 is formed which is orthogonal to the gate line GL and the capacitor line CL (the gate line GL is made of the metal film).
And formed integrally with the capacitor line CL), and both ends of each capacitor line CL are short-circuited to each gate line GL via this short circuit path 11.

[Step 2] Next, a voltage is applied from the voltage application path 10 to the gate line GL, and a voltage is also applied from the gate line GL to the capacitor line CL to perform anodizing treatment. An oxide film is formed on the surface of the capacitor line CL.

The anodic oxidation treatment is performed as follows. First, as shown in FIG. 8 and FIG. 9A, these parts are provided on the terminal GLa of the gate line GL, the ground line connecting part of the capacitor line CL, and the capacitor line short-circuiting part of the short-circuit path 11. A resist mask 21 that covers each is formed.

Next, the substrate 1 is immersed in an electrolytic solution, and the surfaces of the gate lines GL and the capacitor lines CL are anodized in the same manner as in the first embodiment. In this embodiment, the gate lines GL are connected from the left and right voltage application paths 10.
Is applied to the respective capacitor lines CL from the gate lines GL via the short-circuit paths 11.

When this anodic oxidation treatment is performed, the surfaces of the gate lines GL and the capacitor lines CL are shown in FIG.
An oxide film a is formed as shown in FIG. This oxide film a is generated only in the portion not covered with the resist mask 21,
The part covered with the resist mask 21 and not exposed to the electrolytic solution,
In other words, the gate line terminal GLa, the ground line connecting portion of the capacitor line CL, and the capacitor line short-circuiting portion of the short-circuit path 11 are also left in a conductive state on their surfaces.

[Step 3] Next, as shown in FIG. 10, the short-circuited portion of each capacitor line CL with the gate line GL (capacitor line short-circuited portion of the short-circuit path 11 in this embodiment) is separated and separated.

The short-circuiting portion of the capacitor line CL from the gate line GL is separated by separating the capacitor of the short-circuit path 11 as shown in FIGS. 11 and 12 after removing the resist mask 21 formed during the anodizing process. A resist mask 22 that covers other parts except the line short-circuit part
Is formed, and in this state, a region of the capacitor line short circuit portion of the short circuit path 11 whose surface is not oxidized is removed by etching. Since the etching of this region can be performed using the capacitor line CL outside this region and the oxide film a on the surface of the short circuit 11 as an etching mask, the shape accuracy of the resist mask 22 may be somewhat rough.

[Step 4] Next, as shown in FIG. 13, the thin film transistor 2, the pixel electrode 6, and the data line DL.
And a ground line EL commonly connecting the respective capacitor lines CL at both ends thereof to complete a TFT panel.

The portion of the substrate 1 on which the voltage application path 10 is formed is separated from the TFT panel by breaking the substrate 1 along the dividing line B after manufacturing the TFT panel or after assembling the liquid crystal display element. ..

Also in this embodiment, the voltage can be applied to the entire capacitor line to generate the oxide film a on the entire surface thereof regardless of the disconnection of the capacitor line CL. It is possible to prevent the occurrence of an interlayer short circuit with the line DL and improve the manufacturing yield of the TFT panel.

In the above embodiment, before the step of forming the thin film transistor 2 is started (before the gate insulating film 3 and the like are formed).
Further, the gate line short-circuited portion of the capacitor line CL (capacitor line short-circuited portion of the short-circuit path 11 in the above-mentioned embodiment) is separated and separated, but at least the anodization treatment is performed for the separation of the gate line short-circuited portion. It may be performed at any time later.

FIG. 14 shows another method of disconnecting the gate line short-circuited portion (here, the capacitor line short-circuited portion of the short-circuit path 11) of the capacitor line CL. In this example, the gate line short-circuit portion of the capacitor line CL is separated and separated when the data line DL and the ground line EL commonly connecting the capacitor lines CL are formed. This separation is performed as follows. ..

First, as shown in FIG. 14A, after forming the protective insulating film 7, the short-circuited portion of the capacitor line of the short-circuit path 11 is exposed on the protective insulating film 7 and the gate insulating film 3 thereunder. The opening is formed. This opening has a protective insulating film 7
Then, the gate insulating film 3 and the contact hole exposing the data line connecting portion of the drain electrode D and the contact hole exposing the ground line connecting portion of the capacitor line CL are formed at the same time.

Next, as shown in FIG. 14B, after forming a metal film 30 to be the data line DL and the ground line EL on the protective insulating film 7, the metal film 30 is patterned to form the data. When forming the line DL and the ground line EL, the short circuit 1 is formed together with the metal film 30 in the opening.
The capacitor line short circuit part of 1 is etched and removed,
As shown in FIG. 14C, the gate line short circuit portion of the capacitor line CL is separated and separated.

As described above, when the gate line short-circuit portion of the capacitor line CL is cut and separated at the time of forming the data line DL and the ground line EL, the data line DL and the ground line EL are formed by using the forming process. Since the gate line short circuit portion can be separated and separated, the TFT panel can be efficiently manufactured.

In the third embodiment, the capacitor line CL is separated and separated at the short-circuit portion with the short-circuit path 11. However, the capacitor line CL is separated from the gate line GL by the gate of the short-circuit path 11. Alternatively, the line short-circuited portion and the capacitor line short-circuited portion may be separated from each other, or the entire short-circuit path 11 may be removed.

In the first to third embodiments, the gate line GL and the capacitor line CL are anodized by a method of causing a chemical conversion reaction in an electrolytic solution. Alternatively, it may be performed by plasma oxidation that causes a chemical conversion reaction in a gas atmosphere.

[0082]

According to the method of manufacturing a TFT panel of the present invention, both ends of the capacitor line are short-circuited to the voltage application path, and a voltage is applied to the capacitor line from both ends when the gate line and the capacitor line are anodized. Therefore, even if there is a disconnection in the capacitor line, it is possible to apply a voltage to the entire capacitor line and generate an oxide film on the entire surface, preventing the occurrence of interlayer short circuit between the capacitor line and the data line. Therefore, the manufacturing yield can be improved.

[Brief description of drawings]

FIG. 1 is a plan view showing a state where gate lines and capacitor lines are formed on a substrate showing a first embodiment of the present invention.

FIG. 2 is a plan view of the TFT panel manufactured in the first embodiment.

FIG. 3 is a sectional view of a thin film transistor and a pixel electrode portion of the TFT panel.

FIG. 4 is a cross-sectional view of a capacitor line common connection portion of the TFT panel.

5 is a cross-sectional view taken along the line VV of FIG.

FIG. 6 is a manufactured TFT showing a second embodiment of the present invention.
The top view of a panel.

FIG. 7 is a plan view showing a state where gate lines and capacitor lines are formed on a substrate showing a third embodiment of the present invention.

FIG. 8 is a partial plan view showing a method of anodizing a gate line and a capacitor line in a third embodiment.

9 is a sectional view taken along line IX-IX in FIG. 8 showing a state before anodizing and a state after anodizing.

FIG. 10 is a plan view showing a state in which a gate line short circuit portion of a capacitor line in the third embodiment is separated and separated.

FIG. 11 is a partial plan view showing a method of separating and separating a gate line short circuit portion of the capacitor line.

12 is a sectional view taken along line XII-XII in FIG.

FIG. 13 is a plan view of a TFT panel manufactured in the third embodiment.

FIG. 14 is a separation process diagram showing another method of separating the gate line short-circuited portion of the capacitor line in the third embodiment.

FIG. 15 is a plan view of a TFT panel manufactured by a conventional manufacturing method.

[Explanation of symbols]

1 ... Substrate, 2 ... Thin film transistor, GL ... Gate line, CL ... Capacitor line, a ... Oxide film, 3 ... Gate insulating film, 4 ... i-type semiconductor layer, 5 ... N-type semiconductor layer, S ... Source electrode, D ... Drain electrode, DL ... Data line, 6
... Pixel electrode, 7 ... Protective insulating film, 10 ... Voltage application path, 11
... Short circuit, EL ... Grounding line, A ... Display area, B ... Disconnection line.

Claims (3)

[Claims] 1. A plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, a plurality of pixel electrodes, and a plurality of storage capacitors between the pixel electrodes on a transparent substrate. Capacitor line of
In the method of manufacturing a thin film transistor panel provided with a ground line commonly connecting each of the capacitor lines, the gate line and the capacitor line, and a pair of voltage application paths respectively passing outside the both ends of these lines on the substrate. After forming one end of the gate line to one of the pair of voltage application paths and shorting both ends of the capacitor line to the pair of voltage application paths, respectively, the pair of voltage application paths is formed. A voltage is applied to the gate line from one end thereof and a voltage is applied to the capacitor line from both ends thereof to perform anodization, thereby forming an oxide film on the surfaces of the gate line and the capacitor line. After that, the thin film transistor, the pixel electrode, the data line, and the ground line. The method of fabricating a thin film transistor panel and forming a down. 2. The method of manufacturing a thin film transistor panel according to claim 1, wherein both ends of the capacitor line are directly short-circuited to the pair of voltage application paths. 3. The gate lines are alternately short-circuited to the pair of voltage application paths, and both ends of the capacitor line are respectively short-circuited to the gate lines, and short-circuited to the pair of voltage application paths via the gate lines. The method of manufacturing a thin film transistor panel according to claim 1, wherein the gate line short-circuited portion of the capacitor line is cut and separated after at least the anodizing treatment.