JPH05167919A - Circuit for separating data and synchronizing digital video signal - Google Patents

Abstract

PURPOSE:To separate a synchronous signal and an AUX (addition) data from a digital video signal. CONSTITUTION:This system is provided with a synchronism separator circuit 1 for extracting a synchronous signal from an inputted digital video signal, a counter 2 for detecting only a necessary value from data separated by the circuit 1, a decoder 3, and a data separator circuit 4 for separating AUX data and a video signal from the digital video signal by using a value detected by the counter 2 and the decoder 3. Even when the digital video signal and the AUX data are simultaneously transmitted, the synchronous signal and the AUX data can be separatively outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal synchronizing and data separating circuit for separating a synchronizing signal and a data signal from a simultaneously transmitted video signal and AUX (additional) signal in a device for handling a digital video signal. Regarding

[0002]

2. Description of the Related Art In a conventional device that handles digital video signals, an AUX signal is not input at the same time as a video signal, so that it has a certain level (for example, FIG. 2A).
50%) shown at point A), and synchronous separation is performed.
No consideration was given to data separation of signals.

[0003]

Therefore, when the AUX signal and the video signal are input at the same time, the output separated by the synchronization (SYNC) includes another data during the period, that is, the data signal. There was a problem such as not being able to perform accurate sync separation.

The present invention has been made in order to solve the above-mentioned conventional problems, and it is a digital video signal capable of stably and accurately separating a synchronizing signal and a data signal from an AUX signal and a video signal input at the same time. It is an object to provide a synchronization and data separation circuit.

[0005]

In order to achieve the above object, the present invention provides only a necessary value from a sync separation circuit for extracting a sync signal from an input digital video signal and data separated by the sync separation circuit. It is provided with a counter and a decoder for detecting, and a sync separation circuit for separating the AUX data and the video signal from the digital video signal by using the values detected by the counter and the decoder.

[0006]

With the above construction, a digital video signal and an AUX
Even if data is transmitted at the same time, the sync signal can be separated by detecting the sync signal part, and the necessary value can be detected from the sync separated data, and this value can be used to extract the digital video signal. The AUX data can be separated.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to the drawings shown in FIGS.

FIG. 1 is a block diagram of this device, FIG. 2 is a signal waveform diagram showing a signal separation process, and FIG. 3 is a circuit diagram showing a concrete circuit.

In FIG. 1, 1 is a separation circuit, which is shown in FIG.
The digital video signal and the AUX signal shown in (1) are simultaneously input.

The data order of the input signal is detected by the separation circuit 1, and the detected data signal and the sync signal using the data signal are separated, and the separated signal is input to the counter 2. After being done and counted,
Only the necessary values are detected by being decoded by the decoder 3.

This value is input to the data separation circuit 4, and the data separation circuit 4 uses the AUX shown in FIG.
The signal and the video data signal shown in FIG. 2 (d) are separately output, and the sync signal shown in FIG. 2 (d) is outputted from the sync separation circuit 1.

FIG. 3 shows a specific circuit, in which DFF represents a D-type flip-flop, which is driven by a common clock signal.

It is assumed that a digital video signal and a sync signal as shown in FIG. 2A are simultaneously input to the above circuit.

This input signal (a) is applied to points A, B, and
A continuous sync signal is added to the C point and the D, E, and F points in the subsequent stage, and an AUX data signal is added between the G point and the H point and between the I point and the J point. Detect and
Send to AND gate 11.

The data at the point B is input to the AND gate 11, and the data at the points A and B are sent to the DFF 12.
When the DFF 12 and the signal at the point C are input, the AND gate 13 outputs the preceding stage data (a) as one clock width. Similarly, in the latter stage, the DFF 14 detects the point D and sends it to the AND gate 15. The AND gate 15 sends a signal to the DFF 16 when the data at the point E is input.

The DFF 16 and the data at the F point are ANDed.
When input to the gate 17, the AND gate 17 outputs data (a) for one clock width, the data (a) as a set signal and the signal (a) as a reset signal, and the RS flip-flop 18 Is input to
As a result, the RS flip-flop 18 causes the DFF1
The sync signal shown in FIG. 2B is separated and output via 9.

On the other hand, since the data (a) is input to the counter 2 as a load pulse, the counter 2 starts counting.

Then, the data order of the input signals is counted, and the decoder 4 outputs a pulse signal (c) between the points G and H and the points I and J to the data separation circuit 4.

The data separation circuit 4 separates the digital video signal from the AUX data shown in FIG. 2C and the video signal shown in FIG. 2D by using the input pulse signal (C). It is designed to output.

As described above, the synchronizing signal is separated by the combination of the D-type flip-flop and the AND gate for extracting the continuous points A to C and D to F in the input signal (a), and the counter 2 and the decoder 3 separate the AUX signal. The signal is taken out and the AUX data and the video signal are separated by the data separation circuit 4, so that the sync signal and the AUX data can be separated accurately and stably.

In the above embodiment, the data is detected at three points both before and after the input signal, but more or less data may be detected.

Although the load pulse of the counter 2 is obtained from the synchronizing signal, the AUX data (point G to H)
Points).

[0023]

As described above in detail, the present invention detects continuous data from the simultaneously transmitted digital video signal and AUX signal to separate the synchronizing signal, and
A counter and a decoder detect only a necessary value from the data output by the sync separation, and the AUX data is separated from the digital video signal by using this value. The sync signal, the AUX data, and the video signal Can be separated in an accurate and stable state.

[Brief description of drawings]

FIG. 1 is a block diagram of a synchronization and data separation circuit according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram showing a separation process of a synchronization and data separation circuit according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a specific configuration of a synchronization and data separation circuit according to an embodiment of the present invention.

[Explanation of symbols]

 1 sync separation circuit 2 counter 3 decoder 4 sync separation circuit

Claims (1)

[Claims] 1. A sync separation circuit for extracting a sync signal from an input digital video signal, a counter and a decoder for detecting only a necessary value from the data separated by the sync separation circuit, and a value detected by the counter and the decoder. A digital video signal synchronization and data separation circuit comprising a sync separation circuit for separating AUX data and video signal from a digital video signal by utilizing the same.