JPH05167429A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To obtain an output signal changed at a high speed corresponding to a change in the output signal at the side of a CMOS logic circuit by setting a level shift voltage in a range in which NPN and PNP transistors(TRs) are not turned on in steady-state. CONSTITUTION:A level shift circuit comprising a transistor(TR) T3 whose base and emitter are provided with a resistor R1 and whose base and collector are provided with a resistor R2 is inserted between a P-channel MOSFET and an N-channel MOSFET, that is, between bases of output TRs T1, T2, The level shift circuit generates a level shift voltage resulting from increasing a base-emitter voltage VBE of the TR T3 according to the resistance of the resistors R1, R2. Then the level shift voltage is set to a prescribed voltage to quicken the operation while preventing the production of a DC current between the TRs T1, T2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device including, for example, a complementary push-pull output circuit and a bipolar CMOS (hereinafter abbreviated as BiCMOS) circuit including a CMOS logic circuit for driving the complementary push-pull output circuit. It relates to a technology that is particularly effective for use in.

[0002]

2. Description of the Related Art A complementary push-pull output circuit composed of an NPN transistor and a PNP transistor is used as a C
BiCM driven by MOS logic circuit as shown in FIG.
There is an OS circuit. Regarding such a BiCMOS circuit, for example, there is US Pat. No. 3,541,353.

[0003]

In the circuit of FIG. 4, the circuit of FIG.
As shown in the operation waveform diagram of, when the input signal A is changed from the low level to the high level while the input signal B (or A) is at the high level, the level of the input signal A is the threshold of the N-channel MOSFET Q3. When the voltage becomes equal to or higher than Vthn, the MOSFET Q3 starts to turn on,
Combined conductance of Q3 and Q4 and MOSFET Q2
The output voltage V1 changes in accordance with the ratio of the conductances. When the output voltage V1 becomes equal to or lower than the base-emitter voltage VBE1 of the NPN transistor T1, the transistor T1 is turned on and the output signal X corresponding to the change of the input signal V1 is formed. Therefore, there is a problem that the change of the output signal becomes slow. An object of the present invention is to provide a semiconductor integrated circuit device equipped with a BiCMOS circuit which has a high speed operation. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0004]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, by providing a level shift circuit in which resistors are provided between the base and the emitter and between the base and the collector between the bases of the NPN transistor and the PNP transistor that form the complementary push-pull output circuit, both transistors are constantly turned on. Set the level shift voltage within the range that does not cause the state.

[0005]

According to the above-mentioned means, since the bias voltage is applied to both the output transistors shallowly, a high speed is achieved in response to the change of the output signal on the side of the CMOS logic circuit without generating a direct current in the output transistors in the steady state. It is possible to obtain an output signal that changes to.

[0006]

1 is a circuit diagram of an embodiment of a BiCMOS circuit according to the present invention. Each circuit element shown in the same drawing is formed on one semiconductor substrate such as single crystal silicon by a known BiCMOS technique together with other circuit elements which realize a certain circuit function. In the circuit diagram, an MO with an arrow on its channel (back gate) part
The SFET is a P-channel type and is distinguished from an N-channel MOSFET without an arrow.

This embodiment is directed to a BiCMOS circuit having a 2-input NAND (nand) function. P
The channel type MOSFETs Q1 and Q2 are connected in parallel, and the input signals B and A are supplied to their respective gates. In addition, N-channel type MOSFETs Q3 and Q4
Are arranged in series, and the input signals A and B are supplied to their respective gates. That is, the input signal A is commonly supplied to the gates of the P-channel type MOSFET Q2 and the N-channel type MOSFET Q3, and the P-channel type MOSFET Q1 and the N-channel type MOSF of the other side are supplied.
An input signal B is commonly supplied to the gates of ETQ4.

In this embodiment, the CMO as described above is used.
The following level shift circuit is provided to drive the complementary push-pull type NPN output transistor T1 and PNP output transistor in which the emitters are shared by the output signal of the S logic gate circuit at high speed. P-channel type MOSFE constituting the CMOS logic circuit
Between the T side and the N-channel MOSFET side, in other words, between the bases of the output transistors T1 and T2,
A resistor R1 is provided between the base and the emitter, and a level shift circuit including a transistor T3 having a resistor R2 between the base and the collector is inserted. This level shift circuit has a base-emitter voltage VB of the transistor T3.
Forming a level shift voltage in which E is increased according to the resistance ratio of the resistors R1 and R2.

A constant current I such as VBE / R1 flows through the resistor R1. Since this constant current I also flows through the resistor R2, the voltage ΔV across the resistor R2 is obtained by the following equation (1). ΔV = R2 × I = VBE × R2 / R1 (1) Therefore, the level shift voltage between the emitter and collector of the transistor T3 is VBE + ΔV = VBE (1 + R)
2 / R1). Here, if R1 <R2, the level shift voltage becomes a voltage lower than 2VBE and higher than VBE. When the level shift voltage is set to 2 VBE or higher, a direct current constantly flows between the transistors T1 and T2, which increases power consumption. The level shift voltage is set at a voltage close to 2VBE or less in order to speed up the operation while preventing the generation of such a DC current.

FIG. 2 is a waveform diagram for explaining the operation of the BiCMOS circuit according to the present invention. For example, when the input signal B is at the high level, the input signal A changes from the low level to the high level, and the N-channel MO
When the voltage becomes equal to or higher than the threshold voltage Vthn of the SFET Q3, the output signal of the CMOS logic circuit starts to change according to the ratio of the combined conductance of the N-channel MOSFETs Q3 and Q4 and the combined conductance of the P-channel MOSFETs Q1 and Q2. At this time, P-channel type MOSF
Since the level shift circuit is provided between the ET side and the N-channel type MOSFET side, the output signal V2 on the N-channel type MOSFET side is the P-channel type MOS.
The output signal A on the FET side has a voltage reduced by the level shift voltage VB. Therefore, the level shift voltage V
The PNP transistor T2 starts its operation with the start of the decrease of B, and starts the operation of discharging the output signal X from the high level to the low level. As a result, the output signal X can be dropped from the high level to the low level at a high speed almost corresponding to the change of the output signals V1 and V2 on the logic circuit side. This is the same when the input signal A is at high level and the input signal B changes from low level to high level.

When the input signal B is at the high level and the input signal A changes from the high level to the low level again and becomes equal to or lower than the threshold voltage Vthp of the P-channel MOSFET Q2, the combined conductance of the P-channel MOSFETs Q1 and Q2 is obtained. , The output signal V1 of the CMOS logic circuit starts to change according to the ratio of the combined conductances of the N-channel MOSFETs Q3 and Q4. At this time, the level shift circuit causes the P-channel MOSFET
The output signal V1 on the side becomes a voltage increased by the level shift voltage VB with respect to the output signal V2 on the side of the N-channel MOSFET. Therefore, as the level shift voltage V2 starts rising, the NPN transistor T1 starts operating,
The operation of charging up the output signal X from low level to high level is started. As a result, the output signal X is almost corresponding to the change of the output signals V1 and V2 on the logic circuit side.
Can be quickly started from low level to high level. This is the same when the input signal A is at high level and the input signal B changes from high level to low level.

FIG. 3 shows a BiCM to which the present invention is applied.
A circuit diagram of an embodiment of a memory array section and its peripheral circuits in a static RAM having an OS structure is shown. In the figure, one word line W, one word line selection circuit, one memory cell MC, and a pair of complementary data lines D.
T, DB, and their load circuits, write recovery circuits, sense amplifiers, and column switch circuits are exemplarily shown. Also, an output circuit corresponding to the sense amplifier,
The data input circuit IB is also drawn.

The memory cell MC is a P channel type MOS.
CMOS consisting of FET and N-channel MOSFET
CMO in which the input and output of the inverter circuit are cross-connected
S latch circuit, its input / output node and complementary data line D
It is composed of a transmission gate MOSFET for address selection provided between T and DB. The operating voltage on the high level side of the memory cell is the ground potential of the circuit, and the operating voltage on the low level side is the constant voltage V formed by the voltage generating circuit.
EM is used. The memory cell of this embodiment is a complete C
Although a memory cell having a MOS structure is used, a high resistance load made of a polysilicon layer or the like may be used instead of the P-channel MOSFET. This high resistance load is set to a high resistance value such that the memory level accumulated in the gate of the N-channel MOSFET passes a minute current that is not lost by the drain leak current. Therefore, the high resistance load has a significantly different meaning from the load in the normal ratio type inverter circuit. When such a high resistance load is used, the size (occupied area) of the memory cell can be significantly reduced. However, when the operating voltage on the low level side of the memory cell is set to a value such as -3.2V to -3.3V, the operation of the memory cell may become unstable. Use is preferable.

The gate of the transmission gate MOSFET of the memory cell is connected to the corresponding word line. The word line W is selected by the word line drive circuit NOR1 formed of the BiCMOS circuit shown in FIG. Since the above-mentioned embodiment has the NAND structure, in order to obtain the NOR (nor) gate structure as in this embodiment, the P-channel type MOSFET may be arranged in series and the N-channel type MOSFET may be arranged in parallel. Good. The power supply voltage may be set to VEE or VEM on the low level side and the ground potential of the circuit on the high level side. For example, if the NOR gate circuit NOR1 is used as three inputs and the output signals of three predecode circuits corresponding to a 7-bit address signal are supplied by synthesis, one word line is selected from 128 word lines. Such a circuit configuration can be realized, and a word line selection signal is formed from one word line selection circuit in which the above three types of predecode signals are all set to the low level.

The complementary data lines DT and DB are provided with data line load means composed of P-channel MOSFETs MP1 and MP2. These MOSFET MP1, MP
2 has its conductance formed relatively small in consideration of the write characteristic, and the constant voltage VEM is constantly supplied to its gate. These MOSFET MP1, MP
P channel type MOSFET with a relatively large conductance in the source and drain paths of 2.
Source and drain paths of MP3 and MP4 are provided in parallel. By supplying the write control signal WE1 to the gates of these MOSFETs MP3 and MP4, the MOSFETs MP3 and MP4 are turned on at times other than the write operation. In other words, the MOSFETs MP3 and MP4 are M
Together with the OSFETs MP1 and MP2, they constitute a data line load during a read operation. That is, at the time of read operation, the signal amplitude of the complementary data line is limited to realize high speed read. On the other hand, in the write operation, the control signal WE1 turns off the MOSFETs MP3 and MP4 having the relatively large conductance, and the loads on the complementary data lines DT and DB are composed of the MOSFETs MP1 and MP2 having only a small conductance. By doing so, the signal amplitude of the write data transmitted to the complementary data line is increased and high speed writing is performed.

A bias voltage level-shifted by diode-connected transistors Q3 and Q4 is applied to the load circuit. That is, the complementary data lines DT,
The high level of the signal amplitude of DB is set to a low potential such as -2VBE. As a result, the signal amplitudes of the complementary data lines DT and DB at the time of the write operation are limited to a small value, which enables high-speed writing. Since writing to the memory cell is predominantly performed by the low level transmitted to the complementary data line DT or DB, there is no problem even if the high level is lowered to -2VBE as in this embodiment. That is, the gate potential of the storage MOSFET in the ON state of the memory cell is pulled out by the potential of the complementary data line set to the low level via the transmission gate MOSFET and switched to the OFF state, and as a result, it is in the OFF state. This is because the storage MOSFET is turned on and information is inverted and written.

The complementary data lines DT and DB are connected to a pair of common complementary data lines CDT and CDB through N-channel type MOSFETs MN3 and MN4 for column switches. Output terminals of a data input buffer IB for transmitting write data are connected to the common complementary data lines CDT and CDB. MOSFET MN of the above column switch
A column selection signal Y formed by a NOR gate circuit NOR2 composed of the same level conversion circuit as described above is supplied to the gates of 3 and MN4. Also in these NOR gate circuits NOR2, the predecode signal formed by the same predecoder circuit is supplied to form the column selection signal.

The complementary data lines DT and DB are connected to the bases of differential transistors Q5 and Q6 which form a sense amplifier. That is, this memory is of the column sense type. The common emitter of these differential transistors Q5 and Q6 has a switch MOS that receives the column selection signal Y.
It is connected to the constant current MOSFET MN2 via the FET MN1. At the gate of this constant current MOSFET MN2,
The constant voltage VIE is supplied to form a constant current.

The collectors of the differential transistors Q5 and Q6 are input to the current / voltage conversion circuit. That is, the collectors of the transistors Q5 and Q6 have a constant voltage VIE.
It is connected to the emitters of transistors Q7 and Q8 whose base receives a bias voltage formed by a resistor R2 in which a constant current formed by a MOSFET receiving the current flows. The emitters of these transistors Q7 and Q8 have constant current MOSFETs MN5 and MN5 that receive a constant voltage VIE.
MN7 is provided, and resistors R1 and R3 for current / voltage conversion are provided.
Is provided. A high level / low level corresponding to the storage information of the selected memory cell is output to the complementary data lines DT and DB. The differential transistors Q5 and Q6 which form the sense amplifier upon receiving the high level / low level
Is turned on / off. Then, the column selection signal Y
A constant current flows through the resistor R1 or R3 corresponding to the on / off state of the differential transistor via the MOSFET MN1 and the like that are turned on by. The read signal converted into the voltage signal by the resistors R1 and R3 is input to the output buffer OB through the emitter follower circuit including the transistors Q9 and Q10 and the emitter resistors R4 and R5. The output buffer OB is composed of an ECL circuit and outputs an ECL level output signal Do according to the voltage-converted read signal.

The transistors Q1 and Q2 constitute a write recovery circuit, which is turned on by a recovery signal WRC generated after the writing is completed and the write signal is transmitted so that the transistors Q1 and Q2 have a relatively large level difference. The complementary data lines DT and DB are reset at high speed. The recovery signal WRC is output via the emitter follower output transistor. Therefore, in the complementary data lines DT and DB, the transistors Q1 and Q2 are connected to the output transistor that forms the recovery signal WRC in the Darlington form, so that the bias level corresponding to the bias circuit (transistors Q3 and Q4) is obtained. -2
Brought to a level equal to VBE.

The effects obtained from the above embodiment are as follows. That is, by providing a level shift circuit in which resistors are provided between the base and the emitter and between the base and the collector between the bases of the NPN transistor and the PNP transistor that form the complementary push-pull output circuit, both transistors are constantly turned on. Set the level shift voltage within the range that does not cause the state. In this configuration, since a bias voltage is applied to both output transistors shallowly, an output signal that rapidly changes in response to a change in the output signal on the CMOS logic circuit side without generating a direct current in the output transistors in a steady state. The effect that can be obtained is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
The resistance means forming the level shift circuit may be formed of a diffusion layer formed in the semiconductor integrated circuit, a wiring layer, or a MOSFET.
The CMOS logic circuit may have two inputs, one input, or three or more inputs. Depending on the number of these inputs, P-channel MOSFET and N-channel MO
SFETs are provided respectively. The output circuit is used as an internal circuit having a large capacitive load, such as a word line forming a static RAM,
It may form an output signal to be sent to the outside of the semiconductor integrated circuit device. The static RAM has an ECL compatible TT for input and output as in the embodiment of FIG.
It may be L or CMOS compatible.
The BiCMOS circuit according to the present invention has the above Bi structure.
In addition to CMOS static RAM, BiCMO
It can be used for various semiconductor integrated circuit devices such as digital circuits such as S-configured gate arrays.

[0023]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, by providing a level shift circuit in which resistors are provided between the base and the emitter and between the base and the collector between the bases of the NPN transistor and the PNP transistor that form the complementary push-pull output circuit, both transistors are constantly turned on. Set the level shift voltage within the range that does not cause the state. In this configuration, since a bias voltage is applied to both output transistors shallowly, an output signal that rapidly changes in response to a change in the output signal on the CMOS logic circuit side without generating a direct current in the output transistors in a steady state. Can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a BiCMOS circuit according to the present invention.

FIG. 2 is a waveform diagram for explaining an example of the operation of FIG.

FIG. 3 is a circuit diagram showing an embodiment of a memory array section and its peripheral circuits in a static RAM having a BiCMOS structure to which the present invention is applied.

FIG. 4 is a circuit diagram showing an example of a conventional technique.

5 is a waveform diagram for explaining an example of the operation of the circuit of FIG.

[Explanation of symbols]

MC ... Memory cell, OB ... Output buffer, IB ... Input buffer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H01L 27/06 7342-4M H01L 27/06 321 J

Claims (2)

[Claims] 1. A CMOS logic circuit for receiving an input signal,
P-channel type MOS which constitutes this CMOS logic circuit
A level shift circuit provided between the FET side and the N-channel MOSFET side and provided with resistance means between the base and the emitter and between the base and the collector;
NPN that receives output signal from channel type MOSFET
A complementary push-pull output circuit comprising a transistor and a PNP transistor for receiving an output signal on the N-channel MOSFET side, and the level shift circuit is smaller than the sum of the output PNP transistor and the base-emitter voltage of the NPN transistor. A semiconductor integrated circuit device characterized by being set to a voltage. 2. A level shift circuit comprising resistance means provided between the base of the NPN transistor and the base of the PNP transistor which form the complementary push-pull output circuit, between the base and the emitter, and between the base and the collector. The output voltage of both transistors is applied to the bias voltage in the range that does not turn on constantly, and the P-channel type MO
CMO consisting of SFET and N-channel MOSFET
A semiconductor integrated circuit device comprising an S logic gate circuit.