JP2868245B2 - Semiconductor device and semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]

The present invention relates to a semiconductor device and a semiconductor memory, and more particularly to a semiconductor device and a semiconductor memory suitable for high speed and high integration.

[Prior art]

BiCMOS technology has been proposed as a technology for realizing a highly integrated and high-speed semiconductor device. As a basic semiconductor circuit to which the above technology is applied,
For example, see the IEICE Journal Vol.72 No.2 pp.197-20
8 ". FIG. 2A shows a circuit described in the above-mentioned document.
This circuit is an inverter circuit, and has two totem-pole-connected bipolar transistors Q1 and Q2 and an input signal I
It comprises a circuit composed of MOS transistors MP1 and MN1 for controlling the base potential of bipolar transistor Q1 according to N, and a circuit composed of MOS transistors MN2 and 3 for controlling the base potential of bipolar transistor Q2 according to the input signal IN. ing. Hereinafter, the operation of this circuit will be described with reference to FIG. First, consider the case where the input signal IN is at a low potential. At this time, the PMOS transistor MP1 is conducting, and the NMOS transistors MN1 and MN2 are not conducting. Therefore,
The base of transistor Q1 is driven to a high potential. As a result, the transistor Q is turned on, the load capacitance CL is charged, and the output signal OUT becomes high potential. Next, consider the case where the input signal IN changes from the above state to a high potential. At this time, the PMOS transistor MP1 is turned off, and the NMOS transistors MN1 and MN2 are turned on.
Therefore, the base of transistor Q2 is driven to the same potential as output signal OUT, that is, the high potential. As a result, the transistor Q2 becomes conductive, the load capacitance CL is discharged,
The output signal OUT has a low potential. As described above, in the present circuit, since the load capacitance CL is driven by the bipolar transistors Q1 and Q2 having a large load driving capability, a higher-speed operation is possible as compared with a circuit constituted only by CMOS. Also, a circuit composed of only bipolar transistors,
For example, it consumes less power than ECL (emitter coupled logic) and is suitable for high integration.

[Problems to be solved by the invention]

However, in the technique of FIG. 2A, the input signal amplitude is required to be the same as the power supply voltage, while the output signal amplitude is a voltage smaller than the power supply voltage by 2 VBE (VBE: base-emitter voltage of a bipolar transistor). There was a problem that only can be obtained. Hereinafter, the reason will be described with reference to FIGS. 2 (a) and 2 (b). When the input signal IN becomes low potential, the bipolar transistor Q1 becomes conductive as described above, the load capacitance CL is charged, and the output potential changes to high potential. However, when the output potential rises to about VD-VBE (VD: power supply potential on the high potential side), the base-emitter voltage of the bipolar transistor Q1 decreases, and the emitter current sharply decreases.
Therefore, the output potential rises at high speed up to the potential of VD-VBE, and it takes a very long time to rise to a potential higher than VD-VBE. Similarly, when the input signal IN changes to a high potential, the output potential rapidly drops to the potential of VS + VBE (VS: the power supply potential on the lower potential side), but it is extremely difficult to fall to a potential lower than that. It takes a lot of time. Therefore, as shown in FIG. 2 (b), the output signal amplitude that can be substantially secured when this circuit is driven in a high-speed cycle is VD−VS−2VBE, that is, 2V higher than the power supply voltage.
The value is smaller by BE (~ 1.4V). Next, consider the input signal amplitude necessary to prevent a steady through current from flowing through the MOS transistor. First, when the input signal IN is at a high potential, the PMOS transistor MP
In order to make 1 non-conductive, the gate-source voltage of the PMOS transistor MP1 needs to be almost 0V. That is, the high potential of the input signal IN needs to be substantially equal to VD. In order to make the NMOS transistor MN1 non-conductive when the input signal IN is at a low voltage, the NMOS transistor MN1 must be turned off.
It is necessary to make the gate-source voltage of N1 almost 0V.
That is, the low potential of the input signal IN needs to be substantially equal to VS. From the above, the amplitude of the input signal IN is almost VD
It turns out that -VS is necessary. As described above, in the related art, the input signal amplitude is required to be the same as the power supply voltage, but the output signal amplitude is only 2VBE smaller than the power supply voltage. When the device is miniaturized and the breakdown voltage of the device is reduced, the above problem becomes more serious. For example, when the power supply voltage is reduced to 3 V due to a decrease in element withstand voltage (see FIG. 2B)
Assuming that VBE is 0.7V, the input signal amplitude is required to be 3V, whereas the output signal amplitude is 1.6V, so that only about 50% of the power supply voltage can be obtained. 1.6V
However, there is a problem that an input signal having a 3V amplitude is necessary to generate the amplitude of the above, and the load of a circuit preceding the present circuit becomes unnecessarily heavy, making it difficult to increase the speed. SUMMARY OF THE INVENTION It is an object of the present invention to make the input signal amplitude equal to or smaller than the output signal amplitude, and to increase the output amplitude even when the element withstand voltage is reduced by miniaturization, and furthermore, to drive the load. An object of the present invention is to provide a semiconductor device having a large capacity. Another object of the present invention is to provide a semiconductor memory which can operate at high speed using the semiconductor device as described above.

[Means for Solving the Problems]

In order to achieve the above object, the present invention is configured as described in the claims. That is, in the present invention, the first and second transistors for controlling the first and second transistors connected to the output terminal, respectively.
And the second control circuit is connected so that the input signal is directly applied to the first control circuit and the input signal is applied to the second control circuit via the level shift circuit. Wherein the power supply potential on the low potential side of the first control circuit is set to a value lower than the power supply potential on the low potential side of the first control circuit. In the case where both of the transistors are bipolar transistors, the invention according to the second aspect is a case where one is a bipolar transistor and the other is a MOS transistor. According to a third aspect of the present invention, there is provided a semiconductor memory using the circuit according to the first or second aspect as a decoder circuit.

[Operation]

In the semiconductor device of the present invention, the power supply potential on the low potential side of the second control circuit is set lower than the power supply potential on the low potential side of the first control circuit. Therefore, the low potential of the output signal is lower than that of the conventional circuit, and the output signal amplitude can be increased. Further, since the input signal is applied to the second control circuit via the level shift circuit, a steady through current flows through the second control circuit even if the amplitude of the input signal is the same as the amplitude of the output signal. Never. Therefore, the input signal amplitude can be made equal to or smaller than the output signal amplitude, and the output amplitude can be increased even if the element withstand voltage is reduced due to miniaturization, and the load drive capability is increased. Becomes possible. In addition, when the above-described circuit is used as a decoder circuit of a semiconductor memory, the speed of the semiconductor memory can be increased, and power consumption can be reduced if the circuit is used at approximately the same speed as a conventional memory.

【Example】

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram of a first embodiment of the present invention, showing an example in which the present invention is applied to an inverter circuit. The circuit of this embodiment includes a bipolar transistor Q1 for charging the load capacitance CL and a MOS for controlling the base potential of the bipolar transistor Q1.
The current potential VS of the circuit composed of the transistors MP1 and MN1 and the power supply potential VS 'of the circuit composed of the MOS transistors MN2 and MN3 controlling the base potential of the bipolar transistor Q2 discharging the load capacitance CL are set to different potentials. And the point that the input signal supplied to the circuit for performing the above-mentioned discharging is given through a level shift circuit including bipolar transistors Q3 and Q4 and diodes D1 and D2.
This is different from the conventional example of FIG. In this circuit, for example, assuming that the withstand voltage of the MOS transistor is 3 V, VBE (0.7
An output amplitude larger by V), that is, an amplitude of 2.3 V can be obtained. Also, make the input signal amplitude the same as the output signal amplitude
Even at 2.3V, a steady through current does not flow through the MOS transistor. Hereinafter, the operation of this circuit will be described with reference to FIG. Here, as described above, the breakdown voltage of the MOS transistor is 3 V
The case will be described as an example. First, the power supply potential is set to 3.7V for VD, 1.4V for VS, and 0V for VS '. The high potential of the input signal IN is 3.7 V, and the low potential is 1.
Set to 4V. First, in the above circuit, a case where the input signal IN has a low potential, that is, 1.4 V is considered. At this time, the PMOS transistor MP1 is conducting, and the NMOS transistor MN1 is not conducting. Further, the gate potential of the NMOS transistor MN2 is such that the potential of the input signal IN is the bipolar transistor Q3.
2V
The potential drops by BE, and it is almost 0V. Therefore, the NMOS transistor MN2 is off.
Further, since the PMOS transistor MP1 conducts, the bases of the transistors Q1 and Q4 are driven to 3.7V. For this reason,
The load capacitance CL is charged by the transistor Q1, and the potential of the output signal rapidly rises to 3.0V according to the same discussion as the related art. At this time, the gate potential of the NMOS transistor MN3 is a potential obtained by level-shifting the base potential (3.7V) of the bipolar transistor Q4 by 2VBE, that is, 2.
3V, and the NMOS transistor MN3 is conducting. Therefore, the base potential of bipolar transistor Q2 is 0 V, and is in a non-conductive state. Next, from the above state, the input signal IN has a high potential, that is,
Consider the case where it changes to 3.7V. At this time, the PMOS transistor MP1 is off, and the NMOS transistor MN1 is on. The gate potential of the NMOS transistor MN2 is 2.3 V by the level shift circuit, and the NMOS transistor MN2 is in a conductive state. Therefore, the base of the transistor Q2 is driven to the same potential as the output signal, that is, the high potential. As a result, the transistor Q2 is turned on, the load capacitance CL is discharged, and the potential of the output signal rapidly decreases to 0.7 V according to the same discussion as the related art. At this time, the gate potential of the NMOS transistor MN3 is equal to the base potential (1.4V) of the bipolar transistor Q4.
The potential is a level shifted by 2 VBE, that is, almost 0 V, and the NMOS transistor MN3 is in a non-conductive state. As described above, the high potential of the output signal OUT in this circuit is 3.0 V, the low potential is 0.7 V, and the output signal amplitude is 2.3 V. Also, bipolar transistors Q3 and Q4, diode D
The signal level-shifted by the level shift circuit composed of D1 and D2 is applied to the MOS transistors MN2 and MN3.
Even if the input signal amplitude is 2.3V, which is the same as the output signal amplitude,
No steady through current flows through the transistor. As can be understood from the above description, according to the circuit of this embodiment, when the MOS transistors having the same withstand voltage are used, an output amplitude larger by VBE (0.7 V) than that of the conventional circuit can be obtained. Even if the input signal amplitude is the same as the output signal amplitude, it is possible to prevent a steady through current from flowing through the MOS transistor. Thus, for example, when the output signal amplitude of 1.6 V is required in the conventional circuit, the input signal amplitude needs to be 3.0 V, but in the present circuit, it can be reduced to 1.6 V. Therefore, the load on the preceding circuit is reduced, and high-speed operation is possible. Next, FIG. 3 is a diagram of a second embodiment of the present invention, showing an example in which the present invention is applied to a two-input NAND circuit. The configuration of this circuit is basically the same as that of the circuit of FIG. 1, and bipolar transistors Q1 and Q2 connected in totem pole connection and MOS transistors MP1, MP2 and MN1, which control the base potential of bipolar transistor Q1. A first control circuit composed of MN4 and a second control circuit composed of MOS transistors MN2, MN3 and MN5 for controlling the base potential of bipolar transistor Q2.
And three sets of level shift circuits including bipolar transistors Q3, Q4, Q5, diodes D1, D2, D3, and resistors R1, R2, R3 for applying a level-shifted signal to the second control circuit. It consists of. The first control circuit is constituted by a CMOS two-input NAND circuit, and only when the two input signals IN1 and IN2 are both at a high potential,
The base potential of the bipolar transistor Q1 is driven to a low potential. Further, the second control circuit includes a third control circuit connected in series.
MOS transistor MN2, MN5, MN3
Only when both IN1 and IN2 are at a high potential, the base potential of the bipolar transistor Q2 is driven to the same potential as the output signal potential.
Since the potential relationship is the same as that of the circuit shown in FIG. 1, the description is omitted. According to the circuit of this embodiment, the same effect as that of the embodiment of FIG. 1 can be obtained also in the NAND circuit, the load on the preceding circuit can be reduced, and high-speed operation can be performed. FIG. 4 shows a third embodiment of the present invention, in which the present invention is applied to a two-input NOR circuit. The configuration of this circuit is basically the same as that of the circuit of FIG. 1, except that a totem-pole-connected bipolar transistor is used.
A first control circuit composed of Q1, Q2 and MOS transistors MP1, MP3, MN1, MN6 for controlling the base potential of the bipolar transistor Q1, and MOS transistors MN2, MN3, MN7 for controlling the base potential of the bipolar transistor Q2 A second control circuit, and three sets of level shifts including bipolar transistors Q3, Q4, Q5, diodes D1, D2, D3, and resistors R1, R2, R3 for applying a level-shifted signal to the second control circuit. And a circuit. The first control circuit is configured by a CMOS two-input NOR circuit, and drives the base potential of the bipolar transistor Q1 to a low potential when either of the input signals IN1 and IN2 is at a high potential. Further, the second control circuit comprises two MOS transistors MN2 and MN7 connected in parallel,
It is composed of MN3 connected between S 'and input signals IN1, IN2
When either of the potentials is high, the base potential of the bipolar transistor Q2 is driven to the same potential as the output signal potential. In addition,
The potential relationship is the same as that of the circuit shown in FIG. According to the circuit of this embodiment, the same effect as that of the embodiment of FIG. 1 can be obtained also in the NOR circuit, the load on the preceding circuit can be reduced, and high-speed operation can be performed. As described above, FIGS. 1, 3 and 4 show examples in which the present invention is applied to a basic logic circuit. As can be seen from these examples, the bases of two totem-pole-connected bipolar transistors are shown. By applying the present invention to a circuit for controlling a potential, any logical function can be realized. Next, FIG. 5 shows a fourth embodiment of the present invention. In this circuit, an NMOS transistor MN10 is used in place of the bipolar transistor Q2 for discharging the load capacitance in the embodiments described above. Here, an example of an inverter circuit is shown. When a bipolar transistor is used, the low potential of the output signal can be rapidly reduced only to VS '+ VBE, whereas the potential can be rapidly reduced to VS' with an NMOS transistor. Therefore, in this embodiment, the amplitude of the output signal can be further increased by VBE (for example, 0.7 V) as compared with the embodiment of FIG. Further, the circuit configuration can be greatly simplified as shown in the figure, so that it is more suitable for higher integration than the embodiment of FIG. Next, FIG. 6 is a diagram of a fifth embodiment of the present invention, showing an example in which a two-input NAND circuit is configured in the embodiment of FIG. This embodiment has the same function as the embodiment shown in FIG. 3, but has a smaller number of components than the embodiment shown in FIG. 3, and is suitable for high integration. Next, FIG. 7 is a diagram of a sixth embodiment of the present invention, showing an example in which a two-input NOR circuit is configured in the embodiment of FIG. This embodiment has the same function as the embodiment shown in FIG. 4, but has a smaller number of constituent elements than the embodiment shown in FIG. 4, and is suitable for high integration. Next, FIG. 8 is a diagram showing a seventh embodiment of the present invention. In the embodiment of the two-input NOR circuit shown in FIG. 4, a wired OR is constituted by bipolar transistors Q3 and Q5 constituting a level shift circuit. And an example in which the number of elements is reduced. In this circuit, a wired OR circuit is formed by the bipolar transistors Q3 and Q5 forming the level shift circuit, so that the MOS transistor MN7 shown in FIG.
Is unnecessary. Further, the diode D3 and the resistor R3 of the level shift circuit can be shared with the diode D1 and the resistor R1, respectively, so that they become unnecessary. As described above, by using the bipolar transistors Q3 and Q5 for both level shift and wired OR, the number of elements can be reduced, and a circuit suitable for high integration can be configured. Next, FIG. 9 is a diagram showing an eighth embodiment of the present invention. In the embodiment of the two-input NOR circuit shown in FIG. 7, a bipolar circuit constituting a level shift circuit is formed in the same manner as the embodiment shown in FIG. An example is shown in which the transistors Q3 and Q5 form a wired OR to reduce the number of elements. In this circuit, the wired OR circuit is formed by the bipolar transistors Q3 and Q5 forming the level shift circuit, so that the MOS transistor MN11 in FIG. 7 is not required. Further, since the resistor R3 of the level shift circuit can be shared with the resistor R1, it becomes unnecessary. As described above, by using the bipolar transistors Q3 and Q5 for both level shift and wired OR, the number of elements can be reduced, and a circuit suitable for high integration can be configured. Next, FIG. 10 is a diagram showing a ninth embodiment of the present invention, in which a level conversion circuit and the present invention are combined. In this example, VB is
An output signal amplitude larger by E can be obtained. Hereinafter, the operation of this circuit will be described with reference to FIG. Here, VD = 3.7V, VS = 0.7V, VS '= 0V as the power supply potential
, And the high potential of the input signal IN is 3.7V and the low potential is 1.
Set to 4V. First, consider the case where the input signal IN has a low potential, that is, 1.4 V. At this time, the PMOS transistor MP4 is conducting. Further, the gate potentials of the NMOS transistors MN8 and MN10 are level-shifted by the bipolar transistors Q6 and Q7 to become 0.7V and 0V, respectively, so that the MN8 and MN10 are off. And PMOS transistor MP4
Conducts, the base of transistor Q1 becomes 3.7V
, And the high potential of the output signal OUT becomes 3.0 V. Next, consider a case where the input signal IN changes from the above state to a high potential, that is, 3.7V. At this time, the PMOS transistor MP4 is turned off, and the NMOS transistors MN8 and MN10 are turned on. Therefore, the low potential of the output signal OUT is VS '
, That is, 0V. As described above, according to the present embodiment, an output signal amplitude of 3.0 V can be obtained with an input signal amplitude of 2.3 V. In addition, since a through current does not constantly flow through the MOS transistor, a level conversion circuit suitable for low power consumption can be realized. In the above example, the level conversion from 2.3 V to 3.0 V has been described as an example. However, the power supply potential VD and the level shift amount of the input signal IN (bipolar transistor Q6, resistance R
By appropriately setting the level shift amount of the level shift circuit consisting of 4), an arbitrary amount of level conversion can be performed. Next, FIG. 11 is a diagram of a tenth embodiment of the present invention, in which the level conversion circuit of FIG. 10 has a logical function. Here, an example of a two-input NOR is shown. The operation is the same as that of the embodiment shown in FIG. According to this embodiment, a level conversion circuit with a logic function can be realized, and since a steady through current does not flow through the MOS transistor, it is suitable for low power consumption. Next, FIG. 12 is an eleventh embodiment of the present invention, showing an example in which the two-input NOR circuit shown in FIG. 9 is applied to a decoder / driver circuit of a bipolar / CMOS semiconductor memory SRAM. ing. This SRAM achieves high speed by reducing the voltage applied to the memory cell to about 2V and reducing the drive signal amplitude of the word line W and the bit line B. As described above, by applying the semiconductor device of the present invention to a decoder / driver circuit of a semiconductor memory such as an SRAM, the speed of the memory can be increased. Can be reduced. Hereinafter, the circuit operation of FIG. 12 will be described. In FIG. 12, W is a word line, B10 to Bn1 are bit lines, MC1 to MCn are memory cells, and XD1 is a decoder / driver circuit. Signals PDO1 and PDO2 obtained by pre-decoding the address signal are input to the decoder / driver circuit XD1. The decoder / driver circuit XD1 shown here is the two-input NOR circuit shown in FIG. 9, and drives the word line W to a high potential only when the signals PDO1 and PDO2 are both at a low potential. In the above circuit, the signals PDO1 and PDO2 are both at a low potential, the word line W is at a high potential, and the bit line selection signal YS
It is assumed that 1 is a high potential and the memory cell MC1 is selected.
Also, the transistor MNC11 of the memory cell MC1 is conducting,
Assuming that the MNC 10 is non-conductive, the transistor MNC 11 in the conductive state causes the information current to flow through the transistor QS11.
Flows through the transistors MNCT11 and MNC11. On the other hand, since the transistor MNC10 is off, no information current flows through the transistor QS10. Therefore, by detecting this current difference by the sense circuit S, the data output signal is detected.
DO is obtained. The above-described decoder / driver circuit can make the amplitude of the output signal equal to the amplitude of the input signal as described with reference to FIG. Therefore, if the word line drive signal requires 2 V as the amplitude, the conventional circuit
The amplitude of PDO1 and PDO2 required 3.4V, but this circuit requires 2V.
Is good. Therefore, the load on the pre-decoder circuit in the preceding stage can be reduced, and the speed of the pre-decoder circuit can be increased. Further, the above predecoder circuit can be realized by, for example, a wired OR circuit shown in FIG. FIG. 13 shows a case where the number of predecodes is four. This circuit consists of resistors R100 and R101, bipolar transistor Q
100, Q101, current source I100, multi-emitter transistor Q1
The outputs of the address buffers AB0 and AB1 composed of 02 and Q103 are connected as shown in the figure. One of the output signals O0 to O3 of this circuit has a low potential and the remaining three have a high potential in accordance with the address signals A0 and A1. For example, when the address input signals A0 and A1 are both at a high potential, only the output signal O0 is at a low potential and O1 to O3 are at a high potential. Since this circuit is configured by an ECL circuit, high-speed circuit operation can be realized. Next, FIG. 14 is a diagram of a twelfth embodiment of the present invention, in which the 2-input NOR type level conversion circuit of FIG. 11 is applied as the decoder / driver circuit XD1 in the embodiment of FIG. Is shown. Thus, by applying the two-input NOR type level conversion circuit shown in FIG. 11, the amplitudes of the predecode signals PDO1 and PDO0 can be further reduced as compared with the embodiment shown in FIG. That is, when 2 V is required as the amplitude of the word line drive signal, the circuit of FIG. 12 requires the predecode signals PDO1 and PDO2 to have an amplitude of 2.0 V, but this circuit requires only 1.3 V. For this reason, the load on the pre-decoder circuit in the preceding stage can be further reduced,
The speed of the predecode circuit can be increased.

【The invention's effect】

As described above, according to the present invention, the input signal amplitude can be equal to or smaller than the output signal amplitude, and the output amplitude can be increased even if the withstand voltage of the element is reduced by miniaturization. And a semiconductor circuit having a large load driving capability can be realized. Also, by applying the semiconductor circuit of the present invention to a decoder / driver circuit of a semiconductor memory, a number of excellent effects such as realization of a high-speed semiconductor memory can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram of a basic embodiment of the present invention, FIG. 2 is a circuit diagram and an operating voltage characteristic diagram of an example of the prior art, and FIG. 3 is an example in which the embodiment of FIG. 1 is applied to a two-input NAND circuit. FIG. 4 is an embodiment diagram showing an example in which the embodiment of FIG. 1 is applied to a two-input NOR circuit, and FIG. 5 is another basic embodiment diagram of the present invention. 6 is an embodiment showing an example in which the embodiment of FIG. 5 is applied to a two-input NAND circuit, and FIG. 7 is an embodiment showing an example in which the embodiment of FIG. 5 is applied to a two-input NOR circuit. , Eighth
FIG. 9 is an embodiment diagram showing an example in which the number of elements in the embodiment of FIG. 4 is reduced, FIG. 9 is an embodiment diagram showing an example in which the number of elements is reduced in the embodiment of FIG. FIG. 11 is an embodiment diagram showing an example in which the present invention is combined with a level conversion circuit. FIG. 11 is an embodiment diagram showing an example in which a logic function is added to the embodiment of FIG.
FIG. 13 is a diagram showing an example in which the present invention is applied to an SRAM decoder / driver circuit, FIG. 13 is a diagram showing a configuration example of a predecoder circuit of the embodiment in FIG. 12, and FIG. SRAM
FIG. 10 is an embodiment diagram showing another example applied to the decoder / driver circuit of FIG. <Description of References> MN1 to MN11 NMOS transistors MP1 to MP5 PMOS transistors Q1 to Q8 Bipolar transistors D1 to D3 Diodes MC1 to MCn Memory cells W Word lines B10 and Bn1 bits Line S: Sense circuit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Kunihiko Yamaguchi 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. (72) Kazuo Kanaya 1-1280 Higashi Koigakubo, Kokubunji-shi, Tokyo Hitachi Central Research Laboratory (72) Inventor Hiroaki Nambu 1-280 Higashi Koikekubo, Kokubunji City, Tokyo Inside the Hitachi, Ltd.Central Research Laboratories 72) Inventor Yoshiaki Sakurai 3681 Hayano Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd. (56) References JP-A-2-183494 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB Name) G11C 11/414 417

Claims (3)

(57) [Claims] A first bipolar transistor having an emitter connected to the output terminal; a second bipolar transistor having a collector connected to the output terminal; and a base potential of the first bipolar transistor controlled in accordance with an input signal. A bipolar MOS comprising: a first control circuit including at least one MOS transistor; and a second control circuit including at least one MOS transistor for controlling a base potential of the second bipolar transistor according to an input signal. In the mixed semiconductor device, an input signal is directly connected to the first control circuit, an input signal is connected to the second control circuit via a level shift circuit, and the second control circuit is connected to the second control circuit. The power supply potential on the low potential side of the control circuit is set to a value lower than the power supply potential on the low potential side of the first control circuit. Conductor device. 2. A bipolar transistor having an emitter connected to an output terminal and an N-type MOS having a drain connected to an output terminal.
An S transistor and at least one MO for controlling a base potential of the bipolar transistor according to an input signal;
A first control circuit including an S transistor; and a second control circuit for controlling a gate potential of the MOS transistor in accordance with an input signal.
And a control circuit including the control circuit of the first aspect, wherein the input signal is directly applied to the first control circuit, and the input signal is applied to the second control circuit via a level shift circuit. And the power supply potential on the low potential side of the second control circuit is set to a value lower than the power supply potential on the low potential side of the first control circuit. 3. A plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines, a first decoder circuit for selecting the word line, and a second decoder for selecting the bit line. And at least one of the first and second decoder circuits is configured using the semiconductor device according to claim 1 or 2. .