JPH03187517A - Level conversion circuit - Google Patents

Abstract

PURPOSE:To reduce energy consumption while maintaining high-speed operation possessed by an MOS current mirror circuit by reducing a through current flowing to a circuit while maintaining the switching velocity of a specified switching element. CONSTITUTION:At a level conversion circuit 2, since the ON resistance of an NMOS transistor 48 is set larger than the ON resistance of a PMOS transistor 46, the through current is reduced by the current mirror circuit. Since the gate potential of an NMOS transistor 53 is reduced to a power supply voltage V, the through current does not flow to the NMOS transistor 53. Since the gate of an NMOS transistor 49 is connected to a connecting point n2, the gate capacity of the NMOS transistor 49 is not changed and the switching velocity of the NMOS transistor 49 is not reduced even in case the ON resistance of the NMOS transistor 48 is set large. Thus, the energy consumption can be reduced while maintaining the high-speed operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a level conversion circuit, and particularly to a level conversion circuit that connects different types of logic circuits.

[Prior Art] Conventionally, for example, ECL (emitter coupled logic) circuits capable of high-speed operation and CMOS with low power consumption have been developed.
l! ! Various level conversion circuits have been developed for connecting the L path. Figure 5 shows how the ECL level signal is
FIG. 2 is a circuit diagram showing an example of a conventional level conversion circuit that converts to an S level fj number. The level conversion circuit shown in FIG.
This is shown in Publication No. 25, etc.

In FIG. 5, the ECLC circuit 1 is constituted by a bipolar ECL circuit, receives a signal A at the ECL level, and receives a complementary signal a at the ECL level.

Outputs ding. The level conversion circuit 2a is constituted by two current mirror circuits, receives complementary signals a and a at ECL level, and outputs complementary signals s and b at MOS level. The B i CMOS driver circuit 3 is composed of a combination of a bipolar transistor and a CMO8 circuit,
It is used to increase the drive capability of the complementary signals A and B output from the level conversion port 2a.

The ECL/< buffer circuit 1 is an NPN) transistor 11.
12 and resistor 13, and resistor 14, 15.19 and NPN transistor 16.17.
．． 18, and an ECL output circuit section including NPN transistors 20, 21, 22.23 and resistors 24.25.

Note that the configuration of the above ECL buffer circuit is as follows:
It is disclosed in Japanese Patent No. 60-21772'5.

Normally, the positive side power supply voltage V. C is set to Ov, and the negative side power supply voltage VEE is set to -4.5v or -5°2v. An ECL level signal A is applied to the base of the NPN transistor 11. Signal A (7) rHJ L
'Bevel, t-0, 9Vte, rLJ level is -1,
It is 7V. NP which is an emitter follower transistor
ECL level signals a and a are output from the emitters of N transistors 20 and 21, respectively. signal a
, a, the rHJ level of the emitter follower transistor base-emitter voltage V[IE
It becomes a level (approximately -0, 8V) that has decreased by a certain amount. signal a.

The rLJ level V of a is determined by the following equation.

VL-VCCI-RV[SE-(1) where,
(2) is the current value of the current flowing through the resistor 14 or 15, and R is the resistance value of the resistor 14 or 15. Further, the base of the NPN transistor 17 is given a U quasi-voltage V81S. The input threshold value is determined by the reference voltage Vaa. N
A reference voltage VCS+ is applied to the bases of the PN transistors 12.1g and 22.23. Base t\Lightning voltage CS+
The current values of the current switch section and the ECL output circuit section are determined by.

The level conversion circuit 2a is a PMOS transistor 46.4
7 and an NMOS transistor 48.49, and a PMOS transistor 50.5.
1 and a second current mirror including NMOS transistors 52 and 53. PMOS) transistor 46
, 51 is supplied with signal a, and the gate of PMOSI transistor 47.50 is supplied with signal d.

PMOSI-transistor 47 and NMOS transistor 4
A MOS level signal is output from the connection point with 9, and P
A MOS level signal T is output from the connection point between the NMOS transistor 51 and the NMOS transistor 53. The rHJ level of signals S and b is the power supply voltage VCC, and rLJ
The level is power supply voltage VEE.

The B1CMOS driver circuit 3 is a first CM including a PMOS) transistor 32 and an NMOS) transistor 33.
OS inverter and PMOS transistors 38 and N
a second CMOS inverter including a MOS transistor 39; a first base control circuit including NMOS transistors 34 and 35; a second base control circuit including NMOS transistors 40 and 41;
It consists of ゜37.42.43. NPN) transistor 3
6, 37 and NPN transistors 42, 43 are each totem pole connected between the positive side power supply voltage VCC and the negative side power supply voltage VEE.

The first CMOS inverter switches the NPN transistor 36, and the second CMOS inverter switches the NPN transistor 36.
The transistor 42 is switched and driven. The first base control circuit controls the base current of the NPN transistor 37, and the second base control circuit controls the base current of the NPN transistor 4.
Controls the base current of 3. NPN transistor 36
and NPN) from the connection point with transistor 37
OS level signal C is output, and NPN) transistor 4
B1CMO from the connection point between 2 and NPN transistor 43
A signal C at S level is output. The rHJ level of the signal C1C is -0.4v, and the rLJ level is -4°1v or -4.8v.

Next, the operation of the circuit shown in FIG. 5 will be explained.

Here, signal A at ECL level is at rHJ level (-0
, 9V) to the rLJ level (-1, 7V) will be described.

When the ECL signal A applied to the base of NPN) transistor 11 changes from rHJ level to rLJ level,
The collector potential of the NPN transistor 16 changes from the rLJ level to the rHJ level, and the NPN transistor 17
Conversely, the collector potential changes from the rHJ level to the "L" level. As a result, the emitter potential (signal a) of the NPN transistor 21 changes from the rLJ level to the rHJ level, and the emitter potential 71i (signal a) of the NPN transistor 2o changes from the rHJ level to the rLJ level. As mentioned above, the rHJ level of signals a and a is a level that is lower than the power supply voltage VCC by the base-emitter voltage VBE of the emitter follower transistor (approximately -0,
8V). Further, the rLJ level of the 31 signals is determined by the above equation (1). If the amplitude of the output of the current switch section is IV, the rLJ level of the signals a and a is 1.8V.

As mentioned above, the signal a changes from the rLJ level to the rHJ level, and the signal a changes from the rHJ level to the "L" level, so the PMOS transistors 46 and 51 turn on.
PMOS) transistors 47 and 50 are turned off. Also, N
MO3I-transistor 49 is turned on and NMOS transistor 53 is turned off. Therefore, the level conversion is! 1
The signal output from path 2a changes from the rLJ level (power supply voltage VE E ) to the rHJ level (power supply voltage vcc), and the signal biiFHJL and bell (power supply voltage VCC
) changes from h' to rLJ level (power supply voltage VE E ). The levels of these signals S and B are MOS levels. Therefore, conversion from ECL level to MOS level has been performed.

Since the level conversion circuit 2a is constituted by MOS transistors, its driving ability is not very large. Therefore, it is necessary to increase the drive capability of the next-stage B1CMOS driver circuit 3. As mentioned above, when the signal changes from the rLJ level (power supply voltage vEE) to the rHJ level (power supply voltage Vcc), the PMOS)
Transistor 38 is turned off, and NMOS transistor 39 .
40 turns on. As a result, NMOS transistor 4
1 turns off. Therefore, the NPN transistor 42 is turned off and the NPN transistor 43 is turned on. As a result, the signal C output from the B i CMOS driver circuit 3 becomes rLJ level (VEE+0°4V).

On the other hand, as described above, when the signal changes from the rHJ level (power supply voltage Vcc) to the rLJ level (power supply voltage vEE), the PMOS transistor 32 turns on, and the NM
OS transistors 33 and 34 are turned off. This results in
NMOS transistor 35 is turned on. Therefore, N
The PN transistor 36 turns on, and the NPN) transistor 3
7 is off. As a result, the signal C output from the B i CMOS driver 4-way 3 reaches the rHJ level (Vcc
0°4V).

Conversely, the ECL level signal A changes from "L" level to rHJ.
Even when the level changes, the same operation will cause
The signal a becomes the rLJ level of the ECL level, and the signal a becomes the rHJ level of the ECL level. As a result, the signal becomes the rLJ level of the MOS level, and the signal becomes the MOS level.
The rHJ level is S level. Furthermore, signal C is B1
The rLJ level is the CMOS level, and the signal C becomes B1C.
The rHJ level is at the MOS level.

As described above, logic level conversion is performed between the ECL circuit and the MOS circuit.

[Problem to be solved by the invention] However, in the above conventional level conversion circuit,
When the signal a shown in FIG. 5 changes from the rLJ level to the rHJ level and the signal a changes from the rHJ level to the rLJ level, the PMOS transistor 46 and the N
Both MOS transistors 48 are turned on. in this case,
Since the on-resistance of the NMOS transistor 48 is small, a large through current flows through the PMOS transistor 46 and the NMOS transistor 48 from the terminal receiving the power supply voltage VCC to the terminal receiving the power supply voltage VEE. This piercing a
In order to reduce the current, it is conceivable to set the on-resistance of the NMO5) transistor 48 to be large. However, in this case, by increasing the on-resistance of the NMOS transistor 48, the gate capacitance of the NMO3I transistor 49 increases. Therefore, when the signal a reaches the rLJ level, the speed at which the NMOS transistors 48 and 49 are turned on becomes slow.

Furthermore, since the NMOS transistor 52 acts as a MOS diode, a voltage of yE (+vth) is applied to the gate of the NMOS transistor 53. Here, vt
h is the threshold voltage.

Therefore, NMO3) transistor 53 turns on weakly and P
MOS transistor 51 and NMO3) transistor 5
A through current flows through 3.

When the tA゛ level changes from the "H" level to the rLJ level and the signal a changes from the rLJ level to the rHJ level, a through current similarly flows from the terminal receiving the power supply voltage VCC to the terminal receiving the power supply voltage VEE. flows.

As described above, the conventional level conversion circuit has a major problem regarding the power consumption.

An object of the present invention is to obtain a level conversion circuit capable of reducing power consumption while maintaining high speed.

[Means for Solving the Problems] A level conversion circuit according to a first invention converts complementary signals of first and second logic levels in a first type of logic circuit to a second type of logic circuit. a level conversion circuit for converting signals into complementary signals of third and fourth logic levels, a first input terminal receiving a signal of the first or second logic level; a signal of the second or first logic level; a second input terminal for outputting a signal of the third or fourth logic level; a second output terminal for outputting fj of the fourth or third logic level; , 3rd
a first potential source for supplying a potential corresponding to a logic level; a second potential source for supplying a mold surface corresponding to a fourth logic level; first, second, third and fourth potential sources; and fifth, sixth, seventh and eighth switch elements. The first, second, third and fourth switch elements each have a control terminal and become conductive when the control terminal is provided with a mold surface corresponding to the second logic level.

The fifth, sixth, seventh and eighth switch elements are control g4.
It has a J terminal and becomes conductive when a potential corresponding to the first logic level is applied to the control filter terminal t-I.

The first and fifth switch elements are connected in series between the first potential source and the second potential source via the first connection point. The third and seventh switch elements are connected to a first potential source and a second potential source.
is connected in series with the potential source of 1lfJ via the second connection point. The second and sixth switch elements are connected in series between the first potential source and the second potential source via the first output terminal.

The fourth and eighth switch elements are connected in series between the first voltage source and the second voltage source via the second output terminal. Control terminals of the first and fourth switch elements are connected to the first input terminal. Control terminals of the second and third switch elements are connected to the second input terminal. A control terminal of the sixth switch element is connected to the first connection point. 8th
A control terminal of the switch element is connected to the second connection point.

Control terminals of the fifth and seventh switching elements are connected to the first potential source. The fifth and seventh switch elements are formed such that the on-resistances of the fifth and seventh switch elements are larger than the on-resistances of the other switch elements.

The level conversion circuit according to the second invention, like the level conversion circuit according to the first invention, has a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first , a second potential source, first, second, third and fourth switching elements, and fifth, sixth, TS7 and eighth switching elements.

The first to eighth switch elements of the level conversion circuit according to the second invention are the first to eighth switch elements of the level conversion circuit according to the first invention.
- Connected in the same way as the eighth switch element. However, in the level conversion circuit according to the second invention, the fifth
and control terminals of the fifth and seventh switching elements, in place of the fifth and seventh switching elements being formed such that the on-resistance of the seventh switching element is larger than the on-resistance of the other switching elements. By applying a predetermined potential to the on-resistances of the fifth and seventh switching elements, the on-resistances of the fifth and seventh switching elements are set to be larger than the on-resistances of the other switching elements.

[Operation] According to the first and second inventions, since the on-resistances of the fifth and seventh switching elements are set large, the first
The through current flowing from the potential source to the second potential source via the first and fifth switching elements or via the third and seventh switching elements is reduced.

In this case, the control terminal of the sixth switch element is connected to the first connection point and is not connected to the control terminal of the fifth switch element. Further, the control terminal of the eighth switch element is connected to the second connection point, and is not connected to the control terminal of the seventh switch element. Therefore, the fifth
Even if the on-resistance of the seventh switching element is large, the capacitances connected to the control terminals of the sixth and eighth switching elements do not change. Therefore, the switching speeds of the sixth and eighth switching elements do not become slow.

Further, when the first switch element is non-conductive, the potential of the first connection point becomes equal to the potential of the second potential source. Therefore, the sixth switch element becomes sufficiently non-conductive. Therefore, from the first potential source to the second potential source, the second and sixth potential sources are connected.
No through current flows through the switch element.

On the other hand, when the third switch element is non-conductive, the potential of the second connection point is equal to the potential of the second potential source by 8. Therefore, the eighth switch element becomes sufficiently non-conductive.

Therefore, no through current flows from the first potential source to the second potential source via the fourth and eighth switching elements.

[Example] Hereinafter, an example of the present invention will be described in detail using the drawings.

FIG. 1 is a circuit diagram showing the configuration of a level conversion open circuit according to an embodiment of the present invention.

In FIG. 1, ECL buffer circuit 1 and B1CM
The configuration of the OS driver circuit 3 is ECL shown in FIG.
The configurations are the same as those of the buffer circuit 1 and the B1CMOS driver circuit 3. The ECL buffer circuit 1 receives the signal A at the ECL level and outputs complementary signals a and a at the ECL level. Normally, the positive side voltage Vcc is set to OV, and the negative side power supply voltage VEE is -4.5V or -5.2V.
set to V.

Level conversion circuit 2 includes PMO3+- transistor 46.4
7, 50, 51 and NMOS transistors 48, 49
, 52.53. PMO3+- transistor 46,
The gate of 51 is connected to node n1 and PMO3+-
The gates of transistors 47 and 50 are connected to node n1. Node n1 receives signal a from ECL buffer circuit 1, and node n1 receives signal a from ECL buffer circuit 1. PMOS) transistor 47 and NMOS)
From node N1, which is the connection point with transistor 49, to MOS
A level signal is output, and the PMOS transistor 51
Note N, which is the connection point between and the NMOS transistor 53
1 to MOS level fJsub is output. signal,
The rHJ level of b is the power supply voltage VCC, and the rLJ level is the power supply voltage VEE.

The drain of the PMOS transistor 46 is the drain of the NMOS transistor 48 and the drain of the NMOS transistor 49
connected to the gate. NMOS transistor 48
A power supply voltage vcC is applied to the gate of. On the other hand, P.M.
The drain of the OS transistor 50 is connected to the drain of the NMOS transistor 52 and the gate of the NMOS transistor 53. A power supply voltage VCC is applied to the gate of the NMOS transistor 52.

The sources of the PMOS transistors 46, 47, 50, and 51 are supplied with the power supply voltage ■. , and a power supply voltage VEE is applied to the sources of the NMOS transistors 48, 49, 52, and 53. The NMOS transistor 48.52 has a large gate length (L) and a small gate width (W) so that its on-resistance is sufficiently larger than that of the NMOS transistor 46.50. is formed.

The B1CMOS driver 4-way 3 receives the complementary signals S and b at the MOS level and outputs the complementary signal C9C at the B1CMOS level.

Next, the operation of the circuit shown in FIG. 1 will be explained.

First, signal A at ECL level is at rHJ level (-0,9
The operation when changing from V) to rLJ level/L, (-1,7V) will be described. In this case, similarly to the ECL buffer circuit shown in FIG.
The signal a changes from J level to rHJ level, and signal a changes to rH level.
Changes from J level to rLJ level.

As mentioned above, since the signal i is at the rHJ level and the signal a is at the rLJ level, in the level replacement circuit 2, the PMO5
) The transistors 46 and 51 are turned on and the PMOS transistors 47 and 50 are turned off. NMOS) transistor 4B,
The gate of 52 has a power supply of 7fi7fVcc! j, so those transistors are always on. Therefore, the drain voltage α at the connection point n2 between the PMOS transistor 46 and the NMOS transistor 48 is
The potential is determined by the on-resistance ratio of 8. Since the NMOS transistor 48 is formed such that the on-resistance of the NMOS transistor 48 is sufficiently larger than the on-resistance of the PMO transistor 46, the potential of the drain, which is the connection point n2, is the power supply voltage (2). The rHJ level is close to . As a result, the NMO3) transistor 49 is turned on, and the signal S changes from the rHJ level to the rLJ level.

Also, since the PMOS transistor 50 is off and the NMOS transistor 52 is on, the connection point n2 between the PMOS transistor 50 and the NMOS transistor 52
The potential of the drain becomes the rLJ level of the power supply voltage VEE. Therefore, the NMOS transistor 53 is turned off, and the signal S changes from the rLJ level to the rHJ level.

Here, since both the PMOS transistor 46 and the NMOS transistor 48 are on, the power supply voltage VCC
A through current flows from the receiving terminal to the terminal receiving power supply voltage VEE through these transistors 46 and 48.

However, since the on-resistance of the NMOS transistor 48 is set to be sufficiently larger than the on-resistance of the PMO transistor 46, the through current is reduced by U (U) compared to the current mirror circuit shown in FIG.

Also, since the gate potential of the NMOS transistor 53 decreases to the power supply voltage VEE, the NMOS transistor 53
No through current flows through 3.

In this way, according to the level conversion four-way 2 shown in FIG. 1, it is possible to reduce power consumption.

Note that the gate of the NMOS transistor 49 is connected to the connection point "1".
Therefore, even if the on-resistance of the NMO3) transistor 48 is set to be large, the gate capacitance of the NMO5) transistor 49 does not change. Therefore, NMOS)
The switching speed of transistor 49 does not decrease.

Similarly, the gate of the NMOS transistor 53 is connected to the connection point n
2, even if the on-resistance of the NMOS transistor 52 is set to a large value, the gate capacitance of the NMOS transistor 53 does not change. Therefore, NMO3)
The switching speed of transistor 53 does not decrease.

As mentioned above, the signal is at rHJ level (power supply voltage Vc
c) When the signal reaches rLJ level (power supply voltage VEE), the B1CMOS driver circuit 3 shown in Figure 5
Similarly, the signal C output from the B1CMOS driver circuit 3 is at the rLJ level (vE E +0.4 V).
fA'), signal C is at "H" level (Vc c 0
．． 4V).

When the ECL level signal A changes from the rLJ level to the rHJ level, the signal a
becomes the rLJ level of the ECL level, and the signal a becomes the ECL level.
Level r becomes HJ level.

As a result, the signal C becomes the rLJ level of the MOS level, and the signal C becomes the rHJ level of the MOS level.Furthermore, the signal C becomes the rLJ level of the B1CMOS level, and the signal C becomes the rHJ level of the B1CMOS level. As described above, connection with the ECL open circuit MO3 circuit is possible.

In this way, according to the level conversion circuit 2 of FIG.
Is it possible to reduce power consumption while maintaining the high-speed operation of the MOS current mirror circuit shown in the figure? It becomes iI ability.

FIG. 2 is a circuit diagram showing the configuration of a level conversion circuit according to a second embodiment of the invention.

The level conversion circuit 11 circuit 20 shown in FIG. 2 is different from the level conversion circuit 2 shown in FIG.
Instead of applying 1t of power supply voltage VCC to the gates of 52 gates, M' that changes in accordance with power supply voltage VEE is applied to those gates.
This is the point at which the l potential VREF is given. This reference potential VRE
When the power supply voltage VEE fluctuates, F fluctuates by the same voltage as the fluctuation.

That is, the difference between the reference potential VREF and the power supply voltage VEE is always one stroke. Also, this reference potential V.

EF is set to a predetermined potential between power supply voltage VCC and power supply voltage VEE. NMOS transistor 48.5
Since the gate voltage applied to the NMOS transistor 48 of the level conversion circuit 20 is lower than the power supply voltage VCC,
, 52 are even larger than the on-resistances of the NMOS transistors 48 and 52 in the level conversion circuit 2 of FIG. Therefore, the through current is further reduced.

In addition, since the gate potential of the NMOS transistors 48 and 52 follows changes in the power supply voltage VEE, the power supply type LllV
There is an advantage that the through current does not increase even if EE changes.

FIG. 3 is a circuit diagram showing the configuration of a level conversion circuit according to a third embodiment of the present invention.

The level conversion circuit 21 of FIG. 3 is different from the level conversion circuit 2 of FIG. This is the point connected to .

When signal a changes to rLJ, PMOS transistor 4
6 is turned on, and the NMOS transistor 48 is turned on weakly. In this case, since the gate voltage of the NMOS transistor 48 is lower than the power supply voltage VCC, the on-resistance of the NMOS transistor 48 is large. Therefore, NMOS
The through current flowing through transistor 48 is reduced.

Also, when signal a changes to rHJ level, PMOS)
The transistor 46 is turned off, and the NMOS transistor 48 is strongly turned on. In this case, since the PMOS transistor 46 is off, no through current flows through the NMOS transistor 48.

In this way, according to the level conversion circuit 21 of FIG. 3, the gate voltage of the NMOS transistor 48 when the signal a changes to the rLJ level is set lower than the power supply voltage VCC. Also, when the signal level changes to the rLJ level, the gate voltage of the NMOS transistor 52 is the power supply voltage V
It is set lower than CC. As a result, signal a becomes “
NMOS transistor 48 when changed to “L” level
Since the on-resistance of the NMOS transistor 48 of the level conversion circuit 2 shown in FIG. 1 is even larger than that of the NMOS transistor 48 of the level conversion circuit 2 shown in FIG. 1, the through current is further reduced. Similarly, the signal T
The on-resistance of the NMOS transistor 52 when the voltage changes to the "L" level is the N in the level conversion circuit 2 in FIG.
Since it is even larger than the on-resistance of the MOS1-transistor 52, the through current is further reduced.

The level conversion circuits shown in FIGS. 1, 2, and 3 can be used, for example, in each part of B1CMOS-RAM. The 810MO8-RAM was developed to obtain a large-capacity memory that can operate at high speed and consumes little power, and is constructed by combining a bipolar element and a CMOS circuit. Figure 4 shows a general RAM (Ra
nd.

The configuration of m Access Memory is shown below.

In FIG. 4, in a memory cell array 60, a plurality of word lines and a plurality of bit lines are arranged to intersect with each other, and a memory cell is provided at each intersection of the word line and the bit line. . X address buffer
One word line of the memory cell array 60 is selected by the decoder 62, one bit line of the memory cell array 60 is selected by the Y address buffer decoder 64, and the memory cells provided at the intersections of these word lines and bit lines are selected. is selected. Data is written to the selected memory cell, or data stored in the selected memory cell is read. Whether to write or read data is R.
/W selected by control circuit 66. R/W control circuit 6
6 operates in response to an externally applied write enable signal WE and chip select signal C8.

When writing data, manually inputted data Din is manually inputted to the selected memory cell via the R/W control circuit 66.

Furthermore, in reading data, in particular, the data stored in the selected memory cell is detected and amplified by the sense amplifier 68, and is taken out to the outside as output data Dout via the data output buffer 70.

In the B i CMO5-RAM, the memory cell array is composed of MOS transistors, and peripheral circuits such as address buffers and decoders are composed of bipolar transistors or a combination of bipolar transistors and MOS transistors.

The circuits of FIGS. 1, 2, and 3 can be used, for example, in the address buffers included in X address buffer decoder 62 and Y address buffer decoder 64. In this case, signal A applied to ECLCS buffer 1 is an address signal.

Further, the circuits shown in FIGS. 1, 2, and 3 can be used for the CS buffer, WE buffer, and Din buffer included in the R/W control circuit 66. The CS buffer is a circuit that receives the chip select signal C8, and is a circuit that receives the chip select signal C8.
The buffer is a circuit that receives the write enable signal WE, and the Din buffer is a circuit that receives human input data Din.

In this way, by applying the level conversion circuits shown in FIGS. 1, 2, and 3 to B i CMO8-RAM, it is possible to further reduce power consumption while maintaining high speed. becomes.

Note that the level conversion circuit of the present invention is a BiCMO3-R
It can be used not only for AM but also for various other circuits.

Further, the present invention can be applied not only to a level conversion circuit for coupling an ECL circuit and an MO3 circuit, but also to a level conversion circuit for coupling other types of logic circuits.

[Effects of the Invention] As described above, according to the first and second inventions, the on-resistances of the fifth and seventh switching elements are set larger than the on-resistances of the other switching elements, and and the 8th
Since the control terminals of the switch elements are connected to the first and second connection points, respectively, the through current flowing through the level conversion circuit is reduced while maintaining the switching speed of the sixth and eighth switch elements. . Therefore, it is possible to reduce power consumption while maintaining the high speed performance of the level conversion circuit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a level conversion circuit according to a first embodiment of the present invention. FIG. 2 is a circuit diagram showing the configuration of a level conversion circuit according to a second embodiment of the invention. FIG. 3 is a circuit diagram showing the configuration of a level conversion circuit according to a third embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of a RAM to which the level conversion circuit of the present invention can be applied. FIG. 5 is a circuit diagram showing the configuration of a conventional level conversion circuit. In the figure, 1 is an ECL buffer circuit, 2, 20.21
is a level conversion circuit, 3 is a B1CMOS driver circuit, 4 is a level conversion circuit,
6.47, 50.51 are PMOS transistors, 48.
49.52.53 are NMOS transistors, VCC is the positive power supply voltage, VE node, n2. n2 is a connection point. In each figure, the same reference numerals indicate the same or corresponding parts. Agent Dai Tgo Masuo Channel 4

Claims (2)

[Claims] (1) A level conversion circuit that converts complementary signals at the first and second logic levels in the first type of logic circuit to complementary signals at the third and fourth logic levels in the second type of logic circuit. a first input terminal receiving a signal at the first or second logic level, a second input terminal receiving a signal at the second or first logic level, and the third or fourth logic. a first output terminal for outputting a signal at the fourth or third logic level, a second output terminal for outputting a signal at the fourth or third logic level, and a second output terminal for supplying a potential corresponding to the third logic level. a first potential source for supplying a potential corresponding to the fourth logic level; a second potential source for supplying a potential corresponding to the fourth logic level; and a control terminal, the control terminal being supplied with a potential corresponding to the second logic level. first, second, third, and fourth switching elements that become conductive when the logic level is applied, and control terminals, and fifth and fourth switch elements that become conductive when a potential corresponding to the first logic level is applied to the control terminals; 6, seventh and eighth switching elements, the first and fifth switching elements are connected in series between the first potential source and the second potential source via a first connection point. connected, the third and seventh switching elements are connected in series between the first potential source and the second potential source via a second connection point, and the second and sixth switching elements are The switch element is connected in series between the first potential source and the second potential source via the first output terminal, and
and an eighth switch element is connected in series between the first potential source and the second potential source via the second output terminal, and a control terminal of the first and fourth switch elements. is connected to the first input terminal, control terminals of the second and third switch elements are connected to the second input terminal, and a control terminal of the sixth switch element is connected to the first input terminal.
a control terminal of the eighth switch element is connected to the second connection point, control terminals of the fifth and seventh switch elements are connected to the first potential source, The level conversion circuit, wherein the fifth and seventh switching elements are formed such that on-resistances of the fifth and seventh switching elements are larger than on-resistances of other switching elements. (2) A level conversion circuit that converts complementary signals at the first and second logic levels in the first type of logic circuit to complementary signals at the third and fourth logic levels in the second type of logic circuit. a first input terminal receiving a signal at the first or second logic level, a second input terminal receiving a signal at the second or first logic level, and the third or fourth logic. a first output terminal for outputting a signal at the fourth or third logic level, a second output terminal for outputting a signal at the fourth or third logic level, and a second output terminal for supplying a potential corresponding to the third logic level. a first potential source for supplying a potential corresponding to the fourth logic level; a second potential source for supplying a potential corresponding to the fourth logic level; and a control terminal, the control terminal being supplied with a potential corresponding to the second logic level. first, second, third, and fourth switching elements that become conductive when the logic level is applied, and control terminals, and fifth and fourth switch elements that become conductive when a potential corresponding to the first logic level is applied to the control terminals; 6, seventh and eighth switching elements, the first and fifth switching elements are connected in series between the first potential source and the second potential source via a first connection point. connected, the third and seventh switching elements are connected in series between the first potential source and the second potential source via a second connection point, and the second and sixth switching elements are The switch element is connected in series between the first potential source and the second potential source via the first output terminal, and
and an eighth switch element is connected in series between the first potential source and the second potential source via the second output terminal, and a control terminal of the first and fourth switch elements. is connected to the first input terminal, control terminals of the second and third switch elements are connected to the second input terminal, and a control terminal of the sixth switch element is connected to the first input terminal.
A control terminal of the eighth switch element is connected to the second connection point, and a predetermined potential is applied to the control terminals of the fifth and seventh switch elements. and a level conversion circuit, wherein the on-resistance of the seventh switch element is set to be larger than the on-resistance of the other switch elements.