JPH0575034A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit device, working speed of which is increased and which has a level conversion circuit of single input. CONSTITUTION:In a level conversion circuit in a single input, a MOSFET switch-controlled according to the amplified output of an output signal is mounted in a parallel type to a comparatively small MOSFET switch-controlled according to an input signal as the base extracting MOSFET of an output transistor forming the output signal on the high level side, and worked as a variable resistance element. Accordingly, the output signal is altered without delay in response to the input signal by the small MOSFET when the change of the signal is started, and the output signal is amplified and fed back, thus extracting the base of the output transistor at high speed after the output signal lowers to a fixed level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a bipolar CMOS (hereinafter referred to as a bipolar CMOS) having a level conversion circuit for receiving an ECL (emitter coupled logic) signal and converting it to a CMOS level. B
The present invention relates to a technology effectively applied to a static RAM (random access memory) having a configuration of iCMOS.

[0002]

2. Description of the Related Art Bi as a high-speed static RAM
There is a CMOS circuit technology in which the memory array section is configured as a CMOS circuit and the peripheral circuit is an ECL compatible BiCMOS circuit. As such a static RAM having a BiCMOS configuration, 1990 "VLSI Circuit Symposium Proceedings", page 40, page 42 (1990 Symposium
on VLSI Circuits P.40, P41).

[0003]

As a level conversion circuit for converting an ECL level signal into a CMOS level, there is a one-input level conversion circuit as shown in FIG. In this circuit, the base of the output transistor T1 can be quickly pulled out by increasing the size of the N-channel MOSFET Q6. However, if the size of this MOSFET Q6 is increased, the P-channel type MOSFETs Q2 and N
There is a contradictory relationship that the load of the drive circuit formed of the channel type MOSFET Q5 becomes heavy and the switch control of the MOSFET Q6 becomes slow and the operation becomes slow. An object of the present invention is to provide a semiconductor integrated circuit device equipped with a one-input level conversion circuit for speeding up.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0004]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, in the one-input level conversion circuit, as a base extraction MOSFET of an output transistor that forms an output signal on the high level side, a switch control is performed according to an amplified output of the output signal with respect to a relatively small MOSFET that is switch controlled according to the input signal. The above MOSFETs are provided in parallel to operate as a variable resistance element.

[0005]

According to the above means, when the signal starts changing, the output signal is changed without delay by the small MOSFET corresponding to the input signal, and the output signal is amplified and fed back to reduce the output signal to a constant level. Later, the base of the output transistor can be pulled out at high speed.

[0006]

1 is a circuit diagram of an embodiment of a one-input level converting circuit according to the present invention. Each circuit element in the figure is a known BiC together with other circuit elements that constitute a BiCMOS static RAM as described later.
It is formed on one semiconductor substrate such as single crystal silicon by MOS technology. In the circuit diagram, a MOSFET having an arrow on its channel (back gate) portion is a P-channel type, and is distinguished from an N-channel MOSFET without an arrow. This is shown in FIG.
The same is true for.

Although not particularly limited, an input signal DIN input through an input buffer that receives an ECL level external signal is supplied between the source and gate of the P-channel MOSFET Q1. That is, MOSFET Q1
With its source connected to the ground potential point of the circuit, the ECL level input signal DIN whose reference potential is the ground potential of the circuit is supplied between the gate and source of the MOSFET Q1. An N-channel MOSFET Q6 is provided between the drain of the MOSFET Q1 and the power supply voltage VEE of the circuit. This MOSFE
The size of the TQ6 is the above P-channel type MOSFE.
It is formed smaller than TQ1. For example, MOSFE
When the size of TQ1 is 70, the size of MOSFET Q6 is formed as small as 10.

MOSFETQ corresponding to input signal DIN
In order to perform complementary switch control of 1 and the MOSFET Q6, a P-channel MOSFET Q3 to which the input signal DIN is supplied between the gate and the source is provided similarly to the above. On the drain side of the MOSFET Q3, an N-channel type MOSFET Q4 that acts as a resistance element is provided as a load by connecting the gate and the drain. The inverted signal of the input signal DIN formed by the MOSFET Q3 is the N-channel MOSFET Q5.
Is supplied to the gate. Between the MOSFET Q5 and the input terminal DIN, a P-channel type MOSFET Q2 whose gate is supplied with the reference voltage VREF is provided. The MOSFET Q2 does not amplify the source-grounded gate input like the MOSFETs Q1 and Q3, but performs the gate-grounded source input amplification. As a result, the MOSFETs Q2 and Q5 operate complementarily in response to the input signal DIN, and the MOSFETS
It forms the switch control signal for TQ6.

The output signal formed by the MOSFETs Q1 and Q6 is supplied to the base of the output transistor T1 which forms an output signal on the high level (ground potential) side. A transistor T2 forming a totem-pole push-pull circuit is provided between the transistor T1 and the negative power supply voltage VEE. At the base of the transistor T2, an N-channel MOSFET Q8 formed by the MOSFETs Q3 and Q4 and receiving the inverted amplified signal of the input signal DIN, and an N-channel type MOSFET Q8 formed by the MOSFETs Q2 and Q5 and receiving the amplified signal in phase with the input signal DIN are provided. The output signal of the push-pull circuit composed of the channel type MOSFET Q7 is supplied. Although not particularly limited, in this embodiment, the drain of the MOSFET Q7 is connected to the output terminal and uses the output signal dout. Instead of this configuration, the drain of the MOSFET Q7 may be connected to the ground potential of the circuit. M
The OSFET Q9 is for always supplying a minute constant current to the input terminal, and is used, for example, as a constant current load of an emitter follower transistor that forms an input buffer.

In this embodiment, in order to increase the operation speed, the MOSFET Q6 is connected in parallel with an N-channel type M.
An OSFET Q12 is provided. This MOSFET Q1
2 is provided for speeding up the extraction of the base potential of the transistor T1, and its gate has an output signal dou
The output signal of the inverter circuit receiving t is supplied. This inverter circuit is a P-channel MOSFET Q1.
0 and N-channel MOSFET Q11,
The inverted amplified signal of the output signal dout is formed to form the MOS
Switch control of the FET Q12.

The operation of this embodiment circuit is as follows. When the input signal DIN is at the low level, the P-channel type MOSFETs Q1 and Q3 are in the ON state and the P-channel type MOSFET Q2 is in the OFF state. At this time, since the N-channel MOSFET Q5 is turned on by the ON-state of the P-channel MOSFET Q3, the MOSFET Q6 is in the OFF state. The transistor T1 is turned on according to the ON state of the P-channel MOSFET Q1, and the N-channel type M according to the ON state of the P-channel MOSFET Q3.
Since the OSFET Q8 is turned on, the transistor T
2 is in the off state, and the output signal dout is at a high level like the ground potential of the circuit.

When the input signal DIN changes from low level to high level, P-channel MOSFETs Q1 and Q
3 is turned off and the P-channel MOSFET Q2 is turned on. The P-channel type MOSF
In response to the change of ETQ3 to the off state, MOSFETQ
5 is turned off, and the output signals of the MOSFETs Q2 and Q5 also change from low level to high level.
At this time, since the MOSFET Q6 is formed to have a relatively small size, it immediately responds to the amplified output by the MOSFETs Q2 and Q5 and starts drawing the base potential of the transistor T1.

The base potential of the transistor T1 decreases in accordance with the ON state of the MOSFET Q6. At the same time M
The OSFET Q7 is turned on, the high level of the output signal dout is transmitted to the base of the transistor T2, the transistor T2 is turned on, and the output signal dout is changed from the high level to the low level. At this time, MOSF
The ETQ8 is turned off together with the MOSFET Q5. The level change of the output signal dout from the high level to the low level is caused by the inverter circuit (Q10, Q
It is amplified by 11) and transmitted to the MOSFET Q12. When this amplified output signal exceeds the threshold voltage of the MOSFET Q12, the MOSFET Q12 becomes
After a delay of 6, the transistor is turned on and the base potential of the transistor T1 is extracted together with the MOSFET Q6. As a result, the output signal dout changes from high level to low level at high speed.

On the contrary, when the input signal DIN changes from the high level to the low level, the P-channel MOSFET Q
1 and Q3 turned on, P-channel MOSFET Q
2 is switched off. P channel type M
In response to the change of the OSFET Q3 to the ON state, the MOSF
ETQ5 changes to ON state, MOSFETs Q2 and Q5
Output signal also changes from high level to low level. At this time, since the size of the MOSFET Q6 is relatively small, the MOSFETs Q2 and Q5 are
Immediately reacts to the amplified output by and is switched to the off state.

The base potential of the transistor T1 rises according to the ON state of the P-channel MOSFET Q1. At the same time as the MOSFET Q6, the MOSFET Q7 is turned off, and the P-channel MOSFET is replaced.
N-channel MOSFET Q depending on the ON state of Q3
8 is turned on to pull out the base potential of the transistor T2 and turn it off. This causes the output signal dou
t is changed from low level to high level. The level change of the output signal dout from the low level to the high level is amplified by the inverter circuit (Q10, Q11) and transmitted to the MOSFET Q12. MOSFET Q1
2 is turned off after the MOSFET Q6. As a result, the output signal dout changes from the high level to the low level.

FIG. 3 shows a BiCM to which the present invention is applied.
A circuit diagram of an embodiment of a memory array section and its peripheral circuits in a static RAM having an OS structure is shown. In the figure, one word line W, one word line selection circuit, one memory cell MC, and a pair of complementary data lines D.
T, DB, and their load circuits, write recovery circuits, sense amplifiers, and column switch circuits are exemplarily shown. Also, an output circuit corresponding to the sense amplifier,
The data input circuit IB is also drawn.

The memory cell MC is a P channel type MOS.
CMOS consisting of FET and N-channel MOSFET
CMO in which the input and output of the inverter circuit are cross-connected
S latch circuit, its input / output node and complementary data line D
It is composed of a transmission gate MOSFET for address selection provided between T and DB. The operating voltage on the high level side of the memory cell is the ground potential of the circuit, and the operating voltage on the low level side is the constant voltage V formed by the voltage generating circuit.
EM is used. The memory cell of this embodiment is a complete C
Although a memory cell having a MOS structure is used, a high resistance load made of a polysilicon layer or the like may be used instead of the P-channel MOSFET. The high resistance load is set to have a high resistance value such that the memory level accumulated in the gate of the N-channel MOSFET passes a minute current that is not lost by the drain leak current. Therefore, the high resistance load has a significantly different meaning from the load in the normal ratio type inverter circuit. When such a high resistance load is used, the size (occupied area) of the memory cell can be significantly reduced. However, when the operating voltage on the low level side of the memory cell is set to a value such as -3.2V to -3.3V, the operation of the memory cell may become unstable. Use is preferable.

The gate of the transmission gate MOSFET of the memory cell is connected to the corresponding word line. The word line W is selected by the word line drive circuit NOR1. In addition, since the above-mentioned embodiment has the NAND structure, in order to obtain the NOR (nor) gate structure as in this embodiment, the P-channel type MOSFET is connected in series and
The channel type MOSFETs may be arranged in parallel. Also, the power supply voltage, the high level side is the ground potential of the circuit,
The low level side may be set to VEE or VEM. For example, if the NOR gate circuit NOR1 is used as three inputs and the output signals of three predecode circuits corresponding to a 7-bit address signal are supplied by synthesis, one word line is selected from 128 word lines. Such a circuit configuration can be realized, and a word line selection signal is formed from one word line selection circuit in which the above three types of predecode signals are all set to the low level.

The complementary data lines DT and DB are provided with data line load means composed of P-channel type MOSFETs MP1 and MP2. These MOSFETs MP1, MP
2 has its conductance formed relatively small in consideration of the write characteristic, and the constant voltage VEM is constantly supplied to its gate. These MOSFETs MP1, MP
P channel type MOSFET with a relatively large conductance in the source and drain paths of 2.
Source and drain paths of MP3 and MP4 are provided in parallel. By supplying the write control signal WE1 to the gates of the MOSFETs MP3 and MP4, the MOSFETs MP3 and MP4 are turned on except during the write operation. In other words, the MOSFETs MP3 and MP4 are M
Together with the OSFETs MP1 and MP2, they constitute a data line load during a read operation. That is, at the time of the read operation, the signal amplitude of the complementary data line is limited to realize high speed read. On the other hand, in the write operation, the control signal WE1 turns off the MOSFETs MP3 and MP4 having the relatively large conductance, and the loads on the complementary data lines DT and DB are composed of the MOSFETs MP1 and MP2 having only a small conductance. By doing so, the signal amplitude of the write data transmitted to the complementary data line is increased and high speed writing is performed.

A bias voltage level-shifted by the diode-connected transistors Q3 and Q4 is applied to the load circuit. That is, the complementary data lines DT,
The high level of the signal amplitude of DB is set to a low potential such as -2VBE. As a result, the signal amplitudes of the complementary data lines DT and DB at the time of the write operation are limited to a small value, so that high speed writing becomes possible. Since writing to the memory cell is predominantly performed by the low level transmitted to the complementary data line DT or DB, there is no problem even if the high level is lowered to -2VBE as in this embodiment. That is, the gate potential of the storage MOSFET in the ON state of the memory cell is pulled out by the potential of the complementary data line set to the low level via the transmission gate MOSFET and switched to the OFF state, and as a result, it is in the OFF state. This is because the storage MOSFET is turned on and information is inverted and written.

The complementary data lines DT and DB are connected to a pair of common complementary data lines CDT and CDB via N-channel type MOSFETs MN3 and MN4 for column switches. Output terminals of a data input buffer IB for transmitting write data are connected to the common complementary data lines CDT and CDB. MOSFET MN of the above column switch
A column selection signal Y formed by a NOR gate circuit NOR2 composed of the same level conversion circuit as described above is supplied to the gates of 3 and MN4. Also in these NOR gate circuits NOR2, the predecode signal formed by the same predecoder circuit is supplied to form the column selection signal.

The complementary data lines DT and DB are connected to the bases of differential transistors Q5 and Q6 which form a sense amplifier. That is, this memory is of the column sense type. The common emitters of these differential transistors Q5 and Q6 have a switch MOS that receives the column selection signal Y.
It is connected to the constant current MOSFET MN2 via the FET MN1. At the gate of this constant current MOSFET MN2,
The constant voltage VIE is supplied to form a constant current.

The collectors of the differential transistors Q5 and Q6 are input to the current / voltage conversion circuit. That is, the collectors of the transistors Q5 and Q6 have a constant voltage VIE.
It is connected to the emitters of transistors Q7 and Q8 whose base receives the bias voltage formed by the resistor R2 in which the constant current formed by the MOSFET receiving the current flows. The emitters of these transistors Q7 and Q8 have constant current MOSFETs MN5 and MN5 that receive a constant voltage VIE.
MN7 is provided and resistors R1 and R3 for current / voltage conversion are provided.
Is provided. A high level / low level corresponding to the storage information of the selected memory cell is output to the complementary data lines DT and DB. The differential transistors Q5 and Q6 which form the sense amplifier upon receiving the high level / low level
Is turned on / off. Then, the column selection signal Y
A constant current flows through the resistor R1 or R3 corresponding to the on / off state of the differential transistor via the MOSFET MN1 and the like that are turned on by. The read signal converted into the voltage signal by the resistors R1 and R3 is input to the output buffer OB through the emitter follower circuit including the transistors Q9 and Q10 and the emitter resistors R4 and R5. The output buffer OB is composed of an ECL circuit and outputs an ECL level output signal Do according to the voltage-converted read signal.

The transistors Q1 and Q2 constitute a write recovery circuit, which is turned on by a recovery signal WRC generated after the writing is completed, and the write signal is transmitted to have a relatively large level difference. The complementary data lines DT and DB are reset at high speed. The recovery signal WRC is output via the emitter follower output transistor. Therefore, in the complementary data lines DT and DB, the transistors Q1 and Q2 are connected to the output transistor that forms the recovery signal WRC in the Darlington form, so that the bias level corresponding to the bias circuit (transistors Q3 and Q4) circuit is set. -2
Brought to a level equal to VBE.

In the static RAM as described above, an ECL level address signal supplied from the outside,
The control signal and write data are fetched through a buffer such as an emitter follower and converted into a CMOS level by the level conversion circuit shown in FIG.

The operational effects obtained from the above embodiment are as follows. That is, in the one-input level conversion circuit, as a base extraction MOSFET of an output transistor that forms an output signal on the high level side, a switch control is performed according to an amplified output of the output signal with respect to a relatively small MOSFET that is switch controlled according to the input signal. The above MOSFETs are provided in parallel to operate as a variable resistance element. In this configuration, at the start of signal change, the output signal is changed by the small MOSFET in response to the input signal without delay, and the output signal is amplified and fed back to reduce the output signal to a certain level and then the base of the output transistor. It is possible to obtain the effect that the drawing can be performed at high speed.

The invention made by the present inventor has been specifically described based on the embodiments, but the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
MOSFET Q4 constituting the load of MOSFET Q3
May be replaced with a constant current MOSFET whose gate is constantly given a predetermined bias voltage. M
The OSFET Q9 is not directly related to the level conversion operation and can be omitted. The input signal may be at the ECL level and may have a small signal amplitude similar to that. The conductivity type of the MOSFET may be inversely configured according to the signal level and the operating voltage. For example, when the operating voltage is a positive voltage and the input signal is a signal with a small amplitude based on the ground potential of the circuit, a P-channel type M
The OSFET and the N-channel MOSFET may be replaced with each other. The transistor may be replaced with a PNP transistor. INDUSTRIAL APPLICABILITY The level conversion circuit according to the present invention can be used in various semiconductor integrated circuit devices such as a static type RAM having a BiCMOS structure as described above and a digital circuit such as a gate array having a BiCMOS structure.

[0028]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in the one-input level conversion circuit, as a base extraction MOSFET of an output transistor that forms an output signal on the high level side, a switch control is performed according to an amplified output of the output signal with respect to a relatively small MOSFET that is switch controlled according to the input signal. These MOSFETs are provided in parallel and act as a variable resistance element, so that a small MO is generated at the start of signal change.
The output signal can be changed without delay in response to the input signal by the SFET, and the extraction current of the base of the output transistor is added to this output signal by the feedback amplification signal, so that high-speed level conversion operation can be performed. it can.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a level conversion circuit according to the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional level conversion circuit.

FIG. 3 is a circuit diagram showing an embodiment of a memory array section and its peripheral circuits in a static RAM having a BiCMOS structure to which the present invention is applied.

[Explanation of symbols]

MC ... Memory cell, OB ... Output buffer, IB ... Input buffer.

Claims (2)

[Claims] 1. A first MOSFET in which an input signal having a relatively small signal amplitude is supplied between a gate and a source, and a second MOSFET in which a reference voltage is supplied to the gate and the input signal is supplied to a source. , The third M is supplied with the input signal between the gate and the source and forms an inverted amplified signal.
OSFET and a fifth MOSFET that receives the inverted amplified output signal and is complementarily controlled with the second MOSFET.
And a sixth MO which receives the output signals of the second and fifth MOSFETs and is complementarily controlled with the first MOSFET.
An SFET, a first output transistor for receiving the output signals of the first and sixth MOSFETs, a second output transistor in the totem pole type push-pull configuration with the first output transistor, and a fifth output transistor. MOSFET
Of the first and second output transistors and the seventh and eighth MOSFETs that receive the input signal of the second MOSFET and the input signal of the sixth MOSFET, respectively, and form the drive signal of the second output transistor by the output signal. An inverter circuit for receiving an output signal to form an inverted signal, and a level conversion circuit including an twelfth MOSFET in parallel with the sixth MOSFET for receiving the output signal of the inverter circuit. Semiconductor integrated circuit device. 2. The input signal having a relatively small signal amplitude is an input signal corresponding to an ECL level, and the level conversion circuit forms an output signal of a CMOS level. Semiconductor integrated circuit device.