JPH05167029A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce a MOS semiconductor device by a method wherein a low- concentration impurity region is formed, an insulating film applied on the whole surface, a high-concentration impurity is diffused through patterned opening parts to form impurity regions of a concentration higher than that of the low- concentration impurity region and the impurity regions are taken out through the patterned opening parts to form electrodes. CONSTITUTION:A P-type impurity region 10 is formed in one part of an N-type silicon substrate 1. Then, a silicon oxide film 2 is formed on the whole surface of the substrate 1 and a polycrystalline silicon film formed thereon is patterned to form into gates 3. An ion-implantation is performed using the gates 3 as masks to form offset layers 4. A channel part is 11. Then, an insulating film 6 is applied on the whole surface. Then, an etching of opening parts 7 which are used as source and drain take-out ports is performed, a high-concentration impurity is diffused through the opening parts 7 and a source 5 and a drain 5 are formed. An Al film is vapor-deposited in the opening parts 7 to form electrodes 8. Accordingly, a MOS semiconductor device can be made smaller by the amount of a matching margin 9 than a conventional MOS semiconductor device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a MOS transistor having a high breakdown voltage structure and a technique particularly effective when applied to the manufacturing method thereof.

[0002]

2. Description of the Related Art A conventional semiconductor device and its manufacturing method will be described with reference to FIGS. FIG. 9 is a cross-sectional view of a high breakdown voltage MOS transistor manufactured by a conventional manufacturing method, and FIG. 10 is a plan view thereof. In addition,
FIG. 9 shows an AA cross section of FIG.

In the conventional method of manufacturing a semiconductor device,
First, an insulating film 2 and a polycrystalline silicon film are formed on a silicon substrate 1 and patterned with a photoresist to form the polycrystalline silicon film as a gate 3. Next, impurities are doped using the gate 3 as a mask to form an offset layer 4. The source and drain 5 are formed by selectively doping the offset layer 4 with a photoresist at a higher concentration than the above-mentioned impurity doping. Next, the insulating film 6 was covered and the opening 7 for taking out the source and the drain was formed with a photoresist, and the Al layer was vapor-deposited to form the source and the drain taking-out electrode 8. Reference numeral 11 is a channel section.

[0004]

In the above-mentioned conventional device, the offset layer 4 is selectively doped with impurities at a high concentration to form the source and drain 5, and then the insulating film 6 is covered to form the source and drain 5. Since the opening 7 is formed to serve as the source / drain lead-out electrode 8, the alignment margin 9 between the source / drain 5 and the source / drain lead-out electrode 8 is required. Therefore, the size of the MOS transistor is large.

The present invention has been made in order to overcome the above-mentioned problems of the conventional technique, and an object thereof is to reduce the size of a MOS semiconductor device having an offset structure.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, a step of forming an insulating film is provided after the step of forming a low-concentration impurity region which is an offset region, and an impurity having a higher concentration than the low-concentration impurity region is provided through an opening formed by patterning the insulating film. Forming a region,
Further, an extraction electrode for the impurity region is formed from the patterned opening.

[0009]

According to the above-mentioned means, since the high-concentration impurity region is formed from the patterned opening and the extraction electrode is formed in the opening, the high-concentration impurity regions of the source, drain and source are It is not necessary to provide a margin for alignment with the drain extraction electrode, and it is possible to reduce the size of the MOS.

The structure of the present invention will be described below together with an embodiment applied to a MOS type semiconductor device having a high breakdown voltage structure.

In all the drawings for explaining the embodiments, parts having the same functions are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0012]

[Embodiment] (Embodiment 1) FIG.
Will be explained. 1 to 3 are cross-sectional views showing the steps of this example, in which the left half shows an NMOS and the right half shows a PMOS. FIG. 4 is a plan view of FIG.

First, as shown in FIG. 1, a P-type impurity region 10 is formed in a part of the N-type silicon substrate 1. Next, a silicon oxide film 2 is formed on the entire surface of the substrate 1, and the polycrystalline silicon film formed on the silicon oxide film 2 is patterned with a photoresist to form a gate 3. The gate 3 is used as a mask for ion implantation to form an offset layer. 4 is formed. 11
Is the channel section.

Next, as shown in FIG. 2, the entire surface is covered with the insulating film 6.

Next, as shown in FIG. 3, the opening 7 serving as the source / drain extraction port is etched to diffuse the high-concentration impurities from the opening 7 to form the source / drain 5.
To form. Then, Al is deposited on the opening 7 to form the electrode 8.

According to this embodiment described above, since the electrode is formed in the opening where the high-concentration impurity region is formed, the source / drain extraction electrode 8 and the source / drain of the high-concentration impurity region are formed. There is no need to provide a margin for alignment with 5. As is clear from a comparison between FIG. 3 of this example and FIG. 9 showing the conventional example, according to this example, it is possible to obtain a MOS semiconductor device that is reduced by the alignment margin 9 from the conventional one. It is possible.

As shown in the plan view of FIG. 4, the source / drain 5 formed in this example has only the size of the opening 7, so that the source / drain current Ids is the same as the conventional one. It gets smaller. To cope with this, in order to increase the source / drain current Ids, it is necessary to simply lengthen the opening 7 in the direction parallel to the gate 3. Since it expands, the margin must be observed, and the intended purpose of the present invention, that is, reduction, cannot be achieved.

Next, an example in which the source / drain current Ids is made larger than that of the first embodiment in the present invention will be described as a second embodiment.

(Second Embodiment) A second embodiment will be described with reference to FIGS. 5 to 7 are cross-sectional views showing the steps of this example,
FIG. 8 is a plan view of FIG. 7. In addition, FIG. 6 is B- of FIG.
FIG. 7 shows the B section, and FIG. 7 shows the AA section of FIG.

First, as shown in FIG. 5, a silicon oxide film 2 is formed on the entire surface of an N-type silicon substrate 1, and a polycrystalline silicon film formed on the silicon oxide film 2 is patterned by a photoresist to form a gate 3. Then, ions are implanted using the gate 3 as a mask to form an offset layer 4.

Next, as shown in FIG.
2 diffuses the high-concentration impurity into the portion adjacent to the opening 7 (the portion indicated by the line BB in FIG. 8), and the source / drain 1
3 is formed.

Next, as shown in FIG. 7, the insulating film 6 is formed on the entire surface.
Opening 7 that covers the
Etching is performed to diffuse high-concentration impurities from the opening 7 to form the source / drain 5. Then, Al is vapor-deposited in the opening 7 to extract the source / drain electrodes 8.
To form.

As shown in the plan view of FIG. 8, the source and drain 13 obtained by the process of FIG. 6 and the source and drain 5 obtained by the process of FIG.
Is integrated by the subsequent heat treatment, and the lengths of the opposing portions of the source and the drain 5 are not limited to the size of the opening, and the same length as the conventional one can be obtained. The drain current Ids is obtained.

In comparison with the first embodiment, this embodiment is shown in FIG.
The number of processes such as photoresist formation is increasing. However, since this step can be performed simultaneously with the high-concentration MOS high-concentration impurity diffusion step of the normal MOS formed on the same substrate together with the high-voltage MOS, the step of FIG. 6 does not substantially increase the number of steps. I won't.

The invention made by the present inventor has been specifically described based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example,
In each of the above embodiments, the channel portion is sandwiched to form the low concentration impurity region, but it is also possible to form this low concentration impurity region only on one side of the channel and apply it to a MOS transistor having a high resistance on one side. is there.

In the above description, the case where the semiconductor device is mainly applied to the high breakdown voltage type MOS semiconductor device has been described. However, the present invention is not limited to this, and any semiconductor device having an offset region can be applied.

[0027]

The effects obtained by the representative ones of the inventions disclosed in this application will be briefly described as follows.

That is, according to the present invention, a high breakdown voltage MOS
In a semiconductor device having an offset region such as a semiconductor device, it is possible to eliminate the alignment margin between the contact portion and the source / drain portion, which has been conventionally required.
The semiconductor device can be downsized.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first step of Example 1 of the present invention.

FIG. 2 is a sectional view showing a second step of the first embodiment of the present invention.

FIG. 3 is a sectional view showing a third step of Example 1 of the present invention.

FIG. 4 is a plan view of FIG.

FIG. 5 is a sectional view showing a first step of Example 2 of the present invention.

FIG. 6 is a sectional view showing a second step of Example 2 of the present invention.

FIG. 7 is a sectional view showing a third step of Example 2 of the present invention.

FIG. 8 is a plan view of FIG.

FIG. 9 is a cross-sectional view of a semiconductor device obtained by a conventional manufacturing method.

FIG. 10 is a plan view of FIG.

[Explanation of Codes] 1 ... Silicon substrate, 2 ... Insulating film, 3 ... Gate, 4 ... Offset layer, 5, 13 ... Source, drain, 6 ... Insulating film,
7 ... Openings, 8 ... Source and drain extraction electrodes, 9 ...
Margin to fit.

Claims (3)

[Claims] 1. A step of forming a low-concentration impurity region on the substrate on at least one side of the channel portion by using a part of a main surface of a semiconductor substrate as a channel portion, an opening formed by coating the substrate with an insulating film and patterning A method of manufacturing a semiconductor device, which comprises a step of forming an impurity region having a higher concentration than the low-concentration impurity region from a portion, and a step of forming an electrode of the impurity region from the patterned opening. 2. A step of forming a low-concentration impurity region on the substrate on at least one side of the channel part by using a part of a main surface of a semiconductor substrate as a channel part, and an opening formed later in the low-concentration impurity region. Adjacent to the step of forming an impurity region having a higher concentration than the low concentration impurity region at a location parallel to the gate electrode, covering the substrate with an insulating film,
A method of manufacturing a semiconductor device, comprising: a step of forming an impurity region having a higher concentration than the low concentration impurity region from a patterned opening, and a step of forming an electrode of the impurity region from the patterned opening. 3. An opening formed by patterning a part of the main surface of a semiconductor substrate as a channel part, having a low concentration impurity region on at least one side of the channel part on the substrate, and patterning the low concentration impurity region. And a semiconductor device having an electrode and a high-concentration impurity region higher than the low-concentration impurity region are formed from the opening in a self-aligned manner.