JPH05165741A - Input/output processor - Google Patents

Abstract

PURPOSE:To read asynchronous data without considerably increasing hardware quantity. CONSTITUTION:AND between asynchronous data which is read from an asynchronous circuit 10 in a channel part 1 with mask information from a mask register 12 is taken in an AND circuit 13. Data where all bits except for a target bit are fixed to a prescribed value is outputted to a driver 15 by the AND circuit 13. A parity generation circuit 14 generates a parity bit based on data from the AND circuit 13, and outputs it to the driver 15. It outputs asynchronous data where all the bits from the AND circuit 13 except for the target bit are fixed to the prescribed value and the parity bit from the parity generation circuit 14 to an external part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output processing device, and more particularly to a read process for reading data from an asynchronous circuit to a synchronous circuit in the input / output processing device.

[0002]

2. Description of the Related Art In an input / output processing device, a synchronous circuit portion that operates in synchronization with an internal clock and an asynchronous circuit that operates asynchronously with the internal clock are mixed. The synchronous circuit is a part controlled by the microprogram, and the asynchronous circuit is often present in the channel part controlling the input / output interface.

When a microprogram reads asynchronous data from an asynchronous circuit in a channel section, a plurality of signal lines are read by a single microinstruction. In this case, it is often the case that a part of the plurality of signal lines is needed by the microprogram, and these part of the signal lines are uncertain when the microprogram reads an asynchronous signal. There is no such thing.

However, since there is a high possibility that other undesired signal lines that are read at the same time as some of these signal lines change during reading, that is, become indefinite, the problem of delay time occurs and the read data is lost. It is likely to cause a parity error.

Therefore, conventionally, as shown in FIG. 4, after synchronizing the asynchronous data read from the asynchronous circuit 80 of the channel section 8 by the synchronizing circuit 81, it is processed as a synchronizing signal. That is, the synchronizing signal synchronized by the synchronizing circuit 81 is selected by the selecting circuit 82, and the synchronizing signal and the parity bit generated by the parity generating circuit 83 are output from the driver 84 to the synchronizing circuit (not shown). There is.

In such a conventional input / output processing device, since the asynchronous data read from the asynchronous circuit 80 is synchronized by the synchronizing circuit 81, a target signal line and another non-target signal line are connected. In order to synchronize all of them, synchronization circuits for the number of signal lines are required, which has a disadvantage of causing a large increase in hardware amount.

[0007]

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks of the prior art, and provides an input / output processing device capable of reading asynchronous data without significantly increasing the hardware amount. For the purpose of provision.

[0008]

The input / output processing device according to the present invention is an input / output processing device connected to an external device through an input / output interface that operates asynchronously with a clock signal in the device itself in the channel section. A means for fixing the data other than the target data among the data from the output interface to a predetermined value according to preset mask information, and a generating means for generating a parity bit of the data other than the target data fixed to the predetermined value. Is provided.

[0009]

An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the asynchronous data read from the asynchronous circuit 10 of the channel unit 1 is selected by the selection circuit 11, and the selected asynchronous data is ANDed with the mask information from the mask register 12 by the AND circuit 13. That is, the AND circuit 13 fixes all bits other than the target bit to a predetermined value (“0” or “1”) and outputs the fixed value to the driver 15.

The parity generation circuit 14 generates a parity bit from asynchronous data in which all bits other than the target are fixed to a predetermined value, and outputs the parity bit to the driver 15. Therefore, the driver 15 outputs to the synchronizing circuit (not shown) of the input / output processing device the asynchronous data in which all the bits other than the target are fixed to a predetermined value and the parity bit thereof.

FIG. 2 is a block diagram showing the system configuration of an embodiment of the present invention. In the figure, the input / output processing device 4
The channels 1a to 1d are connected to the input / output devices 3a to 3d via the corresponding input / output control devices 2a to 2d, respectively. Further, the channel portions 1a to 1d are the common channel portion 6
It is connected to the micro program controller 5 via.

FIG. 3 is a block diagram showing the detailed arrangement of the input / output processing apparatus according to the embodiment of the present invention. In the figure, the microprogram controller 5 is a buffer gate 5
1, 52, 68, 69 and the data bus 100 are connected to the channel common unit 6.

The write data register (MDBW) 61 of the common channel unit 6 holds the write data to the channel unit 1, and the flip-flop (CWC) 62 holds the write instruction signal 101 when writing to the channel unit 1. ..

A register (CNR) 63 holds a register number 102 for selecting a register or data inside the channel section 1, and a channel number register (TCN) 6
4 holds a channel number 103 for instructing which one of a plurality of existing channel units 1 is selected. Here, the register 63 holds information indicating the information to be read in the case of reading from the channel unit 1, and the information indicating the register or flip-flop group to be written in the case of writing to the channel unit 1. Retained.

Further, the read data register (MDBR) 6
Reference numeral 5 holds the read data from the channel section 1, and the flip-flop (CRC) 66 holds the read instruction signal 104 when reading from the channel section 1.

The I / O interface control circuit 10 of the channel section 1 is a circuit for controlling an asynchronous I / O interface 7 for connecting to a corresponding input / output control device (not shown). In addition, the I / O interface control circuit 10
Includes a signal or a flip-flop that operates asynchronously with the clock inside the channel section 1. here,
The I / O interface 7 has a strobe line for data transfer, a data line, and other control lines.

The selection circuit 11 selects read data based on the output signal 117 from the register 63. That is,
The selection circuit 11 outputs the output data from the I / O interface control circuit 10, the output data 111 from the mask data register (MSKR) 12, the registers (L2R, L1R) 18,
One of the output data 112 and 113 from the output terminal 21 and the output data 114 to 116 from the control flip-flop groups (FFG-1 to FFG-3) 23, 25 and 27 is used as the output signal 117 from the register 63. Based on this, it is selected as read data.

The mask data register 12 stores mask information for fixing output data from the I / O interface control circuit 10 other than the target data to a predetermined value ("0" or "1"). The AND circuit 13 fixes the read data selected by the selection circuit 11 other than the target data to a predetermined value according to the output data 111 from the mask data register 12, and the parity generation circuit (PG) 1
4 and the buffer gate 15. The parity generation circuit 14 generates a parity bit based on the read data output from the AND circuit 13.

The registers 18 and 21 and the control flip-flop groups 23, 25 and 27 store data length information necessary for controlling data transfer. Decoder (DEC) 2
9 decodes the register number of the write destination and outputs the decoded signal to the AND circuits 17, 19, 22, 24, 26 and 28, respectively. The register (CHN) 30 stores the channel number from the channel number register 64 of the common channel unit 6, and the channel number storage unit 31 stores the channel number of its own channel unit 1.

The comparison circuit 32 compares the channel number of the register 30 with the channel number of the channel number storage unit 31, and when the channel numbers match each other, recognizes as a read instruction or a write instruction for the own channel unit 1.

The operation of one embodiment of the present invention will be described with reference to FIGS. First, the operation when the microprogram control device 5 writes data in the register 21 inside the channel section 1 based on the instruction of the microprogram will be described.

The microprogram controller 5 writes desired data in the write data register 61 via the buffer gates 51 and 67 and the data bus 100. At this time, at the same time, the microprogram controller 5 causes the register 21
To the register 63, and the channel number indicating the channel section 1 to the channel number register 64.
Write in each.

When flip-flop 62 is set,
The content of the write data register 61 is the buffer gate 69.
On the channel data bus 110 via. The contents of the flip-flop 62 are further transmitted to the channel section 1.

The register selection number of the register 63 is also sent to the channel section 1, decoded by the decoding circuit 29, and a register write signal is generated. The write data on the channel data bus 110 is output to the input data selector 20 of the register 21 via the buffer gates 69 and 16, and is selected by the input data selector 20 when the output of the AND circuit 22 becomes "1". It is written in the register 21.

Mask data register 12, other register 18, and control flip-flop groups 23, 25, 27
The writing of data to and is also performed in the same manner as the writing of data to the register 21 described above.

Next, the operation for reading the information inside the channel section 1 will be described. First, prior to reading from the inside of the channel unit 1, predetermined data (for example, all “1”) is written in the mask data register 12 by the above-described operation procedure.

After this, the microprogram controller 5
Under the control of 1, the code for selecting the information to be read is written in the register 63, the channel number indicating the channel section 1 is written in the channel number register 64, and "1" is set in the flip-flop 62.

The code written in the register 63 is a signal line.
It is output to the selection circuit 11 via 117, and desired data (for example, the contents of the register 18) is selected and output by the selection circuit 11 according to this code.

The desired data selected by the selection circuit 11 is ANDed with the contents of the mask data register 12 by the AND circuit 13 in correspondence with each bit, and the parity generation circuit 14 generates an odd parity, and the buffer gate 15 On the channel data bus 110 via. In this case, since the contents of the mask data register 12 are all “1”, the read data from the selection circuit 11 is AND circuit 1.
3 is output on the channel data bus 110 without any action.

The buffer gate 15 is enabled by the operation result of the logical product of the output of the comparison circuit 32 indicating that the own channel unit 1 is selected and the signal from the flip-flop 66 instructing the reading. As a result, the read data from the selection circuit 11 is output from the buffer gate 15 onto the channel data bus 110.

The read data output on the channel data bus 110 is taken into the read data register 65 via the buffer gate 70, and then the buffer gate 68.
And read into the microprogram controller 5 via the data bus 100.

Next, the operation of reading asynchronous data from the asynchronous I / O interface control circuit 10 will be described. The I / O interface 7 includes an interface signal and a flip-flop that operate asynchronously with the clocks of the channel unit 1 and the microprogram controller 5. Therefore, when the control signal on the I / O interface 7 which is normally set / reset by the instruction of the microprogram and the strobe signal for data transfer are assigned to different bits of the same read instruction, those controls are controlled. Even if only the signal is read, other bits may operate asynchronously, and the parity of the read data and the data itself may become uncertain. Therefore, there is a possibility that a parity error will occur at the stage of reading to the read data register 65.

In the above case, the mask data in which only the bit position corresponding to the target control signal line is set to "1" and the other bit positions are set to "0" is set in the mask data register 12 as in the above-described operation. And write in advance.

Thereafter, the selection circuit 11 causes the I / O
The data in the interface control circuit 10 is read. Since the AND circuit 13 takes the logical product of the read data from the selection circuit 11 and the contents of the mask data register 12, the AND circuit 13 outputs the I / O interface only to the bit position corresponding to the target control signal line. The control signal on 7 is output, and the other bit positions are fixed to "0".

That is, the output of the AND circuit 13 does not include an indeterminate signal, and the parity generation circuit 14 stably generates the parity bit. Therefore, there is no possibility that a parity error or the like will occur in the data to the read data register 65.

In this embodiment, the blocks relating to the microprogram control inside the input / output processing device 4 are mainly shown, and the interface portion with the main storage device and the portion for performing data transfer are not shown.

As described above, the data other than the target data among the data from the input / output interface 7 that operates asynchronously with the clock signal in the device itself in the channel unit 1 is ANDed according to the mask information preset in the mask register 12. By fixing the value to a predetermined value in 13 and generating a parity bit in the parity generation circuit 14 based on the data from the AND circuit 13, asynchronous data can be obtained without using a large number of synchronization circuits as in the conventional case. Can be confirmed. Therefore, it is possible to read asynchronous data without significantly increasing the amount of hardware.

[0039]

As described above, according to the present invention, of the data from the input / output interface which operates asynchronously with the clock signal in its own device in the channel section, the data other than the target data is converted into preset mask information. Therefore, by fixing the data to the specified value and generating the parity bit based on the data other than the target data fixed to the specified value, the asynchronous data can be generated without significantly increasing the hardware amount. There is an effect that it can be read.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a system configuration of an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of an input / output processing device according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional example.

[Explanation of symbols]

 1, 1a to 1d Channel part 2a to 2d Input / output control device 4 Input / output processing device 5 Micro program control device 6 Channel common part 10 Asynchronous circuit 12 Mask register 13 AND circuit 14 Parity generating circuit 15 Driver

Claims (1)

[Claims] 1. An input / output processing device connected to an external device via an input / output interface that operates asynchronously with a clock signal in the device itself in a channel section, wherein the target data among the data from the input / output interface is It is characterized in that it is provided with means for fixing other than data to a predetermined value according to preset mask information, and generating means for generating a parity bit of data other than the target data fixed to a predetermined value. Output processing device.