JPS60163167A - Memory controller - Google Patents

Abstract

PURPOSE:To prevent generation of the overhead due to the software by executing a segmentation and synthesis processing of plural partial pictures in a memory so as to attain one start processing thereby avoiding a bus neck. CONSTITUTION:A central processing unit 1000 forms a two-dimension block transfer control table T, sets a head address of a transfer control table T, the number of words per one line of a transfer control table and the number of partial pictures to be converted to a table address counter 2001 in a main memory controller 2000, a table word number register 2002 and a transfer block number counter 2003 so as to start the titled device. This device sets a data for the first one line of the transfer control table T to counters and registers in the device and segments/synthesizes one partial picture based on the said data. The data for one line's share is fetched sequentially in the controller 2000, the segmentation/synthesis is attained and when the segmentation and synthesis is finished as to all partial pictures, an end interruption is applied to the central processing unit 1000.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory control device for a computer, and particularly to a memory control device suitable for performing cutting and combining processing of a plurality of partial images at high speed.

[Background of the invention]

As a device for performing such cutting and combining processing at high speed, the inventors have already developed a ``Document Image Data Cutting and Combining Device'' (Japanese Unexamined Patent Publication No. 56-98'60).

We invented a ``memory control device'' (Japanese Patent Application No. 101238/1982), but this device requires software to start and stop the device in order to cut out and combine one partial image.
Since overhead is required once, when there are many partial images, the software processing time becomes long, and there is a drawback that the cutting and combining processing cannot be speeded up.

[9th Object of the Invention] An object of the present invention is to eliminate the above-mentioned drawbacks and to provide an apparatus that can successively cut out and synthesize a plurality of partial images with only one software override and one head.

[Summary of the invention]

In order to achieve the above object, a two-dimensional block transfer control table is provided in the main memory, and a counter for storing the top address of the table and the number of partial images to be transferred is provided in this device.

FIG. 1 shows an explanatory diagram of continuous transfer of a plurality of partial images by this apparatus. The central processing unit 1000 creates the two-dimensional block transfer control table T, and the memory control device 20
The start address of the transfer control table T, the number of words per row of the transfer control table, and the number of partial images to be transferred are stored in the table address working counter 2001 in 00, the table word count register 2002, and the transfer block number counter 2003. Set the settings and start the device.

This device sets the first row of data of the transfer control table T in counters and registers within the device, and then cuts out and combines one partial image based on this data. Immediately after the end, the data for the next line of the transfer control table is input into the device 2000, and the partial images are cut out and combined, instead of being processed by the central processing unit. In this way, when all the specified partial images have been cut out and combined, the central processing unit 10
Apply end interrupt to 00. The meanings of the symbols in FIG. 1 are as follows.

As: Start address of transfer source s: Interval of valid data at transfer source AD: Start address of transfer destination Ep: Interval of valid data at transfer destination W: Width of data to be transferred (valid data) H: Valid Number of repetitions to transfer data (vertical length of valid data) In addition, 3000a and 3000b in the figure are memories, and the blocks shown with diagonal lines correspond to partial images, respectively.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using examples. Second
The figure shows the configuration of a memory control device according to the present invention. In the figure, the part surrounded by a dotted line is the memory control device 2000.

It is located between the central processing unit 1000 and the memory 3000, and the central processing unit includes an address bus 1100,
A data bus 1200 and a control bus 1300 are connected by K.

The memory control device 2000 includes an address switch 2100
, address control section 2200, read/write control section 23
00, a read/write switch 2400, a control section 2500, and a read/write buffer 2600.

The address switch 2100 is connected to the control section 2500.
When the mode signal 2700 sent from
The data sent from 100 is sent to memory 3000. The mode signal is mode 2 (memory is used to cut out partial images and
When the mode (used as a synthesizer) is indicated, data sent from the address control section 2200 is sent to the memory 3000 as address data.

Write buffer 26oou during read is a buffer used when reading from or writing to the memory 3000.

The read/write switch 2400 is connected to the control unit 25
When the mode signal 2700 sent from 00 indicates mode 1, the read/write signal 2800 sent from the control section is sent to the read/write buffer 2600.
and sends it to memory 3000. When the mode signal indicates mode 2, the read/write signal 290 (1, read/write) sent from the read/write control section 2300 is
Write - Send to buffer 2600 and memory 3000.

In mode 2, the address control unit 2200 controls the memory 30
Calculate the address of 00. Its detailed configuration is shown in FIG. In the figure, 2202, 2204, and 2206 are registers or counters that store the starting address in memory of the two-dimensional block transfer control table, the number of words for one line of the table, and the number of partial images to be transferred, respectively. - Counter, table word number counter, and transfer block number counter. These are connected to the central processing unit (FIG. 2 10) via a data bus (FIG. 2 1200).
Initial data 2208f sent from 00): is captured in synchronization with the initial set signal 2210 sent from the control unit 2500.

2212 to 2222 are registers or counters that store each parameter shown in FIG. This is the return count register. These are memory 30
00, the data 2224 sent via the read session write buffer 2600 is sent to the read/write control unit 23.
It is captured in synchronization with the initial load signal 2226 sent from 00. That is, in the first period of the synchronization signal, the memory 30
Transfer source address data is read into the read/write buffer 2600 from 00, and taken into the transfer source address counter 2212 in the second cycle. In the third period,
The transfer source interval data is read from the memory into the read/write buffer, and taken into the transfer source interval register 2214 in the fourth cycle. Thereafter, data for one row of the two-dimensional block transfer control table is stored in the register or counter in the same manner.

The address selector 2228 is the flag register 22
30 indicates O#, the contents of the table address counter 2202 are sent to the address switch 2100 at odd-numbered cycles of the synchronization signal 2232. Nothing is done in the even numbered cycles of the synchronization signal. address switch 2
100, table word number counter 2234, table-address counter 2202
Count up the contents of 1 by 1. The contents of the table word count register 2204 and the table word count counter 2234
When the contents match, comparator 2236 detects this and sends a carry signal to flag register 2230 and table word counter 2234. When the flag register receives this, it changes its contents from "0" to "1".

The table word number counter 2234 sets its contents to an initial value of 0.
Clear to.

Further, when the flag reference register 2230 indicates "1", the address selector 2228 selects the synchronization signal 223.
2, the transfer source address counter 22
12, the contents of the transfer destination address counter 2216 are selected and sent to the address contention switch 2100 in even-numbered cycles. After sending the address, the contents of the selected address counter are counted up one by one. The word counter 2238 counts up by 1 in synchronization with the count up of the transfer destination address counter 2216, and counts the number of transferred words of valid data.

When the contents of the word count counter 2238 and the contents of the word count register 2220 match, the comparator 2240 detects this;
carry signals to adders 2242 and 2244, respectively.
, word counter 2238 and repetition counter 2
246.

When the adder 2242 receives the carry signal, it adds the contents of the transfer source address counter 2212 and the transfer source interval register 2.
214 and the result is returned to the transfer source address counter 2212 again.

Similarly, when adder 2244 receives a carry signal, adder 2244 adds the contents of destination address counter 2216 and the contents of destination interval register 2218, and returns the result to destination address counter 2216 again. In this way, by skipping the contents of the transfer source address counter and the transfer destination address counter during data transfer, it becomes possible to transfer discontinuous data continuously.

Word number counter 2238 clears its contents to the initial value O upon receiving the carry signal. Furthermore, 1 is added to the contents of the repetition counter 2246 by the same carry signal.

Thereafter, repeat the above operation. Through this repetition, the contents of the repetition example counter 2246 are sequentially counted up from the initial value 0. This value is the number of repetitions register 22.
22, the comparator 2248 detects it and sends the carry signal to the flag register 2230 and
It is sent to the transfer block number counter 2206. flag·
When the register receives this signal, it changes its contents from 11" to 1.0". In addition, the transfer block number counter is
When this signal is received, the contents are counted down by 1, and when the result reaches 10", the end signal is 2.
25G to the control section 2500.

When the read/write control unit 2300Fi in FIG. 2 is in mode 2, the read/write signal 290 of the memory 3000
0 and an initial load signal 2226 for loading data for one row of the two-dimensional block transfer control table into a register or counter in the address control unit 2200.

Its detailed configuration is shown in FIG. That is, this read/write control section 2300 synchronizes with the synchronization signal 2232 sent from the control section 2500 to read/write the memory (FIG. 2,
aooo) read-write signal 2900 and an initial load signal 2226 for the registers and counters.

When the flag register (2230 in FIG. 3) in the address control unit 2200 indicates "0", the selector 2310 selects the read signal and performs read/write operations at odd-numbered cycles of the synchronization signal 2232. Switch 2400. On even cycles of the synchronization signal, the initial load signal is selected and sent to a particular register or counter in the address control.

Which register or counter should be sent is determined by the contents of the table word number counter 2234 in the address control section. In other words, the content of the table word count is ゝ′″0.
If “,” go to the source address counter 2212, “1” go to the source interval register 2214, “2” go to the destination address counter 2216. SS 3 “N” go to the destination interval register 2218, “4” go to the word count register 2220.
If it is 1″″5″, an initial load signal 2226 is sent to the repetition count register 2222.

Further, when the flag register 2230 in the address control unit 2200 indicates "1", the selector 2310 selects
A read signal is selected in the odd-numbered cycle of the synchronization signal 2232, and a write signal is selected in the even-numbered cycle and sent to the read/write switch 2400.

The control section 2500 in FIG. 2 includes an address switch 2100, an address control section 2200, a read/write IIJ control section 2300, and a read/write switch 2.
This is the part that controls 400.

The details are shown in FIG. The control section includes an instruction decoder 2510, a synchronization signal generation section 2520, and an interrupt signal generation section 2530.

The instruction decoder 2510 is connected to the central processing unit (100 in FIG.
0)7) = decodes the control signal sent via the control bus 1300t-, determines the mode of the control signal, and generates the mode signal 2700.

This is sent to the synchronization signal generator 2520, read/write switch 2400, and address pot switch 2100. Furthermore, in mode 1, the control bus 1300
The control signal sent via the switch is sent to the read/write switch 2400 as it is without any cutting. On the other hand, in mode 2, the control signal is decoded and sent to the address control section 2200 as an initial set signal 2210.

Synchronization signal generator 2520 receives mode signal 2700 sent from the instruction decoder and timing signal 2540 sent from central processing unit 1000 via control bus 1300.

Only in mode 2, the timing signal is frequency-divided and used as the synchronization signal 2232, and the read/write control unit 2300
It is sent to address control section 2200.

In mode 1, no synchronization signal is generated.

The interrupt signal generation unit 2530 receives the end signal 225 (l) sent from the address control unit 2200, converts it into an interrupt signal 2550 to the medium heat processing device 1000, and sends it to the control bus 1300.

As explained above, according to the memory control device of the present invention, in the case of mode 1, the central processing unit 1000 and the memory 30
00, all control signals and data are passed through without any processing, just as in the case of a normal main memory device. Therefore, in mode 1, the memory plays a role similar to normal main storage.

On the other hand, in mode 2, the value of the flag register 2230 is "0" at first, so the memory is initially in the read state.
Table address counter 2202 as address
Since the value of is specified, the first parameter (A8: starting address of the transfer source) in the first row of the two-dimensional block transfer control table is taken into the read/write buffer 2600.In the next cycle, This data is captured in the transfer source address counter 2212. In this way,
When all the parameters in the first row of the transfer control table are loaded into a predetermined register or counter, the value of the flag register 2230 switches from ゝゝO〃 to (11rt. At this time, the memory When in the read state, the value of the transfer source address counter 2212 is specified as the address, so the transfer source data is taken into the read/write φ buffer 2600.In the next cycle, the memory switches to the write state, Since the value of the transfer destination address counter 2216 is specified as the address, the data in the read/write buffer 2600 is stored at the transfer destination.In this way, data transfer in the memory uses various buses. It runs fast without any problems.

Furthermore, the values of the transfer source address counter 2212.9 and the transfer destination address counter 2216 are incremented by 1 for each transfer.
Not only is it counted up by a certain value, but it is also counted up by a predetermined value (Is) at regular intervals.

ID), address skip transfer of data (cutting out and combining partial images) becomes possible.

In order to cut out and combine a plurality of partial images with this memory control device, the following steps are taken. .

(1) Create a two-dimensional block transfer control table in the memory 3000 in mode 1.

(2) Initial setting of data necessary for transfer (starting address of the two-dimensional block transfer control table, number of words per line of the table, number of partial images to be transferred) is performed. The initial setting method is to set a specified value in the register of the central processing unit 1000, and then send a control signal for each data set to the memory control unit 2000. This data Φ
The control signal for setting is a mode 2 signal, so
An instruction decoder within the control unit decodes each control signal and generates each corresponding initial set signal 2210. As a result, the table word count register 2204 and the table address counter 2 in the address control unit 2200
202, initial values are set in the transfer block number counter 220G.

(3) A control signal instructing the start of mode 2 data transfer is sent from central processing unit 1000.

As a result, the synchronization signal generation section 2520 in the control section 2500 starts operating, and the address control section 2200
, sends a synchronization signal 2232 to the read/write control unit 2300. By this synchronization signal, data for one row of the two-dimensional block transfer control table is first taken into a register or counter in the address control section, and then,
Data transfer for cutting and combining one partial image is executed.

(4) When the designated H number of data transfers are completed, the contents of the repetition number counter 2246 match the contents of the repetition number register 2222. Comparator 2248
is detected and sends a signal to the flag register 2230 and transfer block number counter 2206. The flag register is
When this signal is received, the value is changed from 11" to IS 01, and preparations are made to import data for the next row of the two-dimensional block transfer control table. Also, when the transfer block number counter receives this signal, the value is changed from 11" to IS 01. count down by 1.

(5) When the transfer of the designated N partial images is completed, the content of the transfer block number counter 2206 becomes "0".

At this time, an end signal 22 is sent to the control unit 2500.
Roll out 50. Interrupt signal generation section 253 in the control section
0 stops the operation of the synchronizing signal generator 2520 upon receiving the end signal, and sends an end interrupt 2550 to the central processing unit 1000. The central processing unit knows the end of data transfer by this end interrupt.

〔Effect of the invention〕

According to the present invention, the function of cutting out and combining multiple partial images is
This can be achieved with one startup process. Therefore, no software overhead is generated, so processing speed can be increased. Furthermore, since the extraction and synthesis processing is executed in memory, no bus neck occurs.

FIG. 6 shows a first application example of this device. memory 300
By treating each character pattern developed as a pit map on 0 as a partial image, character vertical/horizontal conversion, character spacing, and line spacing can be changed at high speed. Also,
Processing such as character string correction, insertion, and deletion can also be sped up.

Further, FIG. 7 shows a second application example of this device.

This is an example of multi-window processing. In the transfer source memory 3000, there are three different documents (documents S, , S2, and S3) that have been subjected to bit map development.

A portion of each document W, , W2. Multi-window display can be realized by cutting out W, (this is called a window) and transferring it to the destination memory 3000b. Here, when moving the bush φ down from the view boat Vl to the view boat v3, only the hatched portion (this is called a segment) needs to be transferred. In addition to this, various other processes such as pop-up, deletion, and movement of PewBoat can be considered, but in any case, determine the segments (multiple partial images) that need to be transferred, and write each segment in the two-dimensional block transfer control table. If you start this device after setting the parameters, you can speed up the processing.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of continuous transfer of multiple partial images, FIG. 2 is a block diagram of the memory control device, FIG. 3 is a block diagram of the address control unit in the memory control device, and FIG.
FIG. 5 is a block diagram of the read/write control section in the memory control device, FIG. 5 is a block diagram of the control section in the memory control device, and FIG. 6 is the first application of the memory control device. Figure 7, which shows an example, is a diagram showing a second application example of the memory control device. 1000...Central processing unit, 2000...Memory control unit, 3000...Memory, 1100...Address conflict bus, 1200...Data Φ bus, 1300...
- Control bus, 2100... Address control switch, 2200... Address control unit, 2300...
- Read/write control section, 2400... Read/write switch, 2500... Control section, 260
0... Read/write buffer, 2700... Mode signal, 2800... Read/write signal, 290
0...Read/write signal, 2202...Table address counter, 2204...Table word number register, 2206...Transfer block number counter, 2
208...Initial data, 2210...Initial top signal, 2212...Transfer source address-counter, 221
4... Transfer source interval register, 2216... Transfer destination address counter, 2218... Transfer destination interval register, 2220... Word count register, 2222... Repeat count register, 2224... Data, 2226 ...
Initial load signal, 2228...address ψ selector,
2230...Flag j register, 2232...Synchronization signal, 2234...Table word number counter, 2236
... Comparator, 2238 ... Word counter, 2240
...Comparator, 2242...Adder, 2244...
Adder, 2246...Number of repetitions, 2248
...Comparator, 2250...End signal, 2310...
・Selector, 2320... Read signal generation section, 233
0... Write signal generation unit, 2340... Initial load signal generation unit, 2510... Instruction decoder, 2520...
...Synchronization signal generation section, 2530...Interrupt signal generation section,
2540...ri No. 4 Figure Z 5 Figure 7

Claims (1)

[Claims] 1. In a device that controls the memory of a computer, in addition to the function as a normal main memory device, in order to add a function to continuously transfer (cut out and combine) multiple partial images without software intervention, A memory characterized by being provided with a register or a counter for storing the start address of a two-dimensional block transfer control table containing parameters for data transfer control, the number of words in one row of the table, and the number of partial images to be transferred. Control device.