JPH05165055A - Picture element split type liquid crystal display element - Google Patents

Picture element split type liquid crystal display element

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Publication number
JPH05165055A
JPH05165055A JP33076491A JP33076491A JPH05165055A JP H05165055 A JPH05165055 A JP H05165055A JP 33076491 A JP33076491 A JP 33076491A JP 33076491 A JP33076491 A JP 33076491A JP H05165055 A JPH05165055 A JP H05165055A
Authority
JP
Japan
Prior art keywords
electrode
pixel
liquid crystal
electrodes
crystal display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33076491A
Other languages
Japanese (ja)
Inventor
Teizo Yugawa
禎三 湯川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hosiden Corp
Original Assignee
Hosiden Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hosiden Corp filed Critical Hosiden Corp
Priority to JP33076491A priority Critical patent/JPH05165055A/en
Publication of JPH05165055A publication Critical patent/JPH05165055A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To provide a picture element split type liquid crystal display element, in which connection with normal picture element electrode is made after the picture element electrode or electrodes corresponding to a defective picture element is cut off. CONSTITUTION:In a picture element split type liquid crystal display element, an electrode 15 constituting picture elements is split into a plurality of picture element electrodes 151, 152 which are connected with source busses 19 parallelly through respective TFTs 16, whose drain electrodes 18 are connected with respective picture element electrodes 15 through respective bridging pieces 17 which are narrow and can easily be severed, wherein a source electrode is connected with the respective source busses 19 through bridging pieces 17 narrow and capable of being severed easily, and the picture element electrodes 151, 152 are connected with respective additional capacity electrodes 40 through bridging pieces 41 which are narrow and can easily be severed, and further the gate electrode is connected with a gate bus 18 and a metal for welding shortcircuiting is furnished in the neighborhood of the oppositely situated parts of adjoining picture element electrodes.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、画素分割液晶表示素
子に関し、特に画素分割液晶表示素子の内の欠陥部分を
切り離して当該画素電極を正常画素電極に接続する画素
分割液晶表示素子に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel-divided liquid crystal display element, and more particularly to a pixel-divided liquid crystal display element in which a defective portion in the pixel-divided liquid crystal display element is separated and the pixel electrode is connected to a normal pixel electrode.

【0002】[0002]

【従来の技術】ここで、従来提案されている液晶表示素
子を図1および図2を参照して簡単に説明するに、透明
基板11および透明基板12がスペーサ13を介して互
いに近接対向して具備され、透明画素電極15の画素マ
トリックスが透明基板11内面に形成される。透明画素
電極15のそれぞれには薄膜トランジスタ(TFT)1
6が対応形成される。一方、透明基板12の内面には透
明共通電極17が形成されている。透明画素電極15と
透明共通電極17との間には液晶14が封入される。薄
膜トランジスタ(TFT)16のゲートはゲートバス1
8に接続し、ソースはソースバス19に接続している。
ゲートバス18およびソースバス19は図示される通り
互いに直交して多数本形成される。ゲートバス18に制
御信号を供給して薄膜トランジスタ(TFT)16がオ
ンしたときにこれに対応する透明画素電極15と透明共
通電極17との間にソースバス19を介して電圧が印加
されればこれら電極間の液晶の光学的状態が変化する様
に構成されている。透明画素電極15には、必要により
隣接する薄膜トランジスタ(TFT)16のゲートバス
18に重なるようにその端部から付加電極40を延伸形
成し、付加電極40とゲートバス18との間に付加容量
部を形成する。透明画素電極15と透明共通電極17と
の間に形成される容量と並列のものである。
2. Description of the Related Art A conventional liquid crystal display device will be briefly described with reference to FIGS. 1 and 2. A transparent substrate 11 and a transparent substrate 12 are arranged close to each other via a spacer 13. A pixel matrix of the transparent pixel electrode 15 is formed on the inner surface of the transparent substrate 11. A thin film transistor (TFT) 1 is provided on each of the transparent pixel electrodes 15.
6 are formed correspondingly. On the other hand, a transparent common electrode 17 is formed on the inner surface of the transparent substrate 12. The liquid crystal 14 is sealed between the transparent pixel electrode 15 and the transparent common electrode 17. The gate of the thin film transistor (TFT) 16 is the gate bus 1
8 and the source is connected to the source bus 19.
A large number of gate buses 18 and source buses 19 are formed orthogonal to each other as shown in the drawing. When a control signal is supplied to the gate bus 18 and a thin film transistor (TFT) 16 is turned on, if a voltage is applied between the transparent pixel electrode 15 and the transparent common electrode 17 corresponding thereto via the source bus 19, these It is configured such that the optical state of the liquid crystal between the electrodes changes. If necessary, an additional electrode 40 is extended from the end of the transparent pixel electrode 15 so as to overlap the gate bus 18 of the thin film transistor (TFT) 16 adjacent to the transparent pixel electrode 15, and an additional capacitance portion is provided between the additional electrode 40 and the gate bus 18. To form. It is in parallel with the capacitance formed between the transparent pixel electrode 15 and the transparent common electrode 17.

【0003】ここで、液晶表示装置の製造工程を図3を
参照して簡単に説明しておく。透明基板11上面に画素
電極15、ソースバス19がITOの如き透明導電体に
より形成され、更に画素電極15およびソースバス19
にまたがってTFT16を構成する半導体層23が形成
される。これらすべての上面に亘って窒化シリコンより
成るゲート絶縁膜24を形成し、この絶縁膜24の上面
の半導体層23に対応するところにゲート電極25を形
成すると共にこれらゲート電極25に接続するゲートバ
ス18をソースバス19に直交するように形成する。こ
れらゲート電極25およびゲートバス18を含むゲート
絶縁膜24の上面すべてに保護層26を形成する。そし
て、保護層26と透明共通電極17との間に液晶が封入
される。
The manufacturing process of the liquid crystal display device will be briefly described with reference to FIG. The pixel electrode 15 and the source bus 19 are formed on the upper surface of the transparent substrate 11 by a transparent conductor such as ITO, and the pixel electrode 15 and the source bus 19 are further formed.
A semiconductor layer 23 that forms the TFT 16 is formed so as to straddle. A gate insulating film 24 made of silicon nitride is formed over all of these upper surfaces, a gate electrode 25 is formed on the upper surface of the insulating film 24 at a position corresponding to the semiconductor layer 23, and a gate bus connected to these gate electrodes 25 is formed. 18 is formed so as to be orthogonal to the source bus 19. The protective layer 26 is formed on the entire upper surface of the gate insulating film 24 including the gate electrode 25 and the gate bus 18. Then, liquid crystal is sealed between the protective layer 26 and the transparent common electrode 17.

【0004】[0004]

【発明が解決しようとする課題】画素を複数の画素に分
割し、これら複数の画素の内に欠陥画素が発生してもこ
れを切り離してしまって格別の修復を施すことはしない
手法もある。しかし、画素を例えば3或は4個の多数の
画素に分割したとしても、仮にその内の1画素に欠陥が
発生すれば、1/3画素或は1/4画素の不良が発生し
たことになるのであり、この程度の不良であっても肉眼
には容易に不良と認識されるのである。
There is also a method in which a pixel is divided into a plurality of pixels, and even if a defective pixel occurs in the plurality of pixels, the defective pixel is not cut off and special repair is not performed. However, even if a pixel is divided into a large number of pixels, for example, 3 or 4, if a defect occurs in one of the pixels, it means that a defect of 1/3 pixel or 1/4 pixel has occurred. Therefore, even such a defect is easily recognized by the naked eye as a defect.

【0005】この発明は、画素分割液晶表示素子の内の
欠陥部分を切り離して当該画素電極を正常画素電極に接
続するようにして上述の通りの問題を解消した画素分割
液晶表示素子を提供しようとするものである。
The present invention intends to provide a pixel-divided liquid crystal display device which solves the above-mentioned problems by separating a defective portion in the pixel-divided liquid crystal display device and connecting the pixel electrode to a normal pixel electrode. To do.

【0006】[0006]

【課題を解決するための手段】透明基板11上面に画素
電極15、ソースバス19が透明導電体により形成さ
れ、更に画素電極15およびソースバス19にまたがっ
て薄膜トランジスタ(TFT)16を構成する半導体層
23が形成され、これらを含む透明基板11上面に絶縁
膜24を形成し、この絶縁膜24の上面の半導体層23
に対応するところにゲート電極25を形成すると共にこ
れらゲート電極25に接続するゲートバス18をソース
バス19に直交するように形成し、これらゲート電極2
5およびゲートバス18を含むゲート絶縁膜24の上面
に保護層26を形成し、保護層26と透明共通電極17
との間に液晶が封入された画素分割液晶表示素子におい
て、画素を構成する電極は複数の画素電極151 および
152 に分割され、各画素電極151 および152 はそ
れぞれの薄膜トランジスタ(TFT)161 および16
2 を介して各別に並列にソースバス19に接続してお
り、薄膜トランジスタ(TFT)それぞれのドレイン電
極181 および182 はそれぞれ切断容易な幅の狭い橋
絡片171 および172 によりそれぞれの画素電極15
1 および152 に接続すると共に、ソース電極191
よび192 はそれぞれ切断容易な幅の狭い橋絡片171
および172 によりソースバス19に接続しており、画
素電極15 1 および152 はそれぞれ切断容易な幅の狭
い橋絡片411 および412 により各付加容量電極40
1 および402 に接続しており、ゲート電極はゲートバ
ス18に接続し、相隣接する画素電極151 および画素
電極152 の互いに対向する部分の近傍に溶接短絡用金
属を具備せしめた。
Means for Solving the Problem Pixels are formed on the upper surface of the transparent substrate 11.
The electrode 15 and the source bus 19 are made of a transparent conductor.
And further straddles the pixel electrode 15 and the source bus 19.
Layer forming a thin film transistor (TFT) 16
23 is formed and is insulated on the upper surface of the transparent substrate 11 including them.
The film 24 is formed, and the semiconductor layer 23 on the upper surface of the insulating film 24 is formed.
The gate electrode 25 is formed at the location corresponding to
The source of the gate bus 18 connected to these gate electrodes 25
These gate electrodes 2 are formed so as to be orthogonal to the bus 19.
5 and the upper surface of the gate insulating film 24 including the gate bus 18
The protective layer 26 is formed on the transparent common electrode 17 and the protective layer 26.
In a pixel-divided liquid crystal display element in which liquid crystal is enclosed between
The electrodes forming the pixel are the plurality of pixel electrodes 151and
152Each pixel electrode 151And 152Haso
Thin film transistor (TFT) 161And 16
2And connect to the source bus 19 in parallel via
Drain transistor of each thin film transistor (TFT)
Pole 181And 182Each is a narrow bridge that is easy to cut
Entanglement 171And 172Each pixel electrode 15
1And 152Source electrode 191Oh
And 192Each is a narrow bridging piece 17 that can be easily cut.1
And 172Connected to the source bus 19 by
Elementary electrode 15 1And 152Each has a narrow width for easy cutting
I Bridge 411And 412Each additional capacitance electrode 40
1And 402The gate electrode is connected to
Pixel electrodes 15 adjacent to each other1And pixels
Electrode 152Of welding short-circuiting gold near the parts of the
It has a genus.

【0007】そして、溶接短絡用金属としては、溶接用
金属を画素電極15に具備し、短絡用金属29を透明基
板上面に或は絶縁膜24上面に具備せしめた。また、溶
接兼短絡用金属30を透明基板11上面および絶縁膜2
4上面に具備せしめた。
As the welding short-circuit metal, the welding metal was provided in the pixel electrode 15, and the short-circuit metal 29 was provided on the upper surface of the transparent substrate or on the upper surface of the insulating film 24. In addition, the metal 30 for welding and short circuit is formed on the upper surface of the transparent substrate 11 and the insulating film 2.
4 was provided on the upper surface.

【0008】[0008]

【実施例】この発明の実施例を図4を参照して説明す
る。画素電極は画素電極151 および画素電極152
2枚に分割、構成されており、各画素電極151 および
画素電極152 は薄膜トランジスタ(TFT)161
よび薄膜トランジスタ(TFT)162 を介して各別に
並列にソースバス19に接続している。ここで、薄膜ト
ランジスタ(TFT)161 のドレイン電極181 は切
断容易な幅の狭い橋絡片171 により画素電極151
接続すると共に、ソース電極191 は切断容易な幅の狭
い橋絡片171 によりソースバス19に接続する一方、
薄膜トランジスタ(TFT)162 のドレイン電極18
2 は切断容易な幅の狭い橋絡片172 により画素電極1
2 に接続すると共に、ソース電極192 は切断容易な
幅の狭い橋絡片172 によりソースバス19に接続して
いる。そして、画素電極151 とその付加容量電極40
1 とは切断容易な幅の狭い橋絡片411 により相互接続
しており、画素電極152 とその付加容量電極402
は切断容易な幅の狭い橋絡片412 により相互接続して
いる。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to FIG. Pixel electrodes divided into two pixel electrodes 15 1 and pixel electrode 15 2 is composed, each pixel electrode 15 1 and the pixel electrode 15 2 is connected via a thin film transistor (TFT) 16 1 and a thin film transistor (TFT) 16 2 Each of them is connected to the source bus 19 in parallel. Here, a thin film transistor (TFT) 16 1 of the drain electrode 18 1 is connected by narrow bridging piece 17 1 of scissile width to the pixel electrode 15 1, the narrow bridging piece of the source electrode 19 1 scissile width 17 1 connects to the source bus 19 while
Drain electrode 18 of thin film transistor (TFT) 16 2.
2 pixel electrode 1 by narrow bridging piece 17 2 of scissile width
5 2 as well as connected to the source electrode 19 2 is connected to the source bus 19 by a narrow bridging piece 17 2 of scissile width. Then, the pixel electrode 15 1 and its additional capacitance electrode 40
1 and are interconnected by narrow bridging piece 41 1 of scissile width, the pixel electrode 15 2 and the additional capacitor electrode 40 2 and interconnected by narrow bridging piece 41 2 of scissile width There is.

【0009】この発明においては、上述した通り、画素
電極15、薄膜トランジスタ(TFT)16、付加容量
電極40をそれぞれ分割しており、そして薄膜トランジ
スタ(TFT)16および付加容量電極40をそれぞれ
ソースバス19および画素電極15に切断容易な幅の狭
い橋絡片に接続したことにより、薄膜トランジスタ(T
FT)16或は付加容量電極40に欠陥が生じた場合に
これらを画素電極15から切り離す。次いで欠陥が生じ
た薄膜トランジスタ(TFT)16或は付加容量電極4
0に対応するこれら欠陥部分が切り離された画素電極を
正常画素電極に短絡接続するのであるが、以下におい
て、欠陥部分の切り離しおよび画素電極と正常画素電極
との間の短絡接続の手法について説明する。
In the present invention, as described above, the pixel electrode 15, the thin film transistor (TFT) 16 and the additional capacitance electrode 40 are respectively divided, and the thin film transistor (TFT) 16 and the additional capacitance electrode 40 are respectively connected to the source bus 19 and the source bus 19. The thin film transistor (T
When a defect occurs in the FT) 16 or the additional capacitance electrode 40, these are separated from the pixel electrode 15. Next, a defective thin film transistor (TFT) 16 or additional capacitance electrode 4
The pixel electrode from which these defective portions corresponding to 0 are separated is short-circuited to the normal pixel electrode. The method of separating the defective portion and short-circuiting the pixel electrode and the normal pixel electrode will be described below. ..

【0010】図5は短絡接続部におけるA−A断面を示
す図である。図5(a)の例においては、透明基板11
上面に、先ずこの発明の短絡接続用金属層29を形成
し、短絡接続用金属層29を含み透明基板11上面に絶
縁層22を形成する。この絶縁層22上面には上述の如
くして画素電極15その他を形成する。この発明は、こ
の際画素を構成する相隣接する画素電極151 および画
素電極152 の互いに対向する部分の双方に溶接用金属
281 および282 を具備せしめておく。ところで、短
絡接続用金属層29は溶接用金属281 および282
にまたがる長さを有するものである。24は画素電極1
1 および画素電極152 を含み絶縁層22上面に形成
された絶縁膜である。
FIG. 5 is a view showing an AA cross section in the short-circuit connection portion. In the example of FIG. 5A, the transparent substrate 11
First, the metal layer 29 for short-circuit connection of the present invention is formed on the upper surface, and the insulating layer 22 is formed on the upper surface of the transparent substrate 11 including the metal layer 29 for short-circuit connection. The pixel electrode 15 and others are formed on the upper surface of the insulating layer 22 as described above. In the present invention, the metal for welding 28 1 and 28 2 are provided on both of the portions of the pixel electrode 15 1 and the pixel electrode 15 2 which are adjacent to each other and constitute the pixel, which face each other. By the way, the short-circuit connection metal layer 29 has a length that extends between the welding metals 28 1 and 28 2 . 24 is the pixel electrode 1
The insulating film is formed on the upper surface of the insulating layer 22 including 5 1 and the pixel electrode 15 2 .

【0011】図5(b)の例はは短絡接続用金属層29
を、図5(a)の場合とは異なって、透明基板11上面
にではなくして絶縁層24上面に形成する例を示してい
る。図5(c)は、図5(a)および図5(b)の場合
とは異なり、格別の溶接用金属は使用せずに溶接兼短絡
接続用金属層301 および溶接兼短絡接続用金属層30
2 を透明基板11上面および絶縁層24上面に形成した
例である。
In the example of FIG. 5B, the short-circuit connection metal layer 29 is used.
5A is different from the case of FIG. 5A, an example is shown in which it is formed not on the upper surface of the transparent substrate 11 but on the upper surface of the insulating layer 24. Unlike the case of FIGS. 5A and 5B, FIG. 5C is different from the case of FIG. 5A and FIG. 5B without using any special welding metal, and the welding / short circuit connecting metal layer 30 1 and the welding / short circuit connecting metal are provided. Layer 30
In this example, 2 is formed on the upper surface of the transparent substrate 11 and the upper surface of the insulating layer 24.

【0012】[0012]

【発明の効果】ここで、例えば付加容量電極401 近傍
の付加容量部において欠陥が発生している場合、図5
(a)の例については、透明基板11側から矢印の向き
にレーザ光を放射してこれを付加容量電極401 の切断
容易な幅の狭い橋絡片411 に集束せしめ、橋絡片41
1 を切断することにより欠陥容量部を画素電極151
ら容易に切り離すことができる。次いで、溶接工程に入
るのであるが、欠陥容量部を画素電極151 から切り離
した後、レーザ光を矢印の向きに放射してこれを今度は
溶接用金属281 近傍に集束せしめ、溶接用金属281
を溶融してこれにより画素電極151 と短絡接続用金属
層29とを短絡接続することができる。これと同様の操
作を溶接用金属282 近傍にも施す。これにより溶接用
金属282 を溶融し、画素電極152 と短絡接続用金属
層29とを上述と同様に短絡接続することができる。結
局、欠陥容量部が切り離された画素電極151 は正常な
画素電極152 に短絡接続されるに到り、従って欠陥容
量部が切り離された画素電極151 にも正常な画素電極
152 から表示信号が印加されることとなるので、当該
画素の画素電極全面積に格別の変化を生ぜしめずに済
む。
Here, for example, when a defect occurs in the additional capacitance portion near the additional capacitance electrode 40 1 , as shown in FIG.
In the example of (a), laser light is emitted from the transparent substrate 11 side in the direction of the arrow to focus the laser light on a narrow bridging piece 41 1 of the additional capacitance electrode 40 1 which can be easily cut, and the bridging piece 41 1
By disconnecting 1 , the defective capacitance portion can be easily separated from the pixel electrode 15 1 . Next, in the welding process, after the defective capacitance portion is separated from the pixel electrode 15 1 , laser light is emitted in the direction of the arrow so that this laser light is focused next to the welding metal 28 1 , and the welding metal is welded. 28 1
This makes it possible to short-circuit connects the shorting connection metal layer 29 and the pixel electrode 15 1 by melting. The same operation is performed near the welding metal 28 2 . As a result, the welding metal 28 2 can be melted, and the pixel electrode 15 2 and the short-circuit connection metal layer 29 can be short-circuited in the same manner as described above. Eventually, the pixel electrode 15 1 from which the defective capacitance portion has been cut off is short-circuited to the normal pixel electrode 15 2 , and therefore the pixel electrode 15 1 from which the defective capacitance portion has been cut off from the normal pixel electrode 15 2 Since the display signal is applied, it is not necessary to cause a remarkable change in the entire area of the pixel electrode of the pixel.

【0013】図5(b)の例については、短絡接続用金
属層29が溶接用金属281 および溶接用金属282
上方に配置されているが、この場合も図5(a)の例と
同様に欠陥容量部を画素電極151 から切り離した後、
上述の溶接工程を適用することにより欠陥発生画素電極
と正常画素電極との間の短絡接続を実施することができ
る。
In the example of FIG. 5B, the short-circuit connection metal layer 29 is arranged above the welding metal 28 1 and the welding metal 28 2 , but in this case as well, the example of FIG. after disconnecting the defective capacitor portion from the pixel electrode 15 1 as well as,
By applying the welding process described above, a short-circuit connection between the defective pixel electrode and the normal pixel electrode can be performed.

【0014】図5(c)の例については、これについて
も欠陥容量部を画素電極151 から切り離した後、溶接
兼短絡接続用金属層301 および溶接兼短絡接続用金属
層302 の両端部に上述の溶接工程を適用することによ
り欠陥発生画素電極と正常画素電極との間の短絡接続を
実施することができる。次に、画素電極151 の薄膜ト
ランジスタ(TFT)161 に欠陥が発生している場合
についてであるが、この場合は薄膜トランジスタ(TF
T)161 の橋絡片171 に着目し、透明基板11側か
ら矢印の向きにレーザ光を放射してこれに集束せしめ、
橋絡片171 を切断することにより欠陥TFTを画素電
極151 から容易に切り離すことができる。次いで実施
される溶接工程は付加容量部に欠陥が発生した場合と異
なるところはない。結局、欠陥TFTが切り離された画
素電極151 および付加容量電極401 は共に正常な画
素電極152 に短絡接続されるに到り、従って欠陥TF
Tが切り離された画素電極151 および付加容量電極4
1 にも正常な画素電極152 から表示信号が印加され
ることとなるので、当該画素の画素電極全面積には何等
の変化も生じない。
In the example of FIG. 5C, also in this case, after the defective capacitance portion is separated from the pixel electrode 15 1 , both ends of the metal layer 30 1 for welding and short-circuit connection and the metal layer 30 2 for welding and short-circuit connection are formed. By applying the above-described welding process to the portion, a short-circuit connection between the defective pixel electrode and the normal pixel electrode can be performed. Next, regarding the case where a defect occurs in the thin film transistor (TFT) 16 1 of the pixel electrode 15 1 , in this case, the thin film transistor (TF)
T) Focusing on the bridging piece 17 1 of 16 1 , the laser light is emitted from the transparent substrate 11 side in the direction of the arrow and focused on this.
The defective TFT can be easily separated from the pixel electrode 15 1 by cutting the bridging piece 17 1 . The subsequent welding process is no different from the case where a defect occurs in the additional capacity portion. Eventually, both the pixel electrode 15 1 and the additional capacitance electrode 40 1 from which the defective TFT is separated are short-circuited to the normal pixel electrode 15 2 , and therefore the defective TF is generated.
Pixel electrodes 15 T is detached 1 and the additional capacitance electrode 4
Since the display signal is applied to the pixel electrode 15 2 that is normal to 0 1 , no change occurs in the total area of the pixel electrode of the pixel.

【図面の簡単な説明】[Brief description of drawings]

【図1】液晶表示素子の従来例を示す図である。FIG. 1 is a diagram showing a conventional example of a liquid crystal display element.

【図2】液晶表示素子の画素マトリックスを示す図であ
る。
FIG. 2 is a diagram showing a pixel matrix of a liquid crystal display element.

【図3】図2のD−Dにおける断面を示す図である。FIG. 3 is a diagram showing a cross section taken along the line D-D in FIG. 2;

【図4】この発明の画素分割液晶表示素子の画素を示す
図である。
FIG. 4 is a diagram showing pixels of a pixel division liquid crystal display element of the present invention.

【図5】図4の短絡接続部におけるA−A断面を示す図
であり、(a)は短絡接続用金属層が溶接用金属の下方
に配置されたものを示す図、(b)は短絡接続用金属層
が溶接用金属の上方に配置されたものを示す図、(c)
は溶接兼短絡接続用金属層が使用されものを示す図であ
る。
5 is a view showing a cross section taken along the line AA in the short-circuit connection portion of FIG. 4, (a) showing a metal layer for short-circuit connection arranged below a metal for welding, and (b) a short circuit. The figure which shows what the metal layer for connection was arrange | positioned above the metal for welding, (c).
FIG. 6 is a view showing a case where a metal layer for welding and short-circuit connection is used.

【符号の説明】[Explanation of symbols]

11 透明基板 14 液晶 15 画素電極 16 薄膜トランジスタ(TFT) 17 透明共通電極 18 ゲートバス 19 ソースバス 23 半導体層 24 絶縁膜 25 ゲート電極 26 保護層26 11 transparent substrate 14 liquid crystal 15 pixel electrode 16 thin film transistor (TFT) 17 transparent common electrode 18 gate bus 19 source bus 23 semiconductor layer 24 insulating film 25 gate electrode 26 protective layer 26

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/784 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 29/784

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 透明基板上面に画素電極、ソースバスが
透明導電体により形成され、更に画素電極およびソース
バスにまたがって薄膜トランジスタを構成する半導体層
が形成され、これらを含む透明基板上面に絶縁膜を形成
し、この絶縁膜の上面の半導体層に対応するところにゲ
ート電極を形成すると共にこれらゲート電極に接続する
ゲートバスをソースバスに直交するように形成し、これ
らゲート電極およびゲートバスを含むゲート絶縁膜の上
面に保護層を形成し、保護層と透明共通電極との間に液
晶が封入された画素分割液晶表示素子において、画素を
構成する電極は複数の画素電極に分割され、各画素電極
はそれぞれの薄膜トランジスタを介して各別に並列にソ
ースバスに接続しており、薄膜トランジスタそれぞれの
ドレイン電極はそれぞれ切断容易な幅の狭い橋絡片によ
りそれぞれの画素電極に接続すると共に、ソース電極は
それぞれ切断容易な幅の狭い橋絡片によりソースバスに
接続しており、画素電極はそれぞれ切断容易な幅の狭い
橋絡片により各付加容量電極に接続しており、ゲート電
極はゲートバスに接続し、相隣接する画素電極の互いに
対向する部分の近傍に溶接短絡用金属を具備せしめたこ
とを特徴とする画素分割液晶表示素子。
1. A pixel electrode and a source bus are formed of a transparent conductor on the upper surface of a transparent substrate, and a semiconductor layer forming a thin film transistor is further formed across the pixel electrode and the source bus. An insulating film is formed on the upper surface of the transparent substrate including these. And forming a gate electrode at a position corresponding to the semiconductor layer on the upper surface of the insulating film, and forming a gate bus connected to these gate electrodes so as to be orthogonal to the source bus, and including the gate electrode and the gate bus. In a pixel-divided liquid crystal display element in which a protective layer is formed on the upper surface of a gate insulating film, and liquid crystal is sealed between the protective layer and a transparent common electrode, the electrodes forming pixels are divided into a plurality of pixel electrodes, The electrodes are separately connected in parallel to the source bus through the respective thin film transistors, and the drain electrode of each thin film transistor is Each is connected to each pixel electrode by a narrow bridging piece that can be easily cut, and the source electrode is connected to the source bus by a narrow bridging piece that is easy to cut. It is connected to each additional capacitance electrode by a narrow bridging piece, the gate electrode is connected to the gate bus, and the metal for welding short circuit is provided in the vicinity of the mutually opposing portions of the adjacent pixel electrodes. Pixel-divided liquid crystal display element.
【請求項2】 請求項1に記載される画素分割液晶表示
素子において、溶接用金属を画素電極に具備し、短絡用
金属を透明基板上面に具備せしめたことを特徴とする画
素分割液晶表示素子。
2. The pixel-divided liquid crystal display element according to claim 1, wherein a welding metal is provided on the pixel electrode and a short-circuiting metal is provided on the upper surface of the transparent substrate. ..
【請求項3】 請求項1に記載される画素分割液晶表示
素子において、溶接用金属を画素電極に具備し、短絡用
金属を絶縁膜上面に具備せしめたことを特徴とする画素
分割液晶表示素子。
3. The pixel-divided liquid crystal display element according to claim 1, wherein a welding metal is provided on the pixel electrode and a short-circuiting metal is provided on the upper surface of the insulating film. ..
【請求項4】 請求項1に記載される画素分割液晶表示
素子において、溶接兼短絡用金属を透明基板上面および
絶縁膜上面に具備せしめたことを特徴とする画素分割液
晶表示素子。
4. The pixel-divided liquid crystal display element according to claim 1, wherein a metal for welding and short-circuiting is provided on the upper surface of the transparent substrate and the upper surface of the insulating film.
JP33076491A 1991-12-13 1991-12-13 Picture element split type liquid crystal display element Pending JPH05165055A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33076491A JPH05165055A (en) 1991-12-13 1991-12-13 Picture element split type liquid crystal display element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33076491A JPH05165055A (en) 1991-12-13 1991-12-13 Picture element split type liquid crystal display element

Publications (1)

Publication Number Publication Date
JPH05165055A true JPH05165055A (en) 1993-06-29

Family

ID=18236282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33076491A Pending JPH05165055A (en) 1991-12-13 1991-12-13 Picture element split type liquid crystal display element

Country Status (1)

Country Link
JP (1) JPH05165055A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977563A (en) * 1996-05-09 1999-11-02 Sharp Kabushiki Kaisha Active matrix substrate and correcting method of structural defect
US6710827B2 (en) 2000-03-31 2004-03-23 Sharp Kabushiki Kaisha Liquid crystal display device having sub-pixel electrodes and defect correction method therefor
US7110056B2 (en) 2003-03-31 2006-09-19 Sharp Kabushiki Kaisha Thin film transistor array substrate and method for repairing the same
KR100711365B1 (en) * 2002-03-19 2007-04-27 엔이씨 도낀 가부시끼가이샤 Electronic device for supplying dc power and having noise filter mounted with excellent noise reduction
JP2012048264A (en) * 2005-01-31 2012-03-08 Semiconductor Energy Lab Co Ltd Display device

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5977563A (en) * 1996-05-09 1999-11-02 Sharp Kabushiki Kaisha Active matrix substrate and correcting method of structural defect
US6297520B1 (en) 1996-05-09 2001-10-02 Sharp Kabushiki Kaisha Active matrix substrate and correcting method of structural defect thereof
US6710827B2 (en) 2000-03-31 2004-03-23 Sharp Kabushiki Kaisha Liquid crystal display device having sub-pixel electrodes and defect correction method therefor
KR100529985B1 (en) * 2000-03-31 2005-11-22 샤프 가부시키가이샤 Liquid crystal display device and defect correction method therefor
KR100711365B1 (en) * 2002-03-19 2007-04-27 엔이씨 도낀 가부시끼가이샤 Electronic device for supplying dc power and having noise filter mounted with excellent noise reduction
US7110056B2 (en) 2003-03-31 2006-09-19 Sharp Kabushiki Kaisha Thin film transistor array substrate and method for repairing the same
JP2012048264A (en) * 2005-01-31 2012-03-08 Semiconductor Energy Lab Co Ltd Display device
US8629440B2 (en) 2005-01-31 2014-01-14 Semiconductor Energy Laboratory Co., Ltd. Display device with defective pixels correction structure
US9257453B2 (en) 2005-01-31 2016-02-09 Semiconductor Energy Laboratory Co., Ltd. Display device including first to sixth transistors and light-emitting element
US9613988B2 (en) 2005-01-31 2017-04-04 Semiconductor Energy Laboratory Co., Ltd. Display device having narrower wiring regions
US10573705B2 (en) 2005-01-31 2020-02-25 Semiconductor Energy Laboratory Co., Ltd. Display device with defective pixel correction
US10700156B2 (en) 2005-01-31 2020-06-30 Semiconductor Energy Laboratory Co., Ltd. Display device
US11362165B2 (en) 2005-01-31 2022-06-14 Semiconductor Energy Laboratory Co., Ltd. Display device
US11910676B2 (en) 2005-01-31 2024-02-20 Semiconductor Energy Laboratory Co., Ltd. Display device

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