JPH05160613A - High frequency substrate - Google Patents

High frequency substrate

Info

Publication number
JPH05160613A
JPH05160613A JP29681291A JP29681291A JPH05160613A JP H05160613 A JPH05160613 A JP H05160613A JP 29681291 A JP29681291 A JP 29681291A JP 29681291 A JP29681291 A JP 29681291A JP H05160613 A JPH05160613 A JP H05160613A
Authority
JP
Japan
Prior art keywords
land
coupler
substrate
signal
signal output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP29681291A
Other languages
Japanese (ja)
Other versions
JP3313126B2 (en
Inventor
Chikao Kume
千佳夫 久米
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP29681291A priority Critical patent/JP3313126B2/en
Publication of JPH05160613A publication Critical patent/JPH05160613A/en
Application granted granted Critical
Publication of JP3313126B2 publication Critical patent/JP3313126B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0213Electrical arrangements not otherwise provided for
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/141One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters

Landscapes

  • Combinations Of Printed Boards (AREA)

Abstract

PURPOSE:To make a device small-sized and thin by providing a a coupler substrate of only a coupler part and a main substrate on which circuit elements are mounted and soldering the coupler substrate to the main substrate to give a margin to the height of mounting of the device using a coupler. CONSTITUTION:A main signal output land 12, a couple signal input land 13, a ground land 14, a through signal input land 15, and an isolate signal input land 16 are formed on the surface of a main substrate 11. A coupler substrate 5 consists of a four-layered substrate. That is, a main signal input land 6, a couple signal output land 7, a ground land 8, a through signal output land 9, and an isolate signal output land 10 are formed on substrates of first and fourth layers of the coupler substrate 6. Lands 12 and 6, lands 13 and 7, lands 14 and 8, lands 15 and 9, and lands 16 and 10 are soldered with each other respectively to connect these high frequency substrates. As the result, the thickness of the main substrate 11 is reduced, and a margin is given to the height of mounting of the device using the coupler, and the device can be effectively made small-sized and thin.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、カプラを含む高周波基
板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency board including a coupler.

【0002】[0002]

【従来の技術】従来から、高周波信号を結合させるため
にカプラを内包する4層の基板を用いていた。図6は従
来のカプラを内包する基板の実施例の説明図である。1
はカプラを内包する4層の基板、2,3,4は回路素子
である。
2. Description of the Related Art Conventionally, a four-layer substrate containing a coupler has been used for coupling a high frequency signal. FIG. 6 is an explanatory view of an embodiment of a substrate including a conventional coupler. 1
Is a four-layer substrate containing a coupler, and 2, 3 and 4 are circuit elements.

【0003】[0003]

【発明が解決しようとする課題】しかしながら従来のよ
うにカプラを内包する構成では、カプラはある程度厚く
なってしまうので、全体的に厚くなってしまうという問
題があった。すなわち結合度の高いカプラを形成するた
めには、第2層パターンと第3層パターンの距離に対し
第2層パターンと第1層のグランドパターンの距離ある
いは第3層パターンと第4層のグランドパターンの距離
が大きくなり、かつ第2層パターンと第3層パターンの
距離は0.1mmが限度であるためそれだけ基板が厚くな
ってしまう。
However, in the conventional structure in which the coupler is included, the coupler becomes thick to some extent, so that there is a problem in that it becomes thick as a whole. That is, in order to form a coupler having a high degree of coupling, the distance between the second layer pattern and the third layer pattern or the distance between the second layer pattern and the first layer ground pattern or the third layer pattern and the fourth layer ground is required to form a highly coupled coupler. Since the pattern distance becomes large and the distance between the second layer pattern and the third layer pattern is limited to 0.1 mm, the substrate becomes thicker accordingly.

【0004】[0004]

【課題を解決するための手段】本発明は上記問題点を解
決するために、カプラ部のみのカプラ基板と回路素子を
搭載する親基板を備え、カプラ基板を親基板に半田付け
するものである。
In order to solve the above problems, the present invention is provided with a coupler substrate having only a coupler section and a mother board on which a circuit element is mounted, and the coupler board is soldered to the mother board. ..

【0005】[0005]

【作用】本発明は前記した構成により、親基板の厚さが
薄くなるため、結合度の高いカプラを用いる装置の実装
の高さに余裕ができかつ装置の小型化及び薄型化に有効
となる。
According to the present invention, since the thickness of the parent board is reduced by the above-described structure, the mounting height of the device using the coupler having a high degree of coupling can be afforded, and it is effective for downsizing and thinning of the device. ..

【0006】[0006]

【実施例】図1は本発明の一実施例におけるカプラを含
む高周波基板の構成図である。5はカプラ基板であり、
4層の基板により構成されている。6は主信号を入力す
る主信号入力ランド、7は主信号と結合した信号を出力
するカップル信号出力ランド、8はグランドランド、9
は主信号の通過信号を出力するスルー信号出力ランド、
10は主信号とのアイソレート信号を出力するアイソレ
ート信号出力ランドである。これら主信号入力ランド6
及びカップル信号出力ランド7及びグランドランド8及
びスルー信号出力ランド9及びアイソレート信号出力ラ
ンド10は、図2に示すようにカプラ基板5の第1層及
び第4層の基板に形成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of a high frequency substrate including a coupler according to an embodiment of the present invention. 5 is a coupler substrate,
It is composed of a four-layer substrate. 6 is a main signal input land for inputting a main signal, 7 is a couple signal output land for outputting a signal combined with the main signal, 8 is a ground land, 9
Is a through signal output land that outputs a passing signal of the main signal,
Reference numeral 10 is an isolated signal output land for outputting an isolated signal from the main signal. These main signal input land 6
The coupled signal output land 7, the ground land 8, the through signal output land 9, and the isolated signal output land 10 are formed on the first and fourth layers of the coupler substrate 5, as shown in FIG.

【0007】11は親基板、12は主信号入力ランド6
と位置が対応する主信号出力ランド、13はカップル信
号出力ランド7と位置が対応するカップル信号入力ラン
ド、14はグランドランド8と位置が対応するグランド
ランド、15はスルー信号出力ランド9と位置が対応す
るスルー信号入力ランド、16はアイソレート信号出力
ランド10と位置が対応するアイソレート信号入力ラン
ドである。これら主信号出力ランド12及びカップル信
号入力ランド13及びグランドランド14及びスルー信
号入力ランド15及びアイソレート信号入力ランド16
はそれぞれ親基板11の表面に形成されている。
Reference numeral 11 is a main board, and 12 is a main signal input land 6.
, 13 is a main signal output land whose position corresponds, 13 is a couple signal input land whose position corresponds to the couple signal output land 7, 14 is a ground land whose position corresponds to the ground land 8, and 15 is a through signal output land 9 and the position The corresponding through signal input land, 16 is an isolated signal input land whose position corresponds to that of the isolated signal output land 10. The main signal output land 12, the couple signal input land 13, the ground land 14, the through signal input land 15, and the isolated signal input land 16
Are formed on the surface of the parent substrate 11, respectively.

【0008】図2は図1のカプラ基板の組立図である。
17は第1層基板である。また第4層基板は第1層基板
17と同一の構成であるため同一の番号を付す。18は
第2層基板、19は第3層基板である。上記4つの層は
絶縁層を挟んで重ねあわされる。また斜線が施された部
分は導電箔を示す。
FIG. 2 is an assembly view of the coupler substrate of FIG.
Reference numeral 17 is a first layer substrate. Further, the fourth layer substrate has the same configuration as the first layer substrate 17, and therefore, the same numbers are attached. Reference numeral 18 is a second layer substrate, and 19 is a third layer substrate. The above four layers are overlapped with each other with an insulating layer interposed therebetween. The shaded area indicates the conductive foil.

【0009】以上のように構成された高周波基板につい
て接続方法を説明する。すなわち主信号出力ランド12
と主信号入力ランド6、カップル信号入力ランド13と
カップル信号出力ランド7、グランドランド14とグラ
ンドランド8、スルー信号入力ランド15とスルー信号
出力ランド9、アイソレート信号入力ランド16とアイ
ソレート信号出力ランド10とをそれぞれ半田付けす
る。
A connection method for the high-frequency board constructed as described above will be described. That is, the main signal output land 12
And main signal input land 6, couple signal input land 13 and couple signal output land 7, ground land 14 and ground land 8, through signal input land 15 and through signal output land 9, isolated signal input land 16 and isolated signal output Solder the lands 10 respectively.

【0010】図3は本発明の一実施例におけるカプラ基
板の第1層目から見たパターン図である。図3(a)は
第1層基板17、図3(b)は第2層基板18、図3
(c)は第3層基板19をそれぞれ示す。20は第1層
基板及び第4層基板のパターンと第2層基板をつなぐス
ルーホール、21は第1層基板及び第4層基板のパター
ンと第3層基板のパターンをつなぐスルーホール、22
は第1層基板のパターンと第4層基板のパターンをつな
ぐスルーホールである。
FIG. 3 is a pattern diagram seen from the first layer of the coupler substrate in one embodiment of the present invention. 3A is a first layer substrate 17, FIG. 3B is a second layer substrate 18, and FIG.
(C) shows the third layer substrate 19, respectively. Reference numeral 20 is a through hole that connects the patterns of the first layer substrate and the fourth layer substrate and the second layer substrate, 21 is a through hole that connects the patterns of the first layer substrate and the fourth layer substrate and the pattern of the third layer substrate, 22
Is a through hole that connects the pattern of the first layer substrate and the pattern of the fourth layer substrate.

【0011】主信号入力ランド6に入力ランドに入力し
た主信号はスルーホール20を通って第2層基板のパタ
ーンにいたる。第2層基板に至った主信号は第3層基板
のパターンと結合を起こし、主信号のエネルギーの一部
が第3層パターンに移る。第3層パターンに主信号成分
のエネルギーが移ると第3層パターンにカップル信号が
起こる。カップル信号はスルーホール21を通ってカッ
プル信号出力ランド7に至る。
The main signal input to the input land of the main signal input land 6 passes through the through hole 20 and reaches the pattern of the second layer substrate. The main signal reaching the second layer substrate is coupled with the pattern of the third layer substrate, and part of the energy of the main signal is transferred to the third layer pattern. When the energy of the main signal component is transferred to the third layer pattern, a couple signal is generated in the third layer pattern. The couple signal reaches the couple signal output land 7 through the through hole 21.

【0012】一方主信号は第2層パターンで減衰しスル
ー信号となる。スルー信号はスルーホール20を通って
スルー信号出力ランド9に至る。
On the other hand, the main signal is attenuated by the second layer pattern and becomes a through signal. The through signal reaches the through signal output land 9 through the through hole 20.

【0013】図4は本発明のカプラ基板の応用例の周波
数fRFの主信号及び周波数fLOの局発信号を入力し
周波数fRF−2fLOの信号を出力するミキサ回路で
ある。24は周波数(fRF+fLO)/2で3dBの
結合度のミキサ基板、25はコンデンサ、26はコイ
ル、27はダイオード、28は抵抗器、29はコンデン
サ、30は抵抗器、31は出力ピンである。
FIG. 4 shows a mixer circuit of an application example of the coupler substrate of the present invention, which inputs a main signal of frequency fRF and a local signal of frequency fLO and outputs a signal of frequencies fRF-2fLO. 24 is a mixer substrate having a coupling degree of 3 dB at a frequency (fRF + fLO) / 2, 25 is a capacitor, 26 is a coil, 27 is a diode, 28 is a resistor, 29 is a capacitor, 30 is a resistor, and 31 is an output pin.

【0014】アイソレート信号入力ランドに局発信号を
入力するとカップル信号出力ランドに局発信号のスルー
信号が出力されかつスルー信号出力ランドに局発信号の
カップル信号が出力される。局発信号のスルー信号及び
局発信号のカップル信号はコンデンサ25を通りダイオ
ード27に至る。ダイオード27は局発信号の倍の周波
数2fLOでオン・オフを繰り返すため、周波数2fL
Oの信号が発生する。
When the local signal is input to the isolated signal input land, the through signal of the local signal is output to the couple signal output land and the couple signal of the local signal is output to the through signal output land. The through signal of the local oscillator signal and the couple signal of the local oscillator signal pass through the capacitor 25 and reach the diode 27. Since the diode 27 is repeatedly turned on and off at a frequency 2fLO that is twice the frequency of the local oscillation signal, the frequency 2fL
An O signal is generated.

【0015】周波数2fLOの信号は主信号入力ランド
に主信号を入力するとカップル信号出力ランドにカップ
ル信号を出力しかつスルー信号出力ランドにスルー信号
を出力する。スルー信号は周波数2fLOの信号と合成
され合成信号aとなる。また、カップル信号は周波数2
fLOの信号と合成され合成信号bとなる。
When the main signal is input to the main signal input land, the signal of frequency 2fLO outputs the couple signal to the couple signal output land and outputs the through signal to the through signal output land. The through signal is combined with the signal of frequency 2fLO to form a combined signal a. The frequency of the couple signal is 2
It is combined with the signal of fLO to form a combined signal b.

【0016】合成信号aはコンデンサ29を介し出力端
子に至り、合成信号bは抵抗器28を介して出力端子に
至る。さらに、出力端子で合成信号aと合成信号bが合
成されてfRF−2fLOの信号となる。
The composite signal a reaches the output terminal via the capacitor 29, and the composite signal b reaches the output terminal via the resistor 28. Further, the combined signal a and the combined signal b are combined at the output terminal to become a signal of fRF-2fLO.

【0017】図5は本発明の一実施例におけるカプラを
含む高周波基板の説明図である。32はカプラ基板5を
親基板11に半田付けしたカプラを含む高周波基板、3
3,34,35は回路を構成する回路素子である。これ
ら回路素子33,34,35は親基板11に搭載され
る。カプラ部以外では回路の厚さは親基板11の厚さt
1と回路素子35の厚さt2で決まる。
FIG. 5 is an explanatory diagram of a high frequency substrate including a coupler according to an embodiment of the present invention. Reference numeral 32 denotes a high frequency board including a coupler in which the coupler board 5 is soldered to the parent board 11.
Reference numerals 3, 34 and 35 are circuit elements that form a circuit. These circuit elements 33, 34, 35 are mounted on the parent board 11. The thickness of the circuit other than the coupler is the thickness t of the parent board 11.
1 and the thickness t2 of the circuit element 35.

【0018】[0018]

【発明の効果】以上のように本発明は、カプラ基板を親
基板と半田付けすることによりカプラ部を除いてカプラ
を含む高周波基板の厚さが薄くなるため、高周波基板上
の空間に余裕ができ装置の薄型化が図れる。
As described above, according to the present invention, by soldering the coupler substrate to the parent substrate, the thickness of the high-frequency substrate including the coupler is reduced except for the coupler portion, so that the space on the high-frequency substrate has a margin. As a result, the device can be made thinner.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における高周波基板およびカ
プラ基板の外観斜視図
FIG. 1 is an external perspective view of a high-frequency board and a coupler board according to an embodiment of the present invention.

【図2】同実施例のカプラ基板の分解斜視図FIG. 2 is an exploded perspective view of a coupler substrate of the same embodiment.

【図3】(a)は第1層基板17のパターン図 (b)は第2層基板18のパターン図 (b)は第3層基板19のパターン図3A is a pattern diagram of a first layer substrate 17; FIG. 3B is a pattern diagram of a second layer substrate 18; FIG. 3B is a pattern diagram of a third layer substrate 19;

【図4】同カプラ基板を応用したミキサ回路の回路図FIG. 4 is a circuit diagram of a mixer circuit to which the coupler substrate is applied.

【図5】同カプラ基板を含む高周波基板の説明図FIG. 5 is an explanatory view of a high frequency board including the coupler board.

【図6】従来のカプラを内包する基板の説明図FIG. 6 is an explanatory view of a substrate including a conventional coupler.

【符号の説明】[Explanation of symbols]

5 カプラ基板 6 主信号入力ランド 7 カップル信号出力ランド 8 グランドランド 9 スルー信号出力ランド 10 アイソレート信号出力ランド 11 親基板 12 主信号出力ランド 13 カップル信号入力ランド 14 グランドランド 15 スルー信号入力ランド 16 アイソレート信号入力ランド 17 第1層基板 18 第2層基板 19 第3層基板 5 Coupler board 6 Main signal input land 7 Couple signal output land 8 Ground land 9 Through signal output land 10 Isolated signal output land 11 Parent board 12 Main signal output land 13 Couple signal input land 14 Ground land 15 Through signal input land 16 Iso Rate signal input land 17 First layer substrate 18 Second layer substrate 19 Third layer substrate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】複数の基板を積層し、最外部の基板に少な
くとも信号入力ランド及び信号出力ランドを形成したカ
プラ基板と、前記カプラ基板の信号入力ランドの位置に
対応する信号出力ランド及び前記カプラ基板の信号出力
ランドの位置に対応する信号入力ランドを表面に形成し
た親基板を備え、前記カプラ基板の信号入力ランドおよ
び信号出力ランドを前記親基板の信号出力ランドおよび
信号入力ランドに半田付けした事を特徴とする高周波基
板。
1. A coupler substrate in which a plurality of substrates are laminated and at least a signal input land and a signal output land are formed on the outermost substrate, and a signal output land corresponding to the position of the signal input land of the coupler substrate and the coupler. A parent board having a signal input land corresponding to the position of the signal output land on the board is formed on the surface, and the signal input land and the signal output land of the coupler board are soldered to the signal output land and the signal input land of the parent board. A high-frequency board that is characterized.
JP29681291A 1991-11-13 1991-11-13 High frequency board Expired - Fee Related JP3313126B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29681291A JP3313126B2 (en) 1991-11-13 1991-11-13 High frequency board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29681291A JP3313126B2 (en) 1991-11-13 1991-11-13 High frequency board

Publications (2)

Publication Number Publication Date
JPH05160613A true JPH05160613A (en) 1993-06-25
JP3313126B2 JP3313126B2 (en) 2002-08-12

Family

ID=17838469

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29681291A Expired - Fee Related JP3313126B2 (en) 1991-11-13 1991-11-13 High frequency board

Country Status (1)

Country Link
JP (1) JP3313126B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106171049A (en) * 2014-12-01 2016-11-30 株式会社村田制作所 Electronic equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106171049A (en) * 2014-12-01 2016-11-30 株式会社村田制作所 Electronic equipment
CN106171049B (en) * 2014-12-01 2020-04-03 株式会社村田制作所 Electronic device

Also Published As

Publication number Publication date
JP3313126B2 (en) 2002-08-12

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