JP2001339170A - Multilayer wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a multilayer wiring board having parallel wiring groups intersecting perpendicularly to each other in which the effect of EMI noise is reduced along with the effect of crosstalk noise. SOLUTION: A multilayer wiring body comprises a first parallel wiring group L1 formed on a first insulation layer (I3) to direct toward respective intersection side in each specified region, a second parallel wiring group L2 formed on a second insulation layer (I4) which is formed on the first insulation layer (I3) and intersecting respective first parallel wiring groups L1 perpendicularly in each region, and a through wiring group T for connecting them electrically. The first parallel wiring group L1 has respective ground wirings G1 in each region and it is surrounded by an annular ground wiring GR formed on the outer circumferential part of the first insulation layer (I3) wherein the annular ground wiring GR is connected electrically with the ground wirings G1 thus producing a multilayer wiring board. Effect of EMI noise can be reduced by the annular ground wirings GR and the second parallel wiring group L2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board used for an electronic circuit board or the like, and more particularly to a wiring structure in a multilayer wiring board on which a semiconductor element operating at a high speed is mounted.

[0002]

2. Description of the Related Art Conventionally, in a multilayer wiring board on which a semiconductor element such as a semiconductor integrated circuit element is mounted and which is used for an electronic circuit board or the like, an insulating material made of ceramics such as alumina is used for forming a wiring conductor for internal wiring. Layers and wiring conductors made of a refractory metal such as tungsten (W) are alternately laminated to form a multilayer wiring board.

In a conventional multilayer wiring board, signal wirings of internal wiring wiring conductors usually have a strip wiring structure, and a so-called solid pattern is formed above and below wiring conductors formed as signal wirings via insulating layers. A ground (ground) layer or a power supply layer having a wide area of the shape was formed.

Further, with the increase in the speed of electric signals handled by the multilayer wiring board, a polyimide resin or an epoxy resin having a relatively small relative dielectric constant of 3.5 to 5 instead of an alumina ceramic having a relative dielectric constant of about 10 instead of an insulating layer. And a conductive layer for internal wiring made of copper (Cu) is formed on the insulating layer by using a thin film forming technique such as a vapor deposition method such as a vapor deposition method or a sputtering method. By forming a wiring conductor in a pattern and multiplying the insulating layer and the wiring conductor into layers, a multilayer wiring board having a high density, a high function and a high speed operation of a semiconductor element has been obtained.

On the other hand, the wiring structure of the internal wiring of the multilayer wiring board is designed to reduce ringing noise and reduce crosstalk between signal wirings by matching the impedance of the wirings, and to realize high-density wiring. A structure has been proposed in which a group of parallel wirings is formed on the upper surface of an insulating layer, and this is multi-layered to electrically connect predetermined wirings of the wiring group of each layer via through conductors such as via conductors and through-hole conductors. ing.

In a multilayer wiring board having such a parallel wiring group, an electronic component such as a semiconductor element mounted on the multilayer wiring board is electrically connected to a mounting board on which the multilayer wiring board is mounted. Then, an appropriate wiring is selected from each parallel wiring group in the multilayer wiring board, and the connection between the wirings between different wiring layers is performed via a through conductor such as a via conductor.

[0007] According to such a multilayer wiring board, the number of wiring layers can be reduced as compared with the case where the signal lines are constituted by strip lines, and the signal wirings within the parallel wiring groups and between the parallel wiring groups. The crosstalk between them can be reduced.

[0008]

However, in the conventional multilayer wiring board having a group of parallel wirings, unnecessary electromagnetic waves are radiated from various electronic devices and the like as the speed of electronic components such as semiconductor elements mounted increases. EMI (Electromagnetic Interference) that this electromagnetic wave penetrates into the electronic device or other electric devices in the vicinity, affects the electronic circuit as noise, and causes the electronic device to malfunction.
ectro-Magnetic Interference (Electromagnetic Interference) Noise has become a problem.

On the other hand, the present inventor has disclosed in Japanese Patent Application No. 11-1964.
In No. 4, in each of the divided regions formed on the first insulating layer and divided by two to four straight lines having an intersection at the center of the first insulating layer so that the central angles are substantially equal to each other, A first wiring layer composed of a group of parallel wirings directed toward the intersection and a second insulating layer laminated on the first insulating layer, and each of the divided regions are orthogonal to the first wiring layer. There has been proposed a multilayer wiring board including a laminated wiring body for electrically connecting a second wiring layer including a parallel wiring group with a through conductor group.

According to this, the wiring of the parallel wiring group forming the second wiring layer has a substantially annular wiring structure so as to surround the central portion of the insulating layer, thereby reducing crosstalk noise between the wirings. In addition to the above, the present invention has an effect as a measure against EMI noise. In particular, the second
In the case where the wiring layer has an annular wiring formed by connecting the wirings of the respective divided regions, and the outermost annular wiring is a ground wiring, it is very effective as a measure against EMI noise.

However, even in this multilayer wiring board, when a more complete measure against EMI noise is required, the first
Is composed of a group of parallel wirings directed toward the center of the insulating layer in each of the divided regions. Since the parallel wirings are formed separately from each other, intrusion of EMI noise from outside into the wiring layers. Cannot be completely suppressed, and with the further increase in the speed of semiconductor devices and the like, there has been a tendency that it is difficult to maintain a high level of stable electrical characteristics and perform a good operation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object the purpose of the present invention to be constituted by a group of parallel wirings which are alternately stacked in a predetermined divisional area so as to be orthogonal to each other. While having a wiring structure for reducing crosstalk between wirings, it can operate at high speed, and can reduce the influence of EMI noise even on a parallel wiring group directed toward the center of the insulating layer in each of the divided regions. An object of the present invention is to provide a multilayer wiring board suitable for an electronic circuit board on which electronic components such as semiconductor elements are mounted.

[0013]

A multilayer wiring board according to the present invention is formed on a first insulating layer, and has a center angle of approximately two to four straight lines having an intersection at the center of the first insulating layer. A first parallel wiring group directed toward the intersection and a second insulating layer laminated on the first insulating layer are formed in each of the divided regions so as to be equal to each other. A second parallel wiring group orthogonal to the first parallel wiring group; and a through-conductor group that electrically connects the first and second parallel wiring groups. The first parallel wiring group has a ground wiring in each of the divided regions and is surrounded by an annular ground wiring formed on an outer peripheral portion of the first insulating layer,
In addition, the ground wiring is electrically connected to the annular ground wiring.

Further, in the multilayer wiring board according to the present invention, the first and second parallel wiring groups each have a plurality of signal wirings and a power supply wiring or a ground wiring adjacent to each signal wiring. It is characterized by the following.

According to the multilayer wiring board of the present invention, the first and second parallel wiring groups are arranged perpendicularly to each other in each of the divided regions, stacked vertically, and electrically connected by the through conductor group. The cross-talk noise between the wirings of the parallel wiring groups can be reduced and minimized, and the wirings of the parallel wiring group forming the second wiring layer are located at the center of the insulating layer. In this case, a substantially ring-shaped wiring structure is formed so as to surround the portion, so that crosstalk noise between the wirings can be reduced, and it has an effect as a measure against EMI noise. The first ground wiring in the first parallel wiring group is electrically connected to the annular ground wiring surrounded by the annular ground wiring formed on the outer peripheral portion of the first insulating layer.
Ground wiring in each of the divided regions in the parallel wiring group can be kept at the same ground potential, so that simultaneous switching noise accompanying the operation of the semiconductor element and the like can be reduced, and the circular ground wiring Since it also functions as a shield, it is possible to effectively reduce the penetration of EMI noise into the first parallel wiring group.

Also, in the second parallel wiring group, the parallel wiring in each of the divided regions has a substantially annular wiring structure so as to surround the center of the second insulating layer. E can be reduced
The effect of the MI noise can be reduced. In particular, the second
In the case where the wiring layer has a ring wiring in which the wirings of the respective divided areas are electrically connected, and the outermost ring wiring is a ground wiring, the influence of the EMI noise is reduced to the first parallel wiring group. Can be effectively reduced in the same manner as in the case of the annular ground wiring.

Thus, according to the multilayer circuit board of the present invention, the crosstalk noise between the wirings can be reduced by the laminated wiring body, and the potential of the ground wiring is stably maintained for the first parallel wiring group. It is possible to reduce simultaneous switching noise and effectively reduce the intrusion of EMI noise. An electronic component such as a semiconductor element that operates at a high speed can be accurately and stably operated without causing a malfunction or the like.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multilayer wiring board according to the present invention will be described in detail based on an embodiment shown in the accompanying drawings.

One embodiment of a multilayer wiring board according to the present invention is shown in FIGS. 1 to 6 are top views of respective insulating layers in an example of a multilayer wiring board according to an embodiment of the present invention. FIG. 1 shows a first insulating layer on which an integrated circuit element is mounted. FIG. 2 is a top view of a second insulating layer thereunder, FIG. 3 is a top view of a third insulating layer below, FIG.
5 is a top view of the fourth insulating layer, FIG. 5 is a top view of the fifth insulating layer, and FIG. 6 is a bottom view of the fifth insulating layer.

In these figures, I1 to I5 are first to fifth insulating layers, respectively. In this example, the first insulating layer I1 is the uppermost layer of the multilayer wiring board. The fifth insulating layer I5 is the lowermost layer. M is an upper surface of the first insulating layer I1, that is, a mounting region of a semiconductor element such as an integrated circuit element provided at the center of the upper surface of the multilayer wiring board.

C is a line conductor of a strip line portion disposed below the mounting area M and on the upper surfaces of the third and fifth insulating layers I3 and I5. In this example, the line conductor C on the third insulating layer I3 includes a ground conductor layer GL formed on the surface of the second insulating layer I2 and a fourth insulating layer I2.
A strip line portion is formed by the power supply conductor layer PL formed on the surface of No. 4. Further, the plurality of line conductors C are respectively led out to the mounting area M on the surface of the multilayer wiring board via the through-hole conductor group TC for connection, and are electrically connected to the respective terminal electrodes of the mounted semiconductor element. In FIGS. 1 to 6, each through conductor including the through conductor group TC for connection is indicated by a circle.

GL is a ground conductor layer formed on the surface of the second insulating layer I2. The ground conductor layer GL enables rearrangement for efficiently electrically connecting the semiconductor element to the first parallel wiring group L1 via the line conductor C, and also corresponds to the frequency of the mounted device. By optimizing the area of the ground conductor layer and stabilizing the supply of the potential to the device, the device has a shielding effect against electromagnetic noise. This ground conductor layer GL is appropriately formed on the upper surface of the second conductor layer I2 in the multilayer wiring board in accordance with the specifications of each line conductor C and each parallel wiring group L1, L2 formed below. By forming such a ground conductor layer GL, the ground wiring can be rearranged so that the ground wiring can be efficiently connected between the semiconductor element and the first parallel wiring group L1. A multilayer wiring board having a good shielding effect can be obtained.

Further, PL is a power supply conductor layer formed on the surface of the fourth insulating layer I4. This power supply conductor layer PL
As in the case of the ground conductor layer GL, the rearrangement for efficiently electrically connecting the power supply wiring from the semiconductor element to the first parallel wiring group L1 is enabled. This power supply wiring layer P
L is appropriately formed according to the specification of the multilayer wiring board, similarly to the ground conductor layer GL. By forming such a power supply conductor layer PL, the semiconductor element and the first parallel wiring group L1 are formed. Can be rearranged so that the power supply wiring can be connected efficiently.

The ground conductor layer GL and the power supply conductor layer P
L may be in the form of a lattice if necessary, or may be used by exchanging the power supply and the ground. Whether each of these layers is set to the ground or the power supply may be appropriately selected according to the specifications of the multilayer wiring board.

The through conductor group TC for connection penetrates through these layers while being electrically insulated from the ground conductor layer GL.

Next, L1 and L2 are first and second parallel wiring groups formed on the upper surfaces of the third to fifth insulating layers I3 to I5, respectively. In this example, the first parallel wiring group L1 is formed on the upper surface of the third and fifth insulating layers I3 and I5, and the second parallel wiring group L2 is formed on the upper surface of the fourth insulating layer I4. It is laminated. P1 and P2 are power supply wires in the first and second parallel wiring groups L1 and L2, G1 and G2 are ground wires in the first and second parallel wiring groups L1 and L2, respectively, and S1 and S2 are The signal wirings in the first and second parallel wiring groups L1 and L2 are shown.

The plurality of signal lines S1 and S2 arranged on the same plane may transmit different signals, respectively, and the plurality of power lines P1 and S1 arranged on the same plane may be used.
P2 may supply different powers.

Further, the connection with the external electric circuit is electrically connected from each of the second parallel wiring group L2 or the first parallel wiring group L1 via the through conductor group TCL for external connection. A connection conductor such as a solder bump is attached to each connection land CL disposed on the lower surface of the fifth insulating layer I5, and these are electrically connected to connection electrodes of an external electric circuit. It is. CLP of these many connection lands CL is the power supply wiring P1 or P2.
Are connected to the power supply connection land, and CLG is the ground wiring G.
1 or G2 is connected to the ground connection land by CLS.
Indicates a signal connection land to which the signal wiring S1 or S2 is connected. In addition, the ground conductor layer GL, the power supply conductor layer PL, the line conductor C, and the like are also electrically connected to the connection lands CL via the through conductors as necessary.

Third and fifth insulating layers I3 and I3
5 has an intersection in a mounting area M corresponding to the center of each of the insulating layers I3 and I5.
In each of the divided areas divided by two straight lines indicated by alternate long and short dash lines in FIG. 5 so that the center angles are substantially equal, each of the divided areas is directed toward the intersection, that is, toward the mounting area M in the center of each of the insulating layers I3 and I5. It is composed of parallel wiring groups. here,
The two intersections along the diagonal of each of the substantially square insulating layers I3 and I5 are located in the mounting area M, and have a center angle of about 90.
An example is shown in which four divided areas are set so as to be different degrees.

The second parallel wiring group L2 formed on the fourth insulating layer I4 has a first parallel wiring group in each of the divided regions (indicated by a dashed line in FIG. 4). It is composed of a parallel wiring group orthogonal to the parallel wiring group of L1. Here, in the second parallel wiring group L2, the power supply wiring P2 and the ground wiring G
2 is connected to form a substantially square ring wiring having wiring parallel to each side of the substantially square fourth insulating layer I4.

The first parallel wiring group L1 and the second parallel wiring group L2 correspond to the through conductor group T formed on the third and fourth insulating layers I3 and I4. Wirings are electrically connected at appropriate places, thereby forming a parallel wiring portion which is a laminated wiring body in which a group of parallel wirings orthogonal to each of the divided regions is formed.

In this example, the first and second parallel wiring groups L1 and L2 are connected to the signal wirings S1 and S2 by the power supply wiring P1.
P2 or ground wirings G1 and G2 are arranged adjacent to each other. Thereby, the same insulating layers I3 to I3
5 between the signal lines S1 and S2 on the same plane is electromagnetically cut off, so that crosstalk noise between the left and right signal lines S1 and S2 on the same plane can be reduced favorably.

The arrangement of the signal wirings S1 and S2 is appropriately set according to the specifications of the multilayer wiring board so that a desired wiring circuit is formed in the parallel wiring groups L1 and L2.

In this example, the power supply conductor layer PL is used as a power supply wiring adjacent to a part of the signal wiring S2 of the second parallel wiring group L2. In the case where a group of parallel wirings and a strip line portion are provided, such a modification may be made.

Further, by always making the power supply lines P1 and P2 or the ground lines G1 and G2 adjacent to the signal lines S1 and S2, crosstalk noise between the signal lines S1 and S2 can be cut off and effectively reduced. it can. Further, the mutual coupling between the power supply wirings P1 and P2 and the signal wirings S1 and S2 and the ground wirings G1 and G2 and the signal wirings S1 and S2 on the same plane is maximized, and the current path of the signal wirings S1 and S2 can be minimized. . For this reason, the inductance value from the signal wirings S1 and S2 to the power supply wirings P1 and P2 and the ground wirings G1 and G2 can be reduced, and power supply noise and ground noise at the time of device switching can be effectively reduced. .

This is because the first parallel wiring group L1
Below or the second parallel wiring group L2 is further laminated to form a multi-layer structure, these wiring layers also apply.

According to the multilayer wiring board of the present invention, the divided regions are set as described above, and the laminated wiring body in which parallel wiring groups orthogonal to each other are formed in each of the divided regions is provided. The power supply wiring P2 and the ground wiring G2 of the parallel wiring group constituting the second parallel wiring group L2 have a substantially ring-shaped wiring structure so as to surround the center of the fourth insulating layer I4, and are further disposed in a ring shape. By optimizing the power supply wiring P2 and the grounding wiring G2, an effect of shielding the intrusion of EMI noise from the outside and the radiation of unnecessary electromagnetic wave noise to the outside is obtained, and the crosstalk noise between the signal wirings is reduced. In addition to this, it is effective as an EMI measure.

Further, as shown in FIG. 4, when the outermost peripheral annular wiring in the wiring layer is the ground wiring G2 as shown in FIG. 4, the area of the annular ground wiring G2 is By optimizing the connection with the through conductor group and the through conductor group, a more effective shielding effect against EMI noise can be obtained, and effective EMI countermeasures can be taken.

The first parallel wiring group L1 is formed on the third and fifth insulating layers I3 and I5, that is, in the same plane as the plurality of line conductors C of the strip line portion. For example, one of the signal wirings S1 is a plurality of line conductors C, which are signal wirings, and a mounting area M
Are connected around. Further, the second parallel wiring group L2 is formed on the fourth insulating layer I4, and is electrically connected to the first parallel wiring group L1 by the through conductor group T. Thereby, each terminal electrode of the semiconductor element mounted in the mounting area M and the first or second parallel wiring group L1.
L2 is electrically connected via a strip line section.

According to the multi-layer wiring board of the present invention having such a wiring structure, the wiring connected to the input / output electrodes of the semiconductor elements arranged at a very small pitch and extremely high density is connected to the line conductor C in the strip line portion. The wiring pitch (wiring interval) can be expanded, and the signal wiring, power supply wiring, and ground wiring can be rearranged and expanded into wide-width wiring suitable for the parallel wiring group. Electrical connection can be efficiently performed with a semiconductor element having input / output electrodes of high density while utilizing the excellent electrical characteristics of the wiring group. In addition, a plurality of the strip line portions are stacked and provided until all the signal wires are unfolded, and parallel wiring groups corresponding to the strip line portions are provided in parallel.・ Efficient rearrangement of ground wiring, setting of optimal wiring for connection with surrounding parallel wiring group, and development of parallel wiring group enable multi-layering in response to higher density of semiconductor elements In this case, it is possible to optimize the wiring design and reduce the number of layers.

In the multilayer wiring board of the present invention, the annular ground wiring GR is formed on the outer periphery of the third and fifth insulating layers I3 and I5 to form the first parallel wiring group L1.
, And the ground wiring G1 of the first parallel wiring group L1 is electrically connected to the annular ground wiring GR.

As a result, the potentials of the power supply wiring and the ground wiring fluctuate due to the simultaneous switching of electronic components such as semiconductor elements mounted on the multilayer wiring board, and the power supply wiring in the first parallel wiring group L1 is changed. EMI (Elec) due to high-frequency current from the electromagnetic coupling between the power supply wiring P1 and the ground wiring G1 at the ends of P1 and the ground wiring G1.
tro-Magnetic Interference: Radiation of noise to free space, that is, radiation of EMI noise to free space due to generation of so-called fringe of high-frequency current, is applied to annular ground wiring G.
R can be shielded, and the ground wiring G1 in the first parallel wiring group L1 can be electrically connected at the outer peripheral portion without passing through the through conductor group T, so that the potential drop due to the through conductor group T The potential of the first parallel wiring group L1 can be maintained in a stable state without being affected by the above. As a result, EMI noise generated and radiated from the periphery of the multilayer wiring board can be significantly reduced, and the penetration of EMI noise can also be effectively reduced. Can also keep the potential of the ground wiring G1 stable, reduce simultaneous switching noise, and maintain high-level and stable electric characteristics of mounted electronic components and perform good operation. Becomes

As described above, when the annular ground wiring GR is formed, it is arranged on the outer peripheral portions of the third and fifth insulating layers I3 and I5 so as to surround the first parallel wiring group L1. In the case where the outermost wiring of the parallel wiring group L2 is an annular ground wiring G2, it is preferable to arrange the wiring so as to have a large weight. If the outermost peripheral wiring of the second parallel wiring group L2 is a ring-shaped power supply wiring P1, if the wiring is available, the distance between the first parallel wiring group L1 and the second parallel wiring group L2 is two. It is preferable to arrange the annular ground wiring GR so as to be at least twice as large. As a result, the high frequency current border between the power supply wiring P1 and the ground wiring G1 causes E
It is possible to more effectively prevent the emission of the MI noise into the free space.

In the multilayer wiring board according to the present invention, in addition to the above-described example, the central areas of the third and fifth insulating layers I3 and I5 may be set for the respective divided areas constituting the parallel wiring section. And two central lines having a point of intersection in the mounting region M corresponding to the two substantially straight lines parallel to the sides passing through substantially the center of the sides of the insulating layers I3 and I5, and have a central angle of about 90 degrees. 4 divided areas may be set as described above, and three straight lines may be set so that the central angle is substantially equal to about 60 degrees.
One divided area may be set, and eight divided areas divided by four straight lines so that the central angle is substantially equal to about 45 degrees may be set.

In any of these cases, as in the above example, not only between the left and right signal wirings S1 and S2 on the same plane but also the upper and lower parallel wiring groups are orthogonal, so that the Talk noise can be reduced well,
The current path of the signal lines S1 and S2 can be minimized. Therefore, the inductance value from the signal lines S1 and S2 to the power lines P1 and P2 and the ground lines G1 and G2 can be reduced, and the power supply noise and the ground noise at the time of switching of the device can be effectively reduced. Also,
By providing the annular ground wiring GR for the first parallel wiring group L1, simultaneous switching noise can be reduced and EMI can be reduced.
In addition to reducing the influence of noise, an annular wiring structure is formed such that the power supply wiring P2 and the ground wiring G2 of the parallel wiring group forming the second parallel wiring group L2 surround the center of the insulating layer on which they are formed. In this case, by optimizing the power supply wiring P2 and the grounding wiring G2, it has an effect of shielding the intrusion of EMI noise from the outside and the radiation of unnecessary electromagnetic wave noise to the outside. Can be reduced, and it is also effective as a measure against EMI.

When the outermost peripheral annular wiring of the second parallel wiring group L2 is the ground wiring G2, the area of the annular ground wiring G2 and the connection with the through conductor group are optimized to be more effective. In addition, it has a shielding effect against EMI noise, and effective EMI countermeasures can be taken.

In such a multilayer wiring board of the present invention, for example, an MPU (Micro Processing Unit)
SIC (Application Specific Integrated Circuit)
An electronic component such as a semiconductor device such as a DSP (Digital Signal Processor) is mounted. It is used as a package for storing electronic components such as a package for storing semiconductor devices, a substrate for mounting electronic components, a so-called multi-chip module or multi-chip package on which a large number of semiconductor integrated circuit devices are mounted, or a motherboard. These electronic components are mounted on the surface of the multilayer wiring board by, for example, so-called bump electrodes, or are attached to the mounting portion by an adhesive, a brazing material, or the like, and are also connected to the mounting portion by bonding wires or the like, and through a through conductor or the like. It is electrically connected to the first or second parallel wiring group L1, L2. A connection portion with an external electric circuit and a connection portion with an electronic component such as a semiconductor element to be mounted are not shown.

Here, the through conductor group T is, for example, an insulating layer I
3 and I4 to electrically connect the upper and lower wirings, or the wirings and external connection terminals formed on the surface of the semiconductor element or the multilayer wiring board. A conductor or the like is used and is formed at a location required for connection.

In the multilayer wiring board of the present invention, a multilayer wiring board can be formed by stacking multilayer wiring portions having various wiring structures above and below the multilayer wiring body. For example, a wiring structure of a configuration in which parallel wiring groups are orthogonally stacked like a multilayer wiring body, a wiring structure of a strip line structure, and other specifications required for a multilayer wiring board such as a microstrip line structure and a coplanar line structure. It can be appropriately selected and used according to the conditions.

Further, for example, an electronic circuit may be formed by laminating a polyimide insulating layer and a conductor layer formed by copper vapor deposition. Further, a package for semiconductor element accommodation may be configured by attaching a chip resistor, a thin film resistor, a coil inductor, a cross capacitor, a chip capacitor, and an electrolytic capacitor.

The shape of each insulating layer is not limited to a substantially square shape as shown, but may be a rectangular shape, a rhombic shape, a polygonal shape, or the like.

The first and second parallel wiring groups L1.
L2 is not limited to that formed on the surface of each insulating layer, and may be formed inside each insulating layer.

In the multilayer wiring board of the present invention, each of the insulating layers including the third to fifth insulating layers I3 to I5 is formed by, for example, a ceramic green sheet laminating method.
Using inorganic insulating materials such as aluminum oxide sintered body, aluminum nitride sintered body, silicon carbide based sintered body, silicon nitride based sintered body, mullite sintered body, glass ceramic, or polyimide / epoxy Resin, fluororesin,
Use an organic insulating material such as polynorbornene / benzocyclobutene, or use an electrical insulating material such as a composite insulating material obtained by combining an inorganic insulating powder such as a ceramic powder with a thermosetting resin such as an epoxy resin. Formed.

These insulating layers may be formed so as to form a desired multilayer wiring board by a method such as a green sheet laminating method or a build-up method according to the characteristics of each insulating layer. The thickness of these insulating layers is appropriately set according to the characteristics of the material used, and to satisfy conditions such as mechanical strength and electrical characteristics corresponding to required specifications and ease of forming a through conductor group. Is done.

The first and second parallel wiring groups L1 and L2, the annular ground wiring GR, other wiring layers and the through conductor group T are made of, for example, tungsten, molybdenum, molybdenum-manganese, copper, silver, silver-palladium, etc. Metallized metal powder, or copper, silver, nickel, chromium, titanium,
It is made of a thin film of a metal material such as gold, niobium, or an alloy thereof.

These wiring conductors and through conductors are formed by forming a metal layer by a thick film printing method, for example, by a sputtering method, a vacuum evaporation method, or a plating method according to the characteristics of the respective materials and the method of forming the insulating layer. It is formed in a predetermined pattern shape and size by a lithography method, and is provided on each insulating layer.

The width of each wiring and the distance between the wirings of the first and second parallel wiring groups L1 and L2 are determined according to the characteristics of the material to be used. It is set as appropriate so as to satisfy conditions such as ease of disposition in the device.

The thickness of each of the parallel wiring groups L1 and L2 is 1
It is preferably about 20 μm. This thickness is 1 μm
If it is less than 1, the resistance of the wiring increases, and it tends to be difficult to provide a good power supply to the semiconductor element by the wiring group, secure a stable ground, and propagate a good signal.
On the other hand, if it exceeds 20 μm, the insulation layer laminated thereon may be insufficiently covered, resulting in poor insulation.

Each of the through conductors of the through conductor group T may have a cross-sectional shape other than a circle, an elliptical shape, a rectangular shape such as a square or a rectangle, or any other shape. The position and size are appropriately set according to the characteristics of the material to be used, so as to satisfy conditions such as electrical characteristics corresponding to required specifications and easiness of formation and arrangement on the insulating layer.

For example, when glass ceramics is used for the insulating layer and a conductor material mainly containing copper is used for the parallel wiring group, the thickness of the insulating layer is 100 μm, the line width of the wiring is 100 μm, and the distance between the wirings is 100 μm. Is 100 μm and the diameter of the through conductor is 10
By setting the thickness to 0 μm, the impedance of the signal wiring is set to 50Ω, and the connection between the upper and lower parallel wiring groups can be performed while suppressing the reflection of the high-frequency signal.

It should be noted that the present invention is not limited to the above-described embodiments, and that various changes may be made without departing from the spirit of the present invention. For example, in the above-described embodiment, the present invention has been described as a multilayer wiring board on which a semiconductor element is mounted. However, the present invention may be applied to a semiconductor element housing package for housing a semiconductor element or a multi-chip module. In addition, as an insulating layer, aluminum nitride sintered body considering heat dissipation
A silicon carbide based sintered body or a glass ceramic based sintered body in consideration of a low dielectric constant may be used.

[0062]

According to the multi-layer circuit board of the present invention, the first and second parallel wiring groups are vertically arranged in each of the divided regions, stacked vertically, and electrically connected by the through conductor group. Since the multilayer wiring body is provided, the crosstalk noise between the wirings of the respective parallel wiring groups can be reduced and minimized, and the wiring of the parallel wiring group forming the second wiring layer is formed of an insulating layer. Has a substantially annular wiring structure so as to surround the central portion of the first parallel wiring group, it is possible to reduce crosstalk noise between the wirings, and it is effective as a measure against EMI noise. Is surrounded by an annular ground wiring formed on the outer peripheral portion of the first insulating layer, and the ground wiring in the first parallel wiring group is electrically connected to this annular ground wiring. Since the ground wiring in each of the divided areas can be maintained at the same ground potential, it is possible to reduce simultaneous switching noise due to the operation of the semiconductor element and the like, and the annular ground wiring also functions as an electromagnetic shield. Intrusion of EMI noise into the first parallel wiring group can be effectively reduced.

Also, with respect to the second parallel wiring group, the parallel wiring in each of the divided regions has a substantially ring-shaped wiring structure so as to surround the central portion of the second insulating layer. E can be reduced
The effect of the MI noise can be reduced. In particular, the second
In the case where the wiring layer has a ring wiring in which the wirings of the respective divided areas are electrically connected, and the outermost ring wiring is a ground wiring, the influence of the EMI noise is reduced to the first parallel wiring group. Can be effectively reduced in the same manner as in the case of the annular ground wiring.

As described above, according to the present invention, there is provided a wiring structure constituted by a group of parallel wirings alternately and orthogonally stacked in a predetermined divided region and reducing crosstalk between wirings in the same layer and between upper and lower layers. An electronic circuit mounted with electronic components such as a semiconductor element that operates at high speed and that can reduce the influence of EMI noise even in a parallel wiring group heading toward the center of the insulating layer in each of the divided regions. A multilayer wiring board suitable for a board or the like could be provided.

[Brief description of the drawings]

FIG. 1 is a top view of a first insulating layer, showing an example of an embodiment of a multilayer wiring board of the present invention.

FIG. 2 is a top view of a second insulating layer, showing an example of the embodiment of the multilayer wiring board of the present invention.

FIG. 3 is a top view of a third insulating layer, showing an example of the embodiment of the multilayer wiring board of the present invention.

FIG. 4 is a top view of a fourth insulating layer, showing an example of the embodiment of the multilayer wiring board of the present invention.

FIG. 5 is a top view of a fifth insulating layer, showing an example of the embodiment of the multilayer wiring board of the present invention.

FIG. 6 is a bottom view of a fifth insulating layer, showing an example of an embodiment of the multilayer wiring board of the present invention.

[Explanation of symbols]

 I1 to I5... First to fifth insulating layers L1, L2... First and second parallel wiring groups P1, P2. G1, G2: first and second ground wirings S1, S2: first and fourth signal wirings T: through conductor group GR: Ring ground wiring

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5E338 AA03 CC01 CC04 CC06 CD02 CD11 CD13 CD32 EE13 5E346 AA02 AA04 AA12 AA15 AA29 AA32 AA43 BB02 BB03 BB04 BB06 BB07 BB12 BB13 BB15 BB16 BB20 CC02 CC19 CC37 CC38 CC39 DD16 DD17 EE22 EE32 FF23 FF27 GG02 HH04 HH05 HH06

Claims (2)

[Claims] 1. A method according to claim 1, wherein each of the first and second insulating layers is formed by dividing two to four straight lines having an intersection at the center of the first insulating layer so that the center angles are substantially equal. A second parallel wiring group that is formed on a first parallel wiring group heading toward the intersection and a second insulating layer laminated on the first insulating layer and that is orthogonal to the first parallel wiring group in each of the divided regions. And a through-hole conductor group that electrically connects the first and second parallel wiring groups. The first parallel wiring group is provided in each of the divided regions. A multilayer wiring having a ground wiring, being surrounded by an annular ground wiring formed on an outer peripheral portion of the first insulating layer, wherein the ground wiring is electrically connected to the annular ground wiring. substrate. 2. The device according to claim 1, wherein each of the first and second parallel wiring groups has a plurality of signal wirings and a power supply wiring or a ground wiring adjacent to each signal wiring.
The multilayer wiring board as described in the above.