JPH05160121A - Planar-type semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the occurance of a minute crack on the surface of a staged part of a second layer where a minute crack likely happens by forming a protective film which has an excellent mechanical strength on the surface of the staged part of the second layer of relatively low specific resistance which is formed for the purpose of preventing the accumulation of electric charges on an interface between a semiconductor substrate and a surface protective film. CONSTITUTION:In order to protect a part of a p-n junction 6 between an n-type layer 1 and a p-type region 2 of a device which is exposed to the surface, a silicon oxide film 7 of specific resistance 10<15>-100<16>OMEGAcm and an a-Si film 8 of specific resistance 10<5>-10<6>OMEGAcm are deposited in this order from the substrate, each in the thickness of 1mum. Since the a-Si film 8 has a low specific resistance, it works as a field plate for extending a depletion layer uniformly toward a stopper electrode being at the same potential as a drain electrode when a reverse voltage is applied to the p-n junction 6. This surface protective film has a staged part above an end of the electrode. A nitrode film 9 of 1mum thickness is formed to prevent the occurance of a crack in the staged part of the a-Si film 8. By this method, a planar-type semiconductor device of excellent long-term reliability can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a planar semiconductor device in which a pn junction is exposed on the main surface of a semiconductor substrate and covered with a surface protective film.

[0002]

2. Description of the Related Art p formed by selective diffusion from the surface
Planar type semiconductor devices having an n-junction are suitable for mass production because they do not require processing in the peripheral portion of the substrate, but on the other hand, since the pn junction is exposed on the surface of the semiconductor substrate, it is necessary to secure the breakdown voltage of the pn junction. Is important. For that purpose, a method of covering the vicinity of the pn junction with a surface protective film has been conventionally used.

There are many types of film quality of this surface protective film, and the specific resistance thereof is from 10 ⁵ Ωcm to infinite. In a protective film having an infinite specific resistance, when a voltage is applied for a long period of time, charge may be accumulated near the interface with the semiconductor and the breakdown voltage may be deteriorated. As a method of compensating for such drawbacks,
The surface of the protective film having an infinite specific resistance may be covered with a protective film having a relatively low specific resistance. When the surface is covered with a protective film having a relatively low specific resistance, deterioration of breakdown voltage is unlikely to occur due to the effect of releasing charges in the insulator. Further, since it has an effect as a field plate for averaging the electric field applied to the semiconductor surface, improvement in breakdown voltage can be expected. Amorphous silicon (hereinafter referred to as a-Si) having a specific resistance of about 10 ⁵ to 10 ⁶ Ωcm is most often used as a constituent material of such a protective film having a relatively low specific resistance.

[0004]

However, since a-Si lacks mechanical strength, a-Si is mechanically affected by a temperature change during the manufacturing process or during use in the portion where a-Si covers the step. There is a drawback that the breakdown voltage is deteriorated by applying stress and producing minute cracks.

An object of the present invention is to provide minute cracks on a step portion when a material having a low mechanical strength such as a-Si is used as a material for a protective film having a low specific resistance on a surface protective film. Another object of the present invention is to provide a planar type semiconductor device which eliminates the above-mentioned drawbacks in which the breakdown voltage is deteriorated and the breakdown voltage is deteriorated.

[0006]

In order to achieve the above object, the present invention covers at least the exposed portion of the pn junction on the exposed main surface of the pn junction of the semiconductor substrate and is close to the semiconductor substrate. In a planar semiconductor device having a surface protection film formed by laminating a first layer made of an insulating material on the side and a second layer made of a material having a relatively low specific resistance on the side farther from the semiconductor substrate, at least the second layer It is assumed that the portion in the vicinity of the step portion is covered with an additional protective film made of an insulating material having higher mechanical strength than the material of the second layer. It is effective that the material of the second layer is a-Si, the material of the additional protective film is silicon nitride, and the material of the first layer is silicon oxide.

[0007]

[Function] A protective film having excellent mechanical strength is formed on the surface of the step portion where microcracks easily occur in the second layer having a relatively low specific resistance provided to prevent the accumulation of charges at the interface between the semiconductor substrate and the surface protective film. The addition can prevent the generation of microcracks.

[0008]

FIG. 1 is a vertical DMOS transistor according to an embodiment of the present invention.
Shown on the surface of the n-type silicon substrate 1.
The p-type region 2 is formed by selective diffusion using the mask
Is made. Then, the source electrode is formed on the surface of the p-type region 2.
3, the drain electrode 4 on the back surface, and the stopper electrode on the edge of the substrate.
A pole 5 is provided. N-type layer 1 and p-type region of this device
In order to protect the exposed portion of the pn junction 6 between the two,
Resistivity from board side 10 ¹⁵~Ten¹⁶Ωcm silicon oxide film 7
Specific resistance 10^Five~Ten⁶Ωcm a-Si film 8 is 1 μm each
Are stacked with a thickness of. The specific resistance of the a-Si film 8 is low.
As described above, when the reverse voltage is applied to the pn junction 6, the
Extend toward the stopper electrode 5 that is at the same potential as the rain electrode 4.
The function of the field plate that makes the extension of the depletion layer uniform
Have a heart. This surface protection film is on the peripheral edge of the electrodes 3 and 5.
To prevent it from peeling off from the substrate surface.
There is a step on the end of the pole. A-Si at this step
The nitride film 9 with a thickness of 1 μm is formed to prevent the film 8 from cracking.
Is made. This nitride film 9 is formed on the entire surface by, for example, the CVD method.
After patterning, patterning by photo etching
Then, a width of 10 μm is left only on the step.

In the above-mentioned embodiments, the oxide film, the a-Si film, and the nitride film are used as the surface protective film and the insulating film for mechanical reinforcement, but all of them are made of other materials such as glass or polymer compounds. Etc. can be selected.

[0010]

According to the present invention, the surface protection film covering the pn junction exposed on the surface of the semiconductor substrate of the planar type semiconductor device is formed into two layers of an insulating film and a film having a relatively low specific resistance, and an interface with the substrate is formed. Of the planar semiconductor device with excellent long-term reliability in which the breakdown voltage due to the accumulation of charges or the occurrence of cracks is unlikely to occur by preventing the accumulation of electric charges in Can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view of a vertical DMOS transistor according to an embodiment of the present invention.

[Explanation of Codes] 1 n-type silicon substrate 2 p-type region 3 source electrode 4 drain electrode 5 stopper electrode 6 pn junction 7 oxide film 8 a-Si film 9 nitride film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 29/784 9168-4M H01L 29/78 321 N

Claims (3)

[Claims] 1. A first layer made of an insulating material on a side close to the semiconductor substrate covering at least an exposed portion of the pn junction on the exposed main surface of the pn junction of the semiconductor substrate, and a side farther from the semiconductor substrate. In the case where a surface protective film is formed by laminating a second layer made of a material having a relatively low resistance, at least a portion near the step portion of the second layer is made of an insulating material having higher mechanical strength than the material of the second layer. Planar type semiconductor device characterized by being covered with an additional protective film. 2. The material of the second layer is amorphous silicon, and the material of the additional protective film is silicon nitride.
The planar semiconductor device described. 3. The planar semiconductor device according to claim 1, wherein the material of the first layer is silicon oxide.