CN112242407A - Array substrate and preparation method thereof - Google Patents

Array substrate and preparation method thereof Download PDF

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Publication number
CN112242407A
CN112242407A CN202011097651.9A CN202011097651A CN112242407A CN 112242407 A CN112242407 A CN 112242407A CN 202011097651 A CN202011097651 A CN 202011097651A CN 112242407 A CN112242407 A CN 112242407A
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layer
array substrate
disposed
interlayer dielectric
substrate
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CN112242407B (en
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艾飞
宋德伟
宋继越
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Thin Film Transistor (AREA)

Abstract

The application provides an array substrate and a preparation method thereof, the array substrate comprises a substrate, an active layer, a grid electrode insulating layer, a grid electrode layer, an interlayer dielectric layer and a photosensitive layer, the active layer is arranged on the substrate and comprises a semiconductor part and a first doping part, the first doping part is arranged on two sides of the semiconductor part, the grid electrode insulating layer covers the substrate and the active layer, the grid electrode layer is arranged on the grid electrode insulating layer and is positioned on the semiconductor part, the interlayer dielectric layer covers the grid electrode insulating layer and the grid electrode layer, the interlayer dielectric layer comprises a first through hole, the first through hole penetrates through the grid electrode insulating layer and the interlayer dielectric layer to expose the first doping part, and the photosensitive layer is arranged on the first through hole and. By arranging the photosensitive layer on the first doping part of the active layer, the production cost is reduced, and the yield of the array substrate is improved.

Description

Array substrate and preparation method thereof
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a preparation method thereof.
Background
Fingerprint identification technology has been widely applied to small and medium-sized panels, and mainly includes capacitive type, ultrasonic type, and optical type. Compared with the capacitive and ultrasonic fingerprint identification technologies, the optical fingerprint identification technology has the advantages of good stability, strong antistatic capability, good penetrating power and the like. At present, the photosensitive sensor is usually integrated inside a screen to realize full-screen fingerprint identification, so that user experience can be greatly improved, but the integrated array substrate process becomes complicated, so that the preparation cost is increased, and the product yield is reduced.
Disclosure of Invention
The application provides an array substrate and a preparation method thereof, which are used for reducing the preparation cost of the array substrate and improving the yield of the array substrate.
The application provides an array substrate, includes:
a substrate;
an active layer disposed on the substrate, the active layer including a semiconductor portion and a first doping portion disposed at both sides of the semiconductor portion;
a gate insulating layer covering the substrate and the active layer;
a gate layer disposed on the gate insulating layer, the gate layer being over the semiconductor portion;
an interlayer dielectric layer covering the gate insulating layer and the gate layer, the interlayer dielectric layer including a first via hole penetrating the gate insulating layer and the interlayer dielectric layer to expose the first doped portion; and
and the photosensitive layer is arranged on the first through hole and the interlayer dielectric layer.
In the array substrate provided by the present application, the array substrate further includes a doping layer disposed on the photosensitive layer.
In the array substrate provided by the present application, the array substrate further includes a protection layer, and the protection layer is disposed on the photosensitive layer and the doping layer.
In the array substrate provided by the application, the array substrate further comprises a flat layer, the flat layer covers the interlayer dielectric layer, the photosensitive layer, the doping layer and the protection layer, the flat layer comprises a second through hole, and the second through hole penetrates through the flat layer to expose the protection layer.
In the array substrate provided by the present application, the array substrate further includes a pixel electrode layer, and the pixel electrode layer is disposed on the second via hole and the planarization layer.
In the array substrate provided by the present application, the array substrate further includes a first metal layer disposed between the planarization layer and the pixel electrode layer.
In the array substrate provided by the present application, the array substrate further includes a first passivation layer disposed on the planarization layer and the first metal layer, the first passivation layer includes a third through hole and a fourth through hole, the third through hole penetrates through the first passivation layer to expose the first metal layer, the fourth through hole penetrates through the first passivation layer to expose the doping layer, and the pixel electrode layer is disposed on the fourth through hole and the first passivation layer.
In the array substrate that this application provided, the array substrate still includes the light shield layer, the light shield layer set up in on the base plate, the active layer is located on the light shield layer.
In the array substrate provided by the present application, the active layer further includes a second doped portion disposed on two sides of the semiconductor portion, and the first doped portion is disposed on two sides of the second doped portion.
The application also provides a preparation method of the array substrate, which comprises the following steps:
providing a substrate;
an active layer is arranged on the substrate and comprises a semiconductor part and first doping parts, wherein the first doping parts are arranged on two sides of the semiconductor part;
providing a gate insulating layer on the substrate and the active layer;
providing a gate electrode layer on the gate insulating layer, the gate electrode layer being located over the semiconductor portion;
arranging an interlayer dielectric layer on the grid electrode insulating layer and the grid electrode layer;
etching the gate insulating layer and the interlayer dielectric layer to form a first through hole, wherein the first through hole penetrates through the gate insulating layer and the interlayer dielectric layer to expose the first doping part; and
and arranging photosensitive layers in the first through hole and on the interlayer dielectric layer.
The application provides an array substrate and a preparation method thereof, the array substrate comprises a substrate, an active layer, a grid electrode insulating layer, a grid electrode layer, an interlayer dielectric layer and a photosensitive layer, the active layer is arranged on the substrate and comprises a semiconductor part and a first doping part, the first doping part is arranged on two sides of the semiconductor part, the grid electrode insulating layer covers the substrate and the active layer, the grid electrode layer is arranged on the grid electrode insulating layer and is positioned on the semiconductor part, the interlayer dielectric layer covers the grid electrode insulating layer and the grid electrode layer, the interlayer dielectric layer comprises a first through hole, the first through hole penetrates through the grid electrode insulating layer and the interlayer dielectric layer to expose the first doping part, and the photosensitive layer is arranged on the first through hole and. By arranging the photosensitive layer on the first doping part of the active layer, the production cost is reduced, and the yield of the array substrate is improved.
Drawings
In order to more clearly illustrate the technical solutions in the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a structural cross-sectional view of an array substrate provided in the present application.
FIG. 2 is a flowchart of a method for manufacturing an array substrate according to the present application
Fig. 3 to 19 are cross-sectional views of flow structures of a method for manufacturing an array substrate provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a cross-sectional view of an array substrate provided in the present application. The present application provides an array substrate 10. The array substrate 10 includes a substrate 100, an active layer 200, a gate insulating layer 300, a gate layer 400, an interlayer dielectric layer 500, and a photosensitive layer 600.
In an embodiment, the array substrate 100 further includes a light-shielding layer 700. The light-shielding layer 700 is disposed on the substrate 100. The light-shielding layer 700 is used to prevent external light from being incident into the array substrate, so as to prevent threshold voltage drift.
In one embodiment, the array substrate 10 further includes a buffer layer 800. The buffer layer 800 is disposed on the substrate 100 and the light-shielding layer 600.
The active layer 200 is disposed on the substrate 100. The active layer 200 includes a semiconductor portion 210 and a first doping portion 220. The first doping part 220 is disposed at two sides of the semiconductor part 210. Specifically, the active layer 200 is disposed on the buffer layer 800 and on the light-shielding layer 700. The material of the active layer 200 is polysilicon. The active layer 200 includes a semiconductor portion 210, a first doping portion 220, and a second doping portion 230. The second doping part 230 is disposed at both sides of the semiconductor part 210. The first doping part 220 is located at both sides of the second doping part 230 away from the semiconductor part 210. The first doping portion 220 and the second doping portion 230 are both doped N-type. The doping concentration of the first doping portion 220 is greater than that of the second doping portion 230. The second doping part 230 is doped with N-type with high concentration, so that the thin film transistor can be easily in ohmic contact.
The gate insulating layer 300 covers the substrate 100 and the active layer 200. Specifically, the gate insulating layer 300 covers the buffer layer 800 and the active layer 200.
The gate layer 400 is disposed on the gate insulating layer 300. The gate layer 400 is located above the semiconductor portion 210.
The interlayer dielectric layer 500 covers the gate insulating layer 300 and the gate layer 400. The material of the interlayer dielectric layer 500 includes one or a combination of SiNx and SiOx. The interlayer dielectric layer 500 may be formed by stacking a plurality of layers. The interlayer dielectric layer 500 includes a first via 501, a first via 502, and a second via 503. The first via 501 penetrates the gate insulating layer 300 and the interlayer dielectric layer 500 to expose one side of the first doping part 220. The first via hole 502 penetrates the gate insulating layer 300 and the interlayer dielectric layer 500 to expose the first doping part 220 on the same side as the first via hole 501. The second via 503 penetrates the gate insulating layer 300 and the interlayer dielectric layer 500 to expose the other side of the first doping part 220.
In an embodiment, the array substrate 10 further includes a second metal layer 900. The second metal layer 900 includes a source 910, a drain 920, and a trace 930. The source 910 is disposed in the first via hole 502 and on the interlayer dielectric layer 500, and is electrically connected to one side of the first doping part 220. The drain 920 is disposed in the second via 503 and on the interlayer dielectric layer 500, and is electrically connected to the other side of the first doped portion 220. The active layer 200, the gate insulating layer 300, the gate layer 400, the interlayer dielectric layer 500, the source electrode 910, and the drain electrode 920 form a thin film transistor 999.
The photosensitive layer 600 is disposed on the first via 501 and the interlayer dielectric layer 500, and is electrically connected to the first doping part 220. The photosensitive layer 600 is made of amorphous silicon.
In one embodiment, the array substrate 10 further includes a doped layer 1000. The doped layer 1000 is disposed on the photosensitive layer 600. The doped layer 1000 is doped P-type. The first doped portion 220, the photosensitive layer 600, and the doped layer 1000 form a photosensitive sensor 1099.
In an embodiment, the array substrate 10 further includes a protection layer 1100. The protection layer 1100 is disposed on the photosensitive layer 600 and the doped layer 1000. The material of the protection layer 1100 is indium tin oxide. The protection layer 1100 is used to prevent the doped layer 1000 from being damaged when the array substrate 10 is opened subsequently, and to increase the overlapping contact area with the subsequent pixel electrode layer.
In one embodiment, the array substrate 10 further includes a planarization layer 1200. The planarization layer 1200 covers the interlayer dielectric layer 500, the photosensitive layer 600, the doping layer 1000, and the protection layer 1100. The planarization layer 1200 includes a second via 1201, a third via 1202, and a fourth via 1203. The second through hole 1201 penetrates the planarization layer 1200 to expose the protection layer 1100. The third via 1202 penetrates the planarization layer 1200 to expose the source 910. The fourth via 1203 penetrates the planarization layer 1200 to expose the wire trace portion 930.
In an embodiment, the array substrate 10 further includes a first metal layer 1300. The first metal layer 1300 is disposed on the planarization layer 1200 and located between the third via 1202 and the fourth via 1203.
In one embodiment, the array substrate 10 further includes a second passivation layer 1400. The second passivation layer 1400 covers the protection layer 1100, the planarization layer 1200, and the first metal layer 1300. The second passivation layer 1400 includes a fifth via 1401. The fifth via 1401 penetrates the second passivation layer 1400 and penetrates the third via 1202 to expose the source electrode 910.
In an embodiment, the array substrate 10 further includes a third metal layer 1500. The third metal layer 1500 is disposed in the fifth via 1401 and the third via 1202, and is electrically connected to the source 910.
In an embodiment, the array substrate 10 further includes a third passivation layer 1600. The third passivation layer 1600 covers the second passivation layer 1400. The third passivation layer 1600 includes a sixth via 1601. The sixth via hole penetrates the third passivation layer 1600 to expose the second passivation layer 1400.
In one embodiment, the array substrate 10 further includes an ito layer 1700. The indium tin oxide layer 1700 is disposed in the sixth via 1601 and on the third passivation layer 1600.
In an embodiment, the array substrate 10 further includes a first passivation layer 1800. The first passivation layer 1800 is disposed on the planarization layer 1200 and the first metal layer 1300. The first passivation layer 1800 includes a third via 1801, a fourth via 1802, and a seventh via 1803. The third via 1801 penetrates the first passivation layer 1800 to expose the first metal layer 1300. The fourth through hole 1802 penetrates the first passivation layer 1800 and penetrates the second through hole 1201 to expose the protection layer 1100. The seventh via 1803 penetrates through the planarization layer 1200, the second passivation layer 1400, the third passivation layer 1600, and the first passivation layer 1800, and penetrates through the fourth via 1203 to expose the wire trace portion 930.
In an embodiment, the array substrate 10 further includes a pixel electrode layer 1900. The pixel electrode layer 1900 is disposed on the second via hole 1202 and the planarization layer 1200. Specifically, the pixel electrode layer 1900 is disposed on the first passivation layer 1800, connected to the protective layer through the second via 1202 and the second via 1201, electrically connected to the first metal layer 1300 through the third via 1801, and electrically connected to the wire trace 930 through the seventh via 1803 and the fourth via 1203. The pixel electrode layer 1900 is made of indium tin oxide.
According to the array substrate, the active layer of the thin film transistor 999 and the doped layer of the photosensitive sensor 1099 are prepared from the same layer of polycrystalline silicon, so that the thin film transistor and the photosensitive sensor are arranged in a horizontal mode, and the preparation cost is reduced when the fingerprint identification function of the thin film transistor and the photosensitive sensor is integrated in the array substrate; a photosensitive layer is arranged on the active layer, the active layer is prepared from polycrystalline silicon, and the photosensitive layer is prepared from amorphous silicon, so that the photoproduction current of the photosensitive sensor is improved; after the doping layer is completed, the protective layer is arranged on the doping layer, the doping layer is prevented from being damaged when subsequent holes are opened, meanwhile, the overlap joint contact area of the doping layer and the pixel electrode layer is increased, the risk of overlap joint fracture of the doping layer is reduced, and the yield of the array substrate is improved.
Referring to fig. 2 and fig. 3 to 19, fig. 2 is a flowchart illustrating a method for fabricating an array substrate according to the present application, and fig. 3 to 19 are cross-sectional views illustrating a flow structure of the method for fabricating an array substrate according to the present application. The application also provides a preparation method of the array substrate. The method comprises the following steps:
21. a substrate 100 is provided.
Please refer to fig. 3 and 4. After the step of providing an array substrate 100, the method further includes:
a light-shielding layer 700 material is provided on the substrate 100, and the light-shielding layer 700 is formed by etching and exposure. The material of the light shielding layer 700 includes Mo, Cu, Al, Fe, and the like. The shading layer is used for preventing external light from being emitted into the array substrate, so that threshold voltage drift is avoided.
After the step of disposing the light shielding layer 700 on the substrate 100, the method further includes:
a buffer layer 800 is formed on the substrate 100 and the light-shielding layer 700.
22. An active layer 200 is disposed on the substrate 100, the active layer 200 includes a semiconductor portion 210 and a first doping portion 220, and the first doping portion 220 is disposed on both sides of the semiconductor portion 210.
Please refer to fig. 4 and 5. Specifically, the active layer 200 material is deposited on the buffer layer 800, and exposed and etched to form the active layer 220. The active layer 200 is positioned on the light-shielding layer 700. The active layer 200 is doped with phosphorus ions, arsenic ions, antimony ions, or the like to form a semiconductor portion 210 and a first doped portion 220. The first doping part 220 is disposed at two sides of the semiconductor part 210.
23. A gate insulating layer 300 is disposed on the substrate 100 and the active layer 200.
Please refer to fig. 6. Specifically, a gate insulating layer 300 material is disposed on the buffer layer 800 and the active layer 200 to form the gate insulating layer 300.
24. A gate layer 400 is disposed on the gate insulating layer 300, and the gate layer 400 is located above the semiconductor portion 210.
Please refer to fig. 6. Specifically, a gate layer 400 material is provided on the gate insulating layer 300, and the gate layer 400 is formed by exposure etching.
After the step of forming the gate electrode layer 400 on the gate insulating layer 300, the method further includes:
the semiconductor portion 210 of the active layer 200 is doped using the gate layer 400 as a mask, thereby forming a second doped portion 230. The second doping part 230 is disposed at both sides of the semiconductor part 210. The first doping part 220 is located at both sides of the second doping part 230 away from the semiconductor part 210. The first doping portion 220 and the second doping portion 230 are both doped N-type. The doping concentration of the first doping portion 220 is greater than that of the second doping portion 230. The second doping part 230 is doped with N-type with high concentration, so that the thin film transistor can be easily in ohmic contact.
25. An interlayer dielectric layer 500 is disposed on the gate insulating layer 300 and the gate layer 400.
Please refer to fig. 7. Specifically, an interlayer dielectric layer 500 material is disposed on the gate insulating layer 300 and the gate layer 400, and the interlayer dielectric layer 500 is formed by exposure and etching. The interlevel dielectric layer 500 includes a first via 502 and a second via 503. The first via hole 502 penetrates the gate insulating layer 300 and the interlayer dielectric layer 500 to expose the first doping part 220 on the same side as the first via hole 501. The second via 503 penetrates the gate insulating layer 300 and the interlayer dielectric layer 500 to expose the other side of the first doping part 220. The material of the interlayer dielectric layer 500 includes one or a combination of SiNx and SiOx. The interlayer dielectric layer 500 may be formed by stacking a plurality of layers.
After the step of disposing the interlayer dielectric layer 500 on the gate insulating layer 300 and the gate layer 400, the method further includes:
and depositing a second metal layer 900 material on the interlayer dielectric layer 500, the first via hole 502 and the second via hole 503, and forming a source 910, a drain 920 and a wire routing portion 930 by an exposure etching method. The source 910 is disposed in the first via hole 502 and on the interlayer dielectric layer 500, and is electrically connected to one side of the first doping part 220. The drain 920 is disposed in the second via 503 and on the interlayer dielectric layer 500, and is electrically connected to the other side of the first doped portion 220. The active layer 200, the gate insulating layer 300, the gate layer 400, the interlayer dielectric layer 500, the source electrode 910, and the drain electrode 920 form a thin film transistor 999.
26. A first through hole 501 is formed by etching the gate insulating layer 300 and the interlayer dielectric layer 500, and the first through hole 501 penetrates through the gate insulating layer 300 and the interlayer dielectric layer 500 to expose the first doping part 220.
Please refer to fig. 8. Specifically, the gate insulating layer 300 and the interlayer dielectric layer 500 are exposed and etched to form a first through hole 501, and the first through hole 501 penetrates through the gate insulating layer 300 and the interlayer dielectric layer 500 to expose the first doping portion 220.
27. A photosensitive layer 600 is disposed in the first through hole 501 and on the interlayer dielectric layer 500.
Please refer to fig. 9-19. Specifically, a photosensitive layer 600 material is disposed in the interlayer dielectric layer 500 and the first through hole 501, and the photosensitive layer 600 is formed by an exposure etching method. The photosensitive layer 600 is made of amorphous silicon.
After the step of forming the photosensitive layer 600 in the interlayer dielectric layer 500 and the first via 501, the method further includes:
a protective layer 1100 material is provided on the photosensitive layer 600, and the protective layer 1100 is formed by an exposure etching method. The material of the protection layer 1100 is indium tin oxide. The protection layer 1100 is used to prevent the doped layer 1000 from being damaged when the array substrate 10 is opened subsequently, and to increase the overlapping contact area with the subsequent pixel electrode layer.
After the step of providing the protective layer 1100 on the photosensitive layer 600, the method further includes:
a planarization layer 1200 material is disposed on the interlayer dielectric layer 500, the second metal layer 900, the photosensitive layer 500, and the doping layer 600, and the planarization layer 1200 is formed by an exposure etching method. The planarization layer 1200 includes a second via 1201, a third via 1202, and a fourth via 1203. The second through hole 1201 penetrates the planarization layer 1200 to expose the protection layer 1100. The third via 1202 penetrates the planarization layer 1200 to expose the source 910. The fourth via 1203 penetrates the planarization layer 1200 to expose the wire trace portion 930.
After the step of forming the planarization layer 1200 on the interlayer dielectric layer 500, the second metal layer 900, the photosensitive layer 500, and the doped layer 600, the method further includes:
a first metal layer 1300 material is disposed on the planarization layer 1200, and the first metal layer 1300 is formed by an exposure etching method. The first metal layer 1300 is located between the third via 1202 and the fourth via 1203.
After the step of forming the first metal layer 1300 on the planarization layer 1200, the method further includes:
a second passivation layer 1400 material is disposed on the protection layer 1100, on the planarization layer 1200, in the third via 1202, in the fourth via 1203 and on the first metal layer 1300, and a second passivation layer 1400 is formed by an exposure etching method. The second passivation layer 1400 includes a fifth via 1401. The fifth via 1401 penetrates the second passivation layer 1400 and penetrates the third via 1202 to expose the source electrode 910.
After the step of forming the second passivation layer 1400 on the protection layer 1100, in the planarization layer 1200, the third via 1202, and the fourth via 1203, the method further includes:
a third metal layer 1500 material is disposed in the fifth via 1401 and on the second passivation layer 1400, and the third metal layer 1500 is formed by an exposure etching method.
After the step of forming the third metal layer 1500 in the fifth via 1401 and on the second passivation layer 1400, the method further includes:
a third passivation layer 1600 material is disposed on the second passivation layer 1400 and the third metal layer 1500, and the third passivation layer 1600 is formed by an exposure etching method. The third passivation layer 1600 includes a sixth via 1601. The sixth via hole penetrates the third passivation layer 1600 to expose the second passivation layer 1400.
After the step of forming the third passivation layer 1600 on the second passivation layer 1400 and the third metal layer 1500, the method further includes:
and arranging an indium tin oxide layer 1700 material on the third passivation layer 1600 and the sixth via 1601, and forming the indium tin oxide layer 1700 by an exposure etching method.
After the step of forming the ito layer 1700 on the third passivation layer 1600 and the sixth via 1601, the method further includes:
a first passivation layer 1800 material is disposed on the planarization layer 1200 and the first metal layer 1300, and the first passivation layer 1800 is formed by an exposure etching method. The first passivation layer 1800 includes a third via 1801, a fourth via 1802, and a seventh via 1803. The third via 1801 penetrates the first passivation layer 1800 to expose the first metal layer 1300. The fourth through hole 1802 penetrates the first passivation layer 1800 and penetrates the second through hole 1201 to expose the protection layer 1100. The seventh via 1803 penetrates through the planarization layer 1200, the second passivation layer 1400, the third passivation layer 1600, and the first passivation layer 1800, and penetrates through the fourth via 1203 to expose the wire trace portion 930.
After the step of forming the first passivation layer 1800 on the planarization layer 1200 and the first metal layer 1300, the method further includes:
a pixel electrode layer 1900 is formed by providing a material for the pixel electrode layer 1900 on the second via hole 1202 and the planarization layer 1200 and exposing and etching the material. The pixel electrode layer 1900 is connected to the protective layer through the second via 1202 and the second via 1201, electrically connected to the first metal layer 1300 through the third via 1801, and electrically connected to the wire trace 930 through the seventh via 1803 and the fourth via 1203. The pixel electrode layer 1900 is made of indium tin oxide.
In this application, through the polycrystalline silicon preparation with the active layer of thin film transistor and photosensitive sensor's doping portion adoption one deck, only need increase twice mask process promptly, and need not additionally to let in phosphane and borane gas, just can be integrated to array substrate with thin film transistor and the photosensitive sensor that has the fingerprint identification function, reduced manufacturing cost.
The application provides an array substrate and a preparation method thereof, the array substrate comprises a substrate, an active layer, a grid electrode insulating layer, a grid electrode layer, an interlayer dielectric layer and a photosensitive layer, the active layer is arranged on the substrate and comprises a semiconductor part and a first doping part, the first doping part is arranged on two sides of the semiconductor part, the grid electrode insulating layer covers the substrate and the active layer, the grid electrode layer is arranged on the grid electrode insulating layer and is positioned on the semiconductor part, the interlayer dielectric layer covers the grid electrode insulating layer and the grid electrode layer, the interlayer dielectric layer comprises a first through hole, the first through hole penetrates through the grid electrode insulating layer and the interlayer dielectric layer to expose the first doping part, and the photosensitive layer is arranged on the first through hole and. By arranging the photosensitive layer on the first doping part of the active layer, the production cost is reduced, and the yield of the array substrate is improved.
The foregoing provides a detailed description of embodiments of the present application, and the principles and embodiments of the present application have been described herein using specific examples, which are presented solely to aid in the understanding of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. An array substrate, comprising:
a substrate;
an active layer disposed on the substrate, the active layer including a semiconductor portion and a first doping portion disposed at both sides of the semiconductor portion;
a gate insulating layer covering the substrate and the active layer;
a gate layer disposed on the gate insulating layer, the gate layer being over the semiconductor portion;
an interlayer dielectric layer covering the gate insulating layer and the gate layer, the interlayer dielectric layer including a first via hole penetrating the gate insulating layer and the interlayer dielectric layer to expose the first doped portion; and
and the photosensitive layer is arranged on the first through hole and the interlayer dielectric layer.
2. The array substrate of claim 1, wherein the array substrate further comprises a doped layer disposed on the photosensitive layer.
3. The array substrate of claim 2, further comprising a protective layer disposed on the photosensitive layer and the doped layer.
4. The array substrate of claim 3, further comprising a planarization layer covering the interlevel dielectric layer, the photosensitive layer, the doped layer, and the protection layer, the planarization layer including a second via hole penetrating the planarization layer to expose the protection layer.
5. The array substrate of claim 4, further comprising a pixel electrode layer disposed on the second via and the planarization layer.
6. The array substrate of claim 5, further comprising a first metal layer disposed between the planarization layer and the pixel electrode layer.
7. The array substrate of claim 6, further comprising a first passivation layer disposed on the planarization layer and the first metal layer, wherein the first passivation layer comprises a third via and a fourth via, the third via penetrates the first passivation layer to expose the first metal layer, the fourth via penetrates the first passivation layer to expose the doping layer, and the pixel electrode layer is disposed on the fourth via and the first passivation layer.
8. The array substrate of claim 1, further comprising a light-shielding layer disposed on the substrate, wherein the active layer is disposed on the light-shielding layer.
9. The array substrate of claim 1, wherein the active layer further comprises a second doped portion disposed on both sides of the semiconductor portion, and the first doped portion is disposed on both sides of the second doped portion.
10. A preparation method of an array substrate is characterized by comprising the following steps:
providing a substrate;
an active layer is arranged on the substrate and comprises a semiconductor part and first doping parts, wherein the first doping parts are arranged on two sides of the semiconductor part;
providing a gate insulating layer on the substrate and the active layer;
providing a gate electrode layer on the gate insulating layer, the gate electrode layer being located over the semiconductor portion;
arranging an interlayer dielectric layer on the grid electrode insulating layer and the grid electrode layer;
etching the gate insulating layer and the interlayer dielectric layer to form a first through hole, wherein the first through hole penetrates through the gate insulating layer and the interlayer dielectric layer to expose the first doping part; and
and arranging photosensitive layers in the first through hole and on the interlayer dielectric layer.
CN202011097651.9A 2020-10-14 2020-10-14 Array substrate and preparation method thereof Active CN112242407B (en)

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