CN114188389A - TFT array substrate, manufacturing method thereof and OLED display panel - Google Patents
TFT array substrate, manufacturing method thereof and OLED display panel Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
- H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
Abstract
The application provides a TFT array substrate, a manufacturing method thereof and an OLED display panel. The TFT array substrate comprises a substrate, a first electrode layer, a first insulating layer, a second electrode layer, a second insulating layer and a third electrode layer. The first electrode layer includes a first electrode trace disposed on the substrate. The first insulating layer is provided with a first via hole exposing the first electrode routing. The second electrode layer comprises a first lapping electrode arranged in the first via hole and a first protection electrode arranged on the first lapping electrode. The second insulating layer has a second via hole therein exposing the first protective electrode. The third electrode layer includes a second electrode trace disposed in the second via. The lapping distance of second electrode line and first electrode line can be reduced to this application to, first overlap joint electrode can be avoided by the sculpture to first guard electrode, and it is even still to make the sculpture of second via hole, and it is unusual to walk the line and walk the line overlap joint with first electrode to avoid the second electrode.
Description
Technical Field
The application relates to the technical field of display devices, in particular to a TFT array substrate, a manufacturing method of the TFT array substrate and an OLED display panel.
Background
The electroluminescent diode (OLED) has the advantages of simple manufacturing process, low cost, high light emitting efficiency, easy formation of flexible structure, low power consumption, high color saturation, wide viewing angle, and the like, and the display technology using the electroluminescent diode has become an important display technology.
OLEDs are current-mode light emitting devices that mainly include an anode, a cathode, and an organic material functional layer. The main working principle of the OLED is: the organic material functional layer emits light by carrier injection and recombination under the drive of an electric field formed by the anode and the cathode.
In order to be applied to the driving display of the high-resolution OLED display panel and reduce the charge and discharge delay time, the electrodes (i.e., the traces) in the TFT (thin film transistor) array substrate in the prior art need to be made of a thicker metal material to reduce the resistance of the electrodes. However, the electrodes become thick, the insulating layers between the multiple layers of electrodes also become thick correspondingly, the via holes overlapped by the multiple layers of electrodes also become deep, overlapping abnormality between the multiple layers of electrodes is easily caused, and uneven etching easily occurs in the process of etching the via holes by the thick insulating layers, so that the display effect is influenced.
Disclosure of Invention
The application provides a TFT array substrate, a manufacturing method thereof and an OLED display panel, and aims to solve the problems that in the prior art, due to the fact that via holes overlapped by multiple layers of electrodes in the TFT array substrate become deep, etching of the via holes is uneven, and overlapping among the multiple layers of electrodes is abnormal.
In one aspect, the present application provides a TFT array substrate, including:
a substrate;
a first electrode layer comprising a first electrode trace disposed on the substrate;
the first insulating layer is arranged on the substrate and the first electrode layer, and a first through hole exposing the first electrode routing is formed in the first insulating layer;
the second electrode layer comprises a first lapping electrode arranged in the first via hole and connected with the first electrode routing, and a first protective electrode arranged on the first lapping electrode;
the second insulating layer is arranged on the second electrode layer and the first insulating layer, and a second through hole exposing the first protection electrode is formed in the second insulating layer;
and the third electrode layer comprises a second electrode wire which is arranged in the second via hole and connected with the first protection electrode.
In some possible implementations, the first electrode layer further includes a light-shielding layer disposed on the substrate;
the first insulating layer is also provided with a third through hole exposing the shading layer;
the second electrode layer further comprises a second lapping electrode arranged in the third via hole and connected with the shading layer, and a second protective electrode arranged on the second lapping electrode;
the second insulating layer is provided with a fourth through hole exposing the second protective electrode;
the third electrode layer further comprises a source electrode which is arranged in the fourth through hole and connected with the second protective electrode.
In some possible implementations, the second electrode layer further includes an active layer disposed on the first insulating layer, and a third protective electrode disposed on the active layer;
the second insulating layer is also provided with a fifth through hole exposing the third protective electrode;
the third electrode layer further comprises a source electrode which is arranged in the fifth via hole and connected with the third protective electrode.
In some possible implementations, the second electrode layer further includes a fourth guard electrode disposed on the active layer, and the fourth guard electrode is spaced apart from the third guard electrode;
the second insulating layer is also provided with a sixth through hole exposing the fourth protective electrode;
the third electrode layer further comprises a drain electrode which is arranged in the sixth through hole and connected with the fourth protective electrode.
In some possible implementations, the TFT array substrate further includes a third insulating layer disposed between the active layer and the second insulating layer, and a gate electrode disposed between the third insulating layer and the second insulating layer.
On the other hand, the application also provides an OLED display panel which comprises the TFT array substrate.
In another aspect, the present application also provides a method for manufacturing a TFT array substrate, including:
providing a substrate, and manufacturing a first electrode layer on the substrate, wherein the first electrode layer comprises a first electrode wire arranged on the substrate;
manufacturing a first insulating layer on the substrate and the first electrode layer, and etching the first insulating layer to form a first via hole exposing the first electrode routing;
manufacturing a second electrode layer on the first insulating layer, wherein the second electrode layer comprises a first lap electrode arranged in the first via hole and connected with the first electrode routing, and a first protective electrode arranged on the first lap electrode;
manufacturing a second insulating layer on the second electrode layer and the first insulating layer, and etching the second insulating layer to form a second through hole exposing the first protection electrode;
and manufacturing a third electrode layer on the second insulating layer, wherein the third electrode layer comprises a second electrode wire which is arranged in the second via hole and connected with the first protective electrode.
In some possible implementations, the first electrode layer further includes a light-shielding layer disposed on the substrate;
the first insulating layer is also provided with a third through hole exposing the shading layer;
the second electrode layer further comprises a second lapping electrode arranged in the third via hole and connected with the shading layer, and a second protective electrode arranged on the second lapping electrode;
the second insulating layer is provided with a fourth through hole exposing the second protective electrode;
the third electrode layer further comprises a source electrode which is arranged in the fourth through hole and connected with the second protective electrode.
In some possible implementations, the second electrode layer further includes an active layer disposed on the first insulating layer, and a third protective electrode disposed on the active layer;
the second insulating layer is also provided with a fifth through hole exposing the third protective electrode;
the third electrode layer further comprises a source electrode which is arranged in the fifth via hole and connected with the third protective electrode.
In some possible implementations, the second electrode layer further includes a fourth guard electrode disposed on the active layer, and the fourth guard electrode is spaced apart from the third guard electrode;
the second insulating layer is also provided with a sixth through hole exposing the fourth protective electrode;
the third electrode layer further comprises a drain electrode which is arranged in the sixth through hole and connected with the fourth protective electrode.
The TFT array substrate comprises a substrate, a first electrode layer, a first insulating layer, a second electrode layer, a second insulating layer and a third electrode layer. The first electrode layer includes a first electrode trace disposed on the substrate. The first insulating layer is arranged on the substrate and the first electrode layer, and a first through hole exposing the first electrode routing is formed in the first insulating layer. The second electrode layer comprises a first lap electrode arranged in the first via hole and connected with the first electrode routing, and a first protection electrode arranged on the first lap electrode. The second insulating layer is arranged on the second electrode layer and the first insulating layer, and a second through hole exposing the first protective electrode is formed in the second insulating layer. The third electrode layer comprises a second electrode wire which is arranged in the second via hole and connected with the first protection electrode. This application is walked line through first electrode and is connected first guard electrode and first overlap joint electrode promptly, and rethread second electrode is walked line and is connected first guard electrode, realizes that the second electrode is walked the line and is walked the overlap joint of line with first electrode, compares in prior art and directly walks the line with first electrode with the second electrode and walk the overlap joint, can reduce the second electrode and walk the overlap joint distance of line with first electrode. And, first guard electrode can be corrosion resistant material, and at the in-process of second via hole of second insulating layer formation, first guard electrode not only can prevent the over-etching, avoids first overlap joint electrode to be corroded, can also make the second via hole sculpture evenly, guarantees that the second via hole can expose first guard electrode to guarantee the overlap joint of second electrode line and first guard electrode, in order to avoid the second electrode to walk the line and first electrode to walk the line overlap joint unusual.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic view of a TFT array substrate according to an embodiment of the present disclosure;
fig. 2 is a flowchart of a method for manufacturing a TFT array substrate according to an embodiment of the present disclosure;
fig. 3 is a schematic view illustrating a method for manufacturing a TFT array substrate according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or reference letters in the various examples, which have been repeated for purposes of brevity and clarity and do not in themselves dictate a relationship between the various embodiments and/or arrangements discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Referring to fig. 1 to 3, an embodiment of the present invention provides a TFT array substrate, including:
a substrate 1;
a first electrode layer 2, the first electrode layer 2 comprising a first electrode trace 21 provided on the substrate 1;
a first insulating layer 3, the first insulating layer 3 being disposed on the substrate 1 and the first electrode layer 2, the first insulating layer 3 having a first via hole 31 therein to expose the first electrode trace 21;
a second electrode layer 4, wherein the second electrode layer 4 includes a first overlapping electrode 41 disposed in the first via hole 31 and connected to the first electrode trace 21, and a first protective electrode 42 disposed on the first overlapping electrode 41;
a second insulating layer 5, wherein the second insulating layer 5 is disposed on the second electrode layer 4 and the first insulating layer 3, and the second insulating layer 5 has a second via hole 51 therein for exposing the first protective electrode 42;
and a third electrode layer 6, wherein the third electrode layer 6 includes a second electrode trace 61 disposed in the second via hole 51 and connected to the first protective electrode 42.
It should be noted that, in the present application, the first protective electrode 42 and the first overlapping electrode 41 are connected by the first electrode trace 21, and then the second electrode trace 61 is connected to the first protective electrode 42, so as to realize the overlapping of the second electrode trace 61 and the first electrode trace 21, compared with the prior art in which the second electrode trace 61 is directly overlapped with the first electrode trace 21, the overlapping distance between the second electrode trace 61 and the first electrode trace 21 can be reduced. That is, in the prior art, the second electrode trace 61 directly passes through the first via 31 and the second via 51 to overlap the first electrode trace 21, and the overlapping distance between the second electrode trace 61 and the first electrode trace 21 is the sum of the depths of the first via 31 and the second via 51. In the present application, the first overlapping electrode 41 passes through the first via 31 to overlap the first electrode trace 21, and the subsequent second electrode trace 61 passes through the second via 51 to overlap the first overlapping electrode 41, which is equivalent to the overlapping distance between the second electrode trace 61 and the first electrode trace 21 being the depth of the second via 51, so as to reduce the overlapping distance between the second electrode trace 61 and the first electrode trace 21, thereby avoiding the overlapping abnormality between the second electrode trace 61 and the first electrode trace 21.
And, first protective electrode 42 can be corrosion-resistant material, first overlap electrode 41 can be protected, in the process of second insulating layer 5 forming second via hole 51, first protective electrode 42 not only can prevent the overetching, namely the etching process of second insulating layer 5 can stop in first protective electrode 42 department, avoid first overlap electrode 41 to be corroded, can also make second via hole 51 etch evenly, guarantee that second via hole 51 can expose first protective electrode 42, in order to guarantee the overlap joint of second electrode wiring 61 and first protective electrode 42, in order to further avoid second electrode wiring 61 and first electrode wiring 21 overlap joint unusual.
In addition, the second electrode trace 61, the first protective electrode 42, the first overlapping electrode 41 and the first electrode trace 21 are all connected, so that the resistance of the second electrode trace 61 and the first electrode trace 21 can be further reduced, and the electrical performance of the TFT array substrate is improved.
In some embodiments, the first via 31 and the second via 51 are each less deep than
In some embodiments, referring to fig. 1, the first electrode layer 2 further includes a light shielding layer 22 disposed on the substrate 1. The first insulating layer 3 also has a third via hole 32 therein exposing the light shielding layer 22. The second electrode layer 4 further includes a second bonding electrode 43 disposed in the third via hole 32 and connected to the light-shielding layer 22, and a second protective electrode 44 disposed on the second bonding electrode 43. The second insulating layer 5 has a fourth via hole 52 therein exposing the second guard electrode 44. The third electrode layer 6 further includes a source electrode 62 disposed in the fourth via hole 52 and connected to the second guard electrode 44.
That is, this application passes third via hole 32 overlap joint light shield layer 22 through second overlap joint electrode 43 earlier, follow-up source 62 passes fourth via hole 52 overlap joint second overlap joint electrode 43 again, be equivalent to the overlap joint distance of source 62 and light shield layer 22 is the degree of depth of fourth via hole 52, compare in that source 62 directly passes third via hole 32 and fourth via hole 52 overlap joint light shield layer 22, the overlap joint distance of source 62 and light shield layer 22 is the sum of the degree of depth of third via hole 32 and fourth via hole 52, this application can reduce the overlap joint distance of source 62 and light shield layer 22, thereby avoid source 62 and light shield layer 22 overlap joint unusually. And the second protective electrode 44 may be a corrosion-resistant material, and may protect the second overlapping electrode 43, in the process of forming the fourth via hole 52 in the second insulating layer 5, the second protective electrode 44 may not only prevent over-etching, that is, the etching process of the second insulating layer 5 may stop at the second protective electrode 44, so as to prevent the second overlapping electrode 43 from being etched, but also enable the fourth via hole 52 to be etched uniformly, so as to ensure that the fourth via hole 52 may expose the second protective electrode 44, so as to ensure the overlapping of the source electrode 62 and the second protective electrode 44, so as to further avoid the abnormal overlapping of the source electrode 62 and the light shielding layer 22.
In addition, the light shielding layer 22 is disposed under the active layer 45, so that a floating gate effect is generated, that is, the light shielding layer 22 is equivalent to a bottom gate, and the light shielding layer 22 is easily affected by voltages on other charged structure layers, so as to carry various voltages, so that the light shielding layer 22 has variable voltages, which causes the threshold voltage of the TFT array substrate to change continuously during operation, and the TFT array substrate is unstable in operation. Therefore, the source electrode 62 and the light shielding layer 22 are overlapped to generate stable voltage on the light shielding layer 22, so that the floating gate effect is avoided, and the working stability of the TFT array substrate is effectively improved.
In some embodiments, referring to fig. 1, the second electrode layer 4 further includes an active layer 45 disposed on the first insulating layer 3, and a third protective electrode 46 disposed on the active layer 45. The second insulating layer 5 also has a fifth via hole 53 therein exposing the third guard electrode 46. The third electrode layer 6 further includes a source electrode 62 disposed in the fifth via hole 53 and connected to the third guard electrode 46.
That is, the third protective electrode 46 may be a corrosion-resistant material, and may protect the active layer 45, and in the process of forming the fifth via hole 53 in the second insulating layer 5, the third protective electrode 46 may not only prevent over-etching, that is, the etching process of the second insulating layer 5 may stop at the third protective electrode 46, so as to prevent the active layer 45 from being etched, but also enable the fifth via hole 53 to be etched uniformly, so as to ensure that the fifth via hole 53 can expose the third protective electrode 46, so as to ensure the overlapping of the source electrode 62 and the active layer 45, so as to further prevent the abnormal overlapping of the source electrode 62 and the active layer 45.
In some embodiments, referring to fig. 1, the second electrode layer 4 further includes a fourth guard electrode 47 disposed on the active layer 45, and the fourth guard electrode 47 is spaced apart from the third guard electrode 46. The second insulating layer 5 also has a sixth via hole 54 therein exposing the fourth protective electrode 47. The third electrode layer 6 further includes a drain electrode 63 provided in the sixth via hole 54 and connected to the fourth protective electrode 47.
That is, the fourth protection electrode 47 may be a corrosion-resistant material, and may protect the active layer 45, and in the process of forming the sixth via hole 54 in the second insulating layer 5, the fourth protection electrode 47 may not only prevent over-etching, that is, the etching process of the second insulating layer 5 may stop at the fourth protection electrode 47, so as to prevent the active layer 45 from being etched, but also enable the sixth via hole 54 to be etched uniformly, so as to ensure that the sixth via hole 54 can expose the fourth protection electrode 47, so as to ensure the overlapping of the drain electrode 63 and the active layer 45, so as to further prevent the overlapping abnormality of the drain electrode 63 and the active layer 45.
In this embodiment, the active layer 45 includes a channel region and source and drain contact regions respectively located at both sides of the channel region. The third guard electrode 46 is located directly above the source contact region, and the fourth guard electrode 47 is located directly above the drain contact region.
In this embodiment, referring to fig. 1, the TFT array substrate further includes a third insulating layer 7 disposed between the active layer 45 and the second insulating layer 5, and a gate electrode 8 disposed between the third insulating layer 7 and the second insulating layer 5. That is, the third insulating layer 7 is located between the third and fourth guard electrodes 46 and 47, and the active layer 45, the gate electrode 8, the source electrode 62, and the drain electrode 63 constitute a TFT. The TFT has a top gate structure, and the gate 8 may be located right above the channel region of the active layer 45, so that the gate 8 may block a portion of the doped ions from entering the channel region of the active layer 45 during the process of conducting (i.e., ion doping) the active layer 45, thereby saving the process.
In this embodiment, the light shielding layer 22 is located below the active layer 45, and the orthographic projection of the active layer 45 on the first insulating layer 3 is located in the orthographic projection of the light shielding layer 22 on the first insulating layer 3, so that the light shielding layer 22 completely shields the active layer 45, the active layer 45 is prevented from being irradiated by external ambient light, a drift phenomenon of a threshold voltage of the TFT is avoided, and the illumination stability of the TFT can be significantly improved.
In addition, the area of the light-shielding layer 22 may be larger than that of the active layer 45 to further improve the light-shielding effect.
In this embodiment, the light shielding layer 22 may be a metal or an alloy of silver, molybdenum, aluminum, copper, chromium, tungsten, titanium, tantalum, or the like, which can reflect light.
In some embodiments, the first guard electrode 42, the second guard electrode 44, the third guard electrode 46, and the fourth guard electrode 47 may each be molybdenum titanium (MoTi) or a molybdenum titanium alloy. Of course, the first guard electrode 42, the second guard electrode 44, the third guard electrode 46, and the fourth guard electrode 47 may be made of other corrosion-resistant materials, and the application is not limited herein.
In some embodiments, the active layer 45, the first landing electrode 41, and the second landing electrode 43 may be all Indium Tin Oxide (ITO), Indium Zinc Oxide (IZO), or Indium Gallium Zinc Oxide (IGZO). The first and second landing electrodes 41 and 43 may also be conducted (i.e., ion-doped) in order to improve the electrical properties of the first and second landing electrodes 41 and 43.
In some embodiments, the gate electrode 8, the first electrode trace 21, the second electrode trace 61, the source electrode 62, and the drain electrode 63 may be a combination of one or more of aluminum, aluminum alloy, copper alloy, titanium, and titanium alloy.
In some embodiments, the first electrode trace 21 and the second electrode trace 61 may be scan lines. Of course, the first electrode trace 21 and the second electrode trace 61 may also be configured as other signal traces according to actual requirements, such as a data line, which is not limited herein.
Based on the TFT array substrate, an embodiment of the application further provides an OLED display panel including the TFT array substrate.
It should be noted that the TFT array substrate is connected to the first protective electrode 42 and the first overlapping electrode 41 through the first electrode trace 21, and then connected to the first protective electrode 42 through the second electrode trace 61, so as to realize the overlapping of the second electrode trace 61 and the first electrode trace 21, and reduce the overlapping distance between the second electrode trace 61 and the first electrode trace 21, thereby avoiding the overlapping abnormality between the second electrode trace 61 and the first electrode trace 21. And, first protective electrode 42 can be corrosion-resistant material, first overlap electrode 41 can be protected, in the process of second insulating layer 5 forming second via hole 51, first protective electrode 42 not only can prevent the over-etching, namely, the etching process of second insulating layer 5 can stop in first protective electrode 42, avoid first overlap electrode 41 to be etched, second via hole 51 can also be etched evenly, guarantee that second via hole 51 can expose first protective electrode 42, in order to guarantee the overlap joint of second electrode routing 61 and first protective electrode 42, in order to further avoid second electrode routing 61 and first electrode routing 21 overlap joint unusual, and then improve OLED display panel's display effect.
The application of the OLED display panel is not specifically limited, and the OLED display panel may be any product or component with a display function, such as a television, a notebook computer, a tablet computer, a wearable display device (e.g., a smart band, a smart watch, and the like), a mobile phone, a virtual reality device, an augmented reality device, a vehicle-mounted display, an advertising light box, and the like.
Referring to fig. 2 and fig. 3, based on the TFT array substrate, an embodiment of the present invention further provides a method for manufacturing a TFT array substrate, including:
step S1, providing a substrate 1, and fabricating a first electrode layer 2 on the substrate 1, where the first electrode layer 2 includes a first electrode trace 21 disposed on the substrate 1;
step S2, fabricating a first insulating layer 3 on the substrate 1 and the first electrode layer 2, and etching the first insulating layer 3 to form a first via hole 31 exposing the first electrode trace 21;
step S3, fabricating a second electrode layer 4 on the first insulating layer 3, where the second electrode layer 4 includes a first landing electrode 41 disposed in the first via hole 31 and connected to the first electrode trace 21, and a first protection electrode 42 disposed on the first landing electrode 41;
step S4, fabricating a second insulating layer 5 on the second electrode layer 4 and the first insulating layer 3, and etching the second insulating layer 5 to form a second via hole 51 exposing the first protective electrode 42;
step S5, a third electrode layer 6 is formed on the second insulating layer 5, and the third electrode layer 6 includes a second electrode trace 61 disposed in the second via hole 51 and connected to the first protective electrode 42.
It should be noted that, in the present application, the first protective electrode 42 and the first overlapping electrode 41 are connected by the first electrode trace 21, and then the second electrode trace 61 is connected to the first protective electrode 42, so as to realize the overlapping of the second electrode trace 61 and the first electrode trace 21, compared with the prior art in which the second electrode trace 61 is directly overlapped with the first electrode trace 21, the overlapping distance between the second electrode trace 61 and the first electrode trace 21 can be reduced. That is, in the prior art, the second electrode trace 61 directly passes through the first via 31 and the second via 51 to overlap the first electrode trace 21, and the overlapping distance between the second electrode trace 61 and the first electrode trace 21 is the sum of the depths of the first via 31 and the second via 51. In the present application, the first overlapping electrode 41 passes through the first via 31 to overlap the first electrode trace 21, and the subsequent second electrode trace 61 passes through the second via 51 to overlap the first overlapping electrode 41, which is equivalent to the overlapping distance between the second electrode trace 61 and the first electrode trace 21 being the depth of the second via 51, so as to reduce the overlapping distance between the second electrode trace 61 and the first electrode trace 21, thereby avoiding the overlapping abnormality between the second electrode trace 61 and the first electrode trace 21.
And, first protective electrode 42 can be corrosion-resistant material, first overlap electrode 41 can be protected, in the process of second insulating layer 5 forming second via hole 51, first protective electrode 42 not only can prevent the overetching, namely the etching process of second insulating layer 5 can stop in first protective electrode 42 department, avoid first overlap electrode 41 to be corroded, can also make second via hole 51 etch evenly, guarantee that second via hole 51 can expose first protective electrode 42, in order to guarantee the overlap joint of second electrode wiring 61 and first protective electrode 42, in order to further avoid second electrode wiring 61 and first electrode wiring 21 overlap joint unusual.
In addition, the second electrode trace 61, the first protective electrode 42, the first overlapping electrode 41 and the first electrode trace 21 are all connected, so that the resistance of the second electrode trace 61 and the first electrode trace 21 can be further reduced, and the electrical performance of the TFT array substrate is improved.
In some embodiments, referring to fig. 3, the first electrode layer 2 further includes a light-shielding layer 22 disposed on the substrate 1. The first insulating layer 3 also has a third via hole 32 therein exposing the light shielding layer 22. The second electrode layer 4 further includes a second bonding electrode 43 disposed in the third via hole 32 and connected to the light-shielding layer 22, and a second protective electrode 44 disposed on the second bonding electrode 43. The second insulating layer 5 has a fourth via hole 52 therein exposing the second guard electrode 44. The third electrode layer 6 further includes a source electrode 62 disposed in the fourth via hole 52 and connected to the second guard electrode 44.
That is, this application passes third via hole 32 overlap joint light shield layer 22 through second overlap joint electrode 43 earlier, follow-up source 62 passes fourth via hole 52 overlap joint second overlap joint electrode 43 again, be equivalent to the overlap joint distance of source 62 and light shield layer 22 is the degree of depth of fourth via hole 52, compare in that source 62 directly passes third via hole 32 and fourth via hole 52 overlap joint light shield layer 22, the overlap joint distance of source 62 and light shield layer 22 is the sum of the degree of depth of third via hole 32 and fourth via hole 52, this application can reduce the overlap joint distance of source 62 and light shield layer 22, thereby avoid source 62 and light shield layer 22 overlap joint unusually. And the second protective electrode 44 may be a corrosion-resistant material, and may protect the second overlapping electrode 43, in the process of forming the fourth via hole 52 in the second insulating layer 5, the second protective electrode 44 may not only prevent over-etching, that is, the etching process of the second insulating layer 5 may stop at the second protective electrode 44, so as to prevent the second overlapping electrode 43 from being etched, but also enable the fourth via hole 52 to be etched uniformly, so as to ensure that the fourth via hole 52 may expose the second protective electrode 44, so as to ensure the overlapping of the source electrode 62 and the second protective electrode 44, so as to further avoid the abnormal overlapping of the source electrode 62 and the light shielding layer 22.
In addition, the light shielding layer 22 is disposed under the active layer 45, so that a floating gate effect is generated, that is, the light shielding layer 22 is equivalent to a bottom gate, and the light shielding layer 22 is easily affected by voltages on other charged structure layers, so as to carry various voltages, so that the light shielding layer 22 has variable voltages, which causes the threshold voltage of the TFT array substrate to change continuously during operation, and the TFT array substrate is unstable in operation. Therefore, the source electrode 62 and the light shielding layer 22 are overlapped to generate stable voltage on the light shielding layer 22, so that the floating gate effect is avoided, and the working stability of the TFT array substrate is effectively improved.
In this embodiment, referring to fig. 3, in step S2, the first insulating layer 3 is etched, and the first via 31 exposing the first electrode trace 21 and the third via 32 exposing the light-shielding layer 22 are formed at the same time.
In some embodiments, referring to fig. 3, the second electrode layer 4 further includes an active layer 45 disposed on the first insulating layer 3, and a third protective electrode 46 disposed on the active layer 45. The second insulating layer 5 also has a fifth via hole 53 therein exposing the third guard electrode 46. The third electrode layer 6 further includes a source electrode 62 disposed in the fifth via hole 53 and connected to the third guard electrode 46.
That is, the third protective electrode 46 may be a corrosion-resistant material, and may protect the active layer 45, and in the process of forming the fifth via hole 53 in the second insulating layer 5, the third protective electrode 46 may not only prevent over-etching, that is, the etching process of the second insulating layer 5 may stop at the third protective electrode 46, so as to prevent the active layer 45 from being etched, but also enable the fifth via hole 53 to be etched uniformly, so as to ensure that the fifth via hole 53 can expose the third protective electrode 46, so as to ensure the overlapping of the source electrode 62 and the active layer 45, so as to further prevent the abnormal overlapping of the source electrode 62 and the active layer 45.
In some embodiments, referring to fig. 3, the second electrode layer 4 further includes a fourth guard electrode 47 disposed on the active layer 45, and the fourth guard electrode 47 is spaced apart from the third guard electrode 46. The second insulating layer 5 also has a sixth via hole 54 therein exposing the fourth protective electrode 47. The third electrode layer 6 further includes a drain electrode 63 provided in the sixth via hole 54 and connected to the fourth protective electrode 47.
That is, the fourth protection electrode 47 may be a corrosion-resistant material, and may protect the active layer 45, and in the process of forming the sixth via hole 54 in the second insulating layer 5, the fourth protection electrode 47 may not only prevent over-etching, that is, the etching process of the second insulating layer 5 may stop at the fourth protection electrode 47, so as to prevent the active layer 45 from being etched, but also enable the sixth via hole 54 to be etched uniformly, so as to ensure that the sixth via hole 54 can expose the fourth protection electrode 47, so as to ensure the overlapping of the drain electrode 63 and the active layer 45, so as to further prevent the overlapping abnormality of the drain electrode 63 and the active layer 45.
In this embodiment, referring to fig. 3, in step S4, the second insulating layer 5 is etched, and the second via hole 51 exposing the first protection electrode 42, the fourth via hole 52 exposing the second protection electrode 44, the fifth via hole 53 exposing the third protection electrode 46, and the sixth via hole 54 exposing the fourth protection electrode 47 are formed.
In some embodiments, referring to fig. 3, in step S3, fabricating the second electrode layer 4 on the first insulating layer 3 includes:
depositing a first material layer on the first insulating layer 3 and in the first via hole 31 and the third via hole 32, and patterning and conducing the first material layer to form an active layer 45, a first landing electrode 41, and a second landing electrode 43;
and depositing a second material layer on the first insulating layer 3 and the first material layer, and patterning the second material layer to form a first protective electrode 42, a second protective electrode 44, a third protective electrode 46 and a fourth protective electrode 47, so as to complete the manufacture of the second electrode layer 4.
In this embodiment, the first material layer may be indium tin oxide, indium zinc oxide, or indium gallium zinc oxide. The second material layer may be molybdenum titanium or a molybdenum titanium alloy.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments. In a specific implementation, each unit or structure may be implemented as an independent entity, or may be combined arbitrarily to be implemented as one or several entities, and the specific implementation of each unit or structure may refer to the foregoing method embodiment, which is not described herein again.
The TFT array substrate, the manufacturing method thereof, and the OLED display panel provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principle and implementation manner of the embodiments of the present application, and the description of the embodiments is only used to help understanding the technical solution and the core idea of the embodiments of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A TFT array substrate, comprising:
a substrate;
a first electrode layer comprising a first electrode trace disposed on the substrate;
the first insulating layer is arranged on the substrate and the first electrode layer, and a first through hole exposing the first electrode routing is formed in the first insulating layer;
the second electrode layer comprises a first lapping electrode arranged in the first via hole and connected with the first electrode routing, and a first protective electrode arranged on the first lapping electrode;
the second insulating layer is arranged on the second electrode layer and the first insulating layer, and a second through hole exposing the first protection electrode is formed in the second insulating layer;
and the third electrode layer comprises a second electrode wire which is arranged in the second via hole and connected with the first protection electrode.
2. The TFT array substrate of claim 1, wherein the first electrode layer further comprises a light-shielding layer disposed on the substrate;
the first insulating layer is also provided with a third through hole exposing the shading layer;
the second electrode layer further comprises a second lapping electrode arranged in the third via hole and connected with the shading layer, and a second protective electrode arranged on the second lapping electrode;
the second insulating layer is provided with a fourth through hole exposing the second protective electrode;
the third electrode layer further comprises a source electrode which is arranged in the fourth through hole and connected with the second protective electrode.
3. The TFT array substrate of claim 1, wherein the second electrode layer further comprises an active layer disposed on the first insulating layer, and a third protective electrode disposed on the active layer;
the second insulating layer is also provided with a fifth through hole exposing the third protective electrode;
the third electrode layer further comprises a source electrode which is arranged in the fifth via hole and connected with the third protective electrode.
4. The TFT array substrate of claim 3, wherein the second electrode layer further comprises a fourth guard electrode disposed on the active layer, the fourth guard electrode being spaced apart from the third guard electrode;
the second insulating layer is also provided with a sixth through hole exposing the fourth protective electrode;
the third electrode layer further comprises a drain electrode which is arranged in the sixth through hole and connected with the fourth protective electrode.
5. The TFT array substrate of claim 3, further comprising a third insulating layer disposed between the active layer and the second insulating layer, and a gate electrode disposed between the third insulating layer and the second insulating layer.
6. An OLED display panel, comprising: the TFT array substrate of any of claims 1-5.
7. A manufacturing method of a TFT array substrate is characterized by comprising the following steps:
providing a substrate, and manufacturing a first electrode layer on the substrate, wherein the first electrode layer comprises a first electrode wire arranged on the substrate;
manufacturing a first insulating layer on the substrate and the first electrode layer, and etching the first insulating layer to form a first via hole exposing the first electrode routing;
manufacturing a second electrode layer on the first insulating layer, wherein the second electrode layer comprises a first lap electrode arranged in the first via hole and connected with the first electrode routing, and a first protective electrode arranged on the first lap electrode;
manufacturing a second insulating layer on the second electrode layer and the first insulating layer, and etching the second insulating layer to form a second through hole exposing the first protection electrode;
and manufacturing a third electrode layer on the second insulating layer, wherein the third electrode layer comprises a second electrode wire which is arranged in the second via hole and connected with the first protective electrode.
8. The method of manufacturing a TFT array substrate as set forth in claim 7, wherein the first electrode layer further comprises a light-shielding layer disposed on the substrate;
the first insulating layer is also provided with a third through hole exposing the shading layer;
the second electrode layer further comprises a second lapping electrode arranged in the third via hole and connected with the shading layer, and a second protective electrode arranged on the second lapping electrode;
the second insulating layer is provided with a fourth through hole exposing the second protective electrode;
the third electrode layer further comprises a source electrode which is arranged in the fourth through hole and connected with the second protective electrode.
9. The method of claim 7, wherein the second electrode layer further comprises an active layer disposed on the first insulating layer, and a third protective electrode disposed on the active layer;
the second insulating layer is also provided with a fifth through hole exposing the third protective electrode;
the third electrode layer further comprises a source electrode which is arranged in the fifth via hole and connected with the third protective electrode.
10. The method of claim 9, wherein the second electrode layer further comprises a fourth guard electrode disposed on the active layer, and the fourth guard electrode is spaced apart from the third guard electrode;
the second insulating layer is also provided with a sixth through hole exposing the fourth protective electrode;
the third electrode layer further comprises a drain electrode which is arranged in the sixth through hole and connected with the fourth protective electrode.
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