CN113629070B - Array substrate, manufacturing method of array substrate and display panel - Google Patents
Array substrate, manufacturing method of array substrate and display panel Download PDFInfo
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- CN113629070B CN113629070B CN202110822871.1A CN202110822871A CN113629070B CN 113629070 B CN113629070 B CN 113629070B CN 202110822871 A CN202110822871 A CN 202110822871A CN 113629070 B CN113629070 B CN 113629070B
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The application provides an array substrate, a manufacturing method of the array substrate and a display panel. The array substrate comprises a substrate base plate and a thin film transistor layer arranged on the substrate base plate, wherein the substrate base plate is provided with a display area and a frame area positioned on one side of the display area. The thin film transistor layer comprises a first thin film transistor positioned in the frame area and a second thin film transistor positioned in the display area. The drain electrode of the first thin film transistor is electrically connected with the grid electrode of the second thin film transistor, and the source electrode and the drain electrode of the first thin film transistor are arranged on the same layer as the grid electrode of the second thin film transistor. The source and drain electrodes of the first thin film transistor and the grid electrode of the second thin film transistor are arranged on the same layer, and the source and drain electrodes of the first thin film transistor and the grid electrode of the second thin film transistor can be formed through a photomask manufacturing process, so that the manufacturing process of the array substrate is simplified, and the manufacturing cost is reduced.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display panel.
Background
In order to improve the display effect of the display device, the narrow frame design of the display device is receiving more and more attention. The narrow frame of the display device can be realized by a Gate Driver on Array (GOA) technology. The display panel adopting the GOA technology comprises a GOA area and a display area, wherein a Thin Film Transistor (TFT) in the GOA area outputs a signal to the TFT in the display area to realize scanning driving of the TFT in the display area.
However, since the size of the TFT required in the GOA region is large, the amount of heat generation thereof is also large. Therefore, different types of thin film transistors are required to be manufactured in the GOA area and the display area, respectively, which results in a complicated manufacturing process of the array substrate.
Disclosure of Invention
The application provides an array substrate, a manufacturing method of the array substrate and a display panel, and aims to solve the problem that in an existing display panel, manufacturing processes of the array substrate are complex due to the fact that thin film transistors are manufactured in a GOA area and a display area respectively.
In a first aspect, the present application provides an array substrate, including:
the substrate comprises a substrate base plate and a display area, wherein the substrate base plate is provided with a frame area positioned on one side of the display area;
the thin film transistor layer is arranged on the substrate and comprises a first thin film transistor positioned in the frame area and a second thin film transistor positioned in the display area, and the first thin film transistor comprises a first grid electrode, a first active layer, a first source electrode and a first drain electrode which are sequentially arranged on the substrate and are electrically connected with the first active layer;
the second thin film transistor comprises a second grid electrode, a second active layer, a second source electrode and a second drain electrode, wherein the second grid electrode and the second active layer are sequentially arranged on the substrate base plate; the first source electrode, the first drain electrode and the second grid electrode are arranged on the same layer, and the first drain electrode is electrically connected with the second grid electrode.
Optionally, the thin-film transistor layer includes a first connection line, and the first drain is electrically connected to the second gate through the first connection line; the first connecting line and the second grid or the second source are arranged on the same layer.
Optionally, the first connection line and the second source are disposed on the same layer; an interlayer dielectric layer is arranged between the first connecting line and the first drain electrode, a first through hole is formed in the interlayer dielectric layer, and the first connecting line penetrates through the first through hole and is electrically connected with the first drain electrode;
the thin film transistor layer comprises a second grid line positioned in the display area, and the second grid line is electrically connected with the second grid and arranged on the same layer; the interlayer dielectric layer is arranged between the first connecting line and the second gate line, a second through hole is formed in the interlayer dielectric layer, and the first connecting line penetrates through the second through hole and is electrically connected with the second gate line.
Optionally, a metal oxide layer is disposed between the first connection line and the interlayer dielectric layer, and the metal oxide layer and the second active layer are disposed on the same layer.
Optionally, the thin film transistor layer includes a first gate line located in the frame region, and the first gate line are disposed on the same layer; and a third through hole is formed in the interlayer dielectric layer, and the first connecting wire penetrates through the third through hole and is electrically connected with the first gate line.
Optionally, the thin film transistor layer includes a second connection line, and the first drain is electrically connected to the second gate through the second connection line; and a passivation layer and a pixel electrode are sequentially arranged on the thin film transistor layer, the pixel electrode is positioned in the display area, the pixel electrode is electrically connected with the second drain electrode, and the second connecting wire and the pixel electrode are arranged on the same layer.
Optionally, the thin film transistor layer includes a second gate line located in the display area, and the second gate line is electrically connected to the second gate line and disposed on the same layer;
and a fourth through hole corresponding to the first drain electrode and a fifth through hole corresponding to the second gate line are formed in the passivation layer, the second connecting line penetrates through the fourth through hole and is electrically connected with the first drain electrode, and the second connecting line penetrates through the fifth through hole and is electrically connected with the second gate line.
In a second aspect, the present application provides a method for manufacturing an array substrate, including the following steps:
providing a substrate, wherein the substrate is provided with a display area and a frame area positioned on one side of the display area;
manufacturing a first grid electrode on a frame area of the substrate base plate;
sequentially manufacturing an insulating layer and a first active layer on the first grid;
manufacturing a first source electrode and a first drain electrode on the first active layer, so that the first grid electrode, the first active layer, the first source electrode and the first drain electrode form a first thin film transistor, and manufacturing a second grid electrode in a display area of the substrate base plate;
manufacturing an interlayer dielectric layer on the first source electrode, the first drain electrode and the second grid electrode;
manufacturing a metal oxide layer on the interlayer dielectric layer;
patterning the metal oxide layer to form a second active layer over the second gate electrode;
and manufacturing a second source electrode and a second drain electrode on the second active layer, so that the second grid electrode, the second active layer, the second source electrode and the second drain electrode form a second thin film transistor, and the first drain electrode is electrically connected with the second grid electrode.
Optionally, a second gate line is further disposed on the display area of the substrate, and the second gate line is electrically connected to the second gate and disposed on the same layer; the step of forming a second source and a second drain on the second active layer and electrically connecting the first drain to the second gate includes:
respectively forming a first through hole and a second through hole in the positions, corresponding to the first drain electrode and the second gate line, of the metal oxide layer;
and manufacturing a first connecting wire on the metal oxide layer, and a second source electrode and a second drain electrode which are electrically connected with the second active layer, wherein the first connecting wire penetrates through a first through hole and is electrically connected with the first drain electrode, and the first connecting wire penetrates through a second through hole and is electrically connected with the second gate line, so that the first drain electrode is electrically connected with the second gate line.
Optionally, a second gate line is further disposed on the display area of the substrate, and the second gate line is electrically connected to the second gate and disposed on the same layer; the step of forming a second source and a second drain on the second active layer and electrically connecting the first drain to the second gate includes:
manufacturing a second source electrode and a second drain electrode on the second active layer, so that the second grid electrode, the second active layer, the second source electrode and the second drain electrode form a second thin film transistor;
manufacturing a passivation layer on the second source electrode and the second drain electrode;
respectively forming a fourth through hole and a fifth through hole in positions, corresponding to the first drain electrode and the second gate line, on the passivation layer;
manufacturing a transparent electrode layer on the passivation layer;
and patterning the transparent electrode layer to form a second connecting wire, enabling the second connecting wire to penetrate through the fourth through hole to be electrically connected with the first drain electrode, and enabling the second connecting wire to penetrate through the fifth through hole to be electrically connected with the second gate line, so that the first drain electrode is electrically connected with the second gate electrode.
In a third aspect, the present application provides a display panel including the array substrate according to the embodiments of the present application.
The application provides an array substrate, a manufacturing method of the array substrate and a display panel. The array substrate comprises a substrate base plate and a thin film transistor layer arranged on the substrate base plate, wherein the substrate base plate is provided with a display area and a frame area positioned on one side of the display area. The thin film transistor layer comprises a first thin film transistor positioned in the frame area and a second thin film transistor positioned in the display area. The drain electrode of the first thin film transistor is electrically connected with the grid electrode of the second thin film transistor, and the source electrode and the drain electrode of the first thin film transistor are arranged on the same layer as the grid electrode of the second thin film transistor. The source and drain electrodes of the first thin film transistor and the grid electrode of the second thin film transistor are arranged on the same layer, and the source and drain electrodes of the first thin film transistor and the grid electrode of the second thin film transistor can be formed through a photomask manufacturing process, so that the manufacturing process of the array substrate is simplified, and the manufacturing cost is reduced.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an array substrate after a first thin film transistor and a second gate electrode are manufactured on a substrate;
FIG. 2 is a schematic structural diagram of an array substrate after an interlayer dielectric layer and a metal oxide layer are formed on the structure of FIG. 1;
FIG. 3 is a schematic structural diagram of the array substrate after the structure of FIG. 2 is provided with through holes;
FIG. 4 is a schematic structural view of an array substrate after a third conductive layer is deposited on the structure of FIG. 3;
FIG. 5 is a schematic structural diagram of the array substrate after patterning the third conductive layer in FIG. 4;
FIG. 6 is a schematic structural diagram of an array substrate after an interlayer dielectric layer is formed on the structure of FIG. 5;
FIG. 7 is a schematic structural diagram of an array substrate after a passivation layer and a pixel electrode are formed on the structure of FIG. 6;
FIG. 8 is a schematic structural view of an array substrate after a third conductive layer is deposited on the structure of FIG. 2;
FIG. 9 is a schematic structural diagram of the array substrate after patterning the third conductive layer on the structure of FIG. 8;
FIG. 10 is a schematic structural diagram of an array substrate after an interlayer dielectric layer is formed on the structure of FIG. 9;
FIG. 11 is a schematic structural view of an array substrate after a passivation layer and a pixel electrode are formed on the structure of FIG. 10;
fig. 12 is a schematic flowchart illustrating a manufacturing method of an array substrate according to an embodiment of the present disclosure;
fig. 13 is a schematic flowchart of step S8 in fig. 12;
fig. 14 is a schematic flowchart of another embodiment of step S8 in fig. 12.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
The embodiment of the application provides an array substrate, a manufacturing method of the array substrate and a display panel. The following are detailed descriptions. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
In a first aspect, the present application provides an array substrate 10. As shown in fig. 1, the array substrate 10 includes a substrate 11 and a thin-film transistor layer 12 disposed on the substrate 11. The substrate base plate 11 has a display area 11b and a frame area 11a on the side of the display area 11 b. Thin-film transistor layer 12 includes a first thin-film transistor 121 located in frame region 11a, and a second thin-film transistor 122 located in display region 11 b.
Referring to fig. 1 to 5, the first thin film transistor 121 includes a first gate electrode 1214a, a first active layer 1211, a first source electrode 1212 and a first drain electrode 1213 electrically connected to the first active layer 1211, which are sequentially disposed on the substrate 11.
The second thin film transistor 122 includes a second gate electrode 1224a, a second active layer 1221, and a second source electrode 1222 and a second drain electrode 1223 electrically connected to the second active layer 1221, which are sequentially disposed on the substrate base 11. The first source 1212, the first drain 1213 and the second gate 1224a are disposed at the same layer, and the first drain 1213 and the second gate 1224a are electrically connected to realize the scan driving of the first tft 121 in the frame region 11a to the second tft 122 in the display region 11 b.
Specifically, after a voltage is applied to the first gate electrode 1214a of the first thin film transistor 121, the first source electrode 1212 and the first drain electrode 1213 of the first thin film transistor 121 are turned on, and the first drain electrode 1213 transmits an electrical signal to the second gate electrode 1224a of the second thin film transistor 122 through the first connection line 21. When the second gate electrode 1224a is applied with a voltage, the second source electrode 1222 and the second drain electrode 1223 of the second thin film transistor 122 are turned on, and the second drain electrode 1223 writes a signal voltage to a pixel connected thereto. Thereby realizing the driving of the second thin film transistor 122 by the first thin film transistor 121.
Thin Film Transistors (TFTs) include Indium Gallium Zinc Oxide (IGZO) TFTs and amorphous silicon (a-Si) TFTs. The IGZO TFT is a TFT with an active layer material adopting indium gallium zinc oxide, and the a-Si TFT is a TFT with an active layer material adopting amorphous silicon. The IGZO TFT has advantages of high carrier mobility, low light sensitivity, and the like, and is more suitable for use in the display region 11 b. The a-Si TFT has the advantages of small self-heating effect and good stability, and is more suitable for being used in the frame region 11a to drive the TFT in the display region 11 b.
As shown in fig. 6, in the embodiment of the present application, the first thin film transistor 121 is an a-Si thin film transistor, and the second thin film transistor 122 is an IGZO thin film transistor. That is, IGZO TFTs are used in the display region 11b, and a-Si TFTs are used in the frame region 11 a. Therefore, when the IGZO TFT is used in the frame region 11a, the self-heating effect of the IGZO TFT is large, and thus the TFT device in the display region 11b is prevented from being damaged.
By arranging the first source 1212, the first drain 1213 and the second gate 1224a in the same layer, that is, by arranging the source and the drain of the first tft 121 and the gate of the second tft 122 in the same layer, a metal layer may be deposited and then patterned when the first source 1212, the first drain 1213 and the second gate 1224a are fabricated. The first source electrode 1212, the first drain electrode 1213 and the second gate electrode 1224a may be formed by a single mask process. Therefore, the problem of complicated manufacturing process of the array substrate 10 caused by manufacturing different types of thin film transistors in the GOA region and the display region 11b can be avoided.
Referring to fig. 5 and 6, in the embodiment of the present application, the thin-film transistor layer 12 includes a first connection line 21. In the frame region 11a, the first drain electrode 1213 is electrically connected to the first connecting line 21, and in the display region 11b, the second gate electrode 1224a is electrically connected to the first connecting line 21. Thus, the first drain electrode 1213 is electrically connected to the second gate electrode 1224a, so that the first thin film transistor 121 in the frame outputs a signal to the second thin film transistor 122 in the display region 11b, thereby performing scanning driving on the second thin film transistor 122 in the display region 11 b.
It should be noted that the electrical connection between the first drain 1213 and the second gate 1224a can be implemented in various ways. For example, the first connecting line 21 may be disposed on the same layer as the second gate electrode 1224a, i.e., the first connecting line 21 is disposed on the same layer as the first source electrode 1212, the first drain electrode 1213 and the second gate electrode 1224 a. When the first connection line 21, the first source 1212, the first drain 1213 and the second gate 1224a are formed, a metal layer may be deposited and then patterned. When the metal layer is patterned, the first connection line 21 is electrically connected to the first drain 1213 and the second gate 1224 a.
Referring to fig. 5 to 7, in other embodiments of the present application, the first connection line 21 and the second source 1222 are disposed at the same layer. An interlayer dielectric layer 13 is disposed between the first connecting line 21 and the first drain 1213, a first through hole 301 is formed in the interlayer dielectric layer 13, and the first connecting line 21 passes through the first through hole 301 and is electrically connected to the first drain 1213.
The thin-film transistor layer 12 includes a second gate line 1224b in the display region 11b, and the second gate line 1224b is electrically connected to the second gate electrode 1224a and disposed at the same layer. The second gate line 1224b and the second gate electrode 1224a may be formed by patterning the same metal layer. An interlayer dielectric layer 13 is disposed between the first connecting line 21 and the second gate line 1224b, a second via hole 302 is formed in the interlayer dielectric layer 13, and the first connecting line 21 passes through the second via hole 302 and is electrically connected to the second gate line 1224 b.
In fabricating the first connection line 21, the second source 1222 and the second drain 1223, an interlayer dielectric layer 13 may be first fabricated on the first source 1212, the first drain 1213 and the second gate 1224a, then a metal layer may be deposited on the interlayer dielectric layer 13, and finally the metal layer may be patterned to form the first connection line 21, the second source 1222 and the second drain 1223. This achieves that the first connection line 21 and the second source 1222 are arranged on the same layer.
Referring to fig. 3 to 6, in the frame region 11a, the first connection line 21 passes through the first through hole 301 and is electrically connected to the first drain electrode 1213, and in the display region 11b, the first connection line 21 passes through the second through hole 302 and is electrically connected to the second gate line 1224b, so as to electrically connect the first drain electrode 1213 of the first tft 121 and the second gate electrode 1224a of the second tft 122.
In the embodiment of the present application, as shown in fig. 7, the metal oxide layer 14 is disposed between the first connection line 21 and the interlayer dielectric layer 13, and the metal oxide layer 14 is disposed in the same layer as the second active layer 1221.
Referring to fig. 2 to 5, after the interlayer dielectric layer 13 is formed on the first source electrode 1212 and the first drain electrode 1213, the metal oxide layer 14 is formed on the interlayer dielectric layer 13. A metal layer is then deposited over the metal oxide and patterned with the metal oxide layer 14. The metal layer is patterned to form the first connection line 21 in the frame region 11a and to form the second source 1222 and the second drain 1223 of the second thin film transistor 122 in the display region 11 b. The metal oxide layer 14 is patterned to form the second active layer 1221 of the second thin film transistor 122 in the display region 11b, i.e., the metal oxide layer 14 and the second active layer 1221 are disposed in the same layer.
In the frame region 11a, due to the shielding of the metal layer from the metal oxide layer 14, the metal oxide layer 14 under the first connection line 21 in the frame region 11a is retained, i.e., the metal oxide layer 14 is disposed between the first connection line 21 and the interlayer dielectric layer 13.
It should be noted that, after the metal oxide layer 14 is formed on the interlayer dielectric layer 13, it may also be patterned to form the second active layer 1221 in the display area 11b and remove the metal oxide layer 14 in the frame area 11 a. Then, a metal layer is deposited on the metal oxide layer and the interlayer dielectric layer 13, and is patterned to form the first connection line 21 in the bezel region 11a and the second source 1222 and the second drain 1223 in the display region 11 b. In this manner, the first connecting line 21 in the frame region 11a is directly connected to the interlayer dielectric layer 13.
In an embodiment of the present application, the material of the metal Oxide layer 14 is Indium Gallium Zinc Oxide (IGZO). It is understood that the material of the metal Oxide layer 14 may also be other types of metal oxides such as Indium Gallium Oxide (IGO), which may be determined according to actual situations.
As shown in fig. 7, in the embodiment of the present disclosure, the thin-film transistor layer 12 includes a first gate line 1214b located in the frame region 11a, and the first gate line 1214b is disposed on the same layer as the first gate line 1214 a. When the first gate electrode 1214a and the first gate line 1214b are formed, the first gate electrode 1214a and the first gate line 1214b may be formed by depositing a metal layer and then patterning the metal layer.
The interlayer dielectric layer 13 is formed with a third via 303, and the first connection line 21 passes through the third via 303 and is electrically connected to the first gate line 1214 b. The opening of the third via 303 may be performed by performing photolithography on the interlayer dielectric layer 13.
By electrically connecting the first connecting line 21 to the first gate line 1214b through the third via 303, the resistance of the first connecting line 21 may be reduced, facilitating the transmission of an electrical signal between the first drain electrode 1213 of the first thin film transistor 121 and the second gate electrode 1224a of the second thin film transistor 122.
It is to be noted that the connection line between the first drain electrode 1213 and the second gate electrode 1224a may be disposed on the same layer as the pixel electrode 16, in addition to the second source electrode 1222 and the second drain electrode 1223. In some embodiments of the present application, after the thin-film transistor layer 12 is fabricated, a passivation layer 15 and a pixel electrode 16 are sequentially fabricated on the thin-film transistor layer 12.
Referring to fig. 8 to 11, after the passivation layer 15 is formed, an ITO film is deposited on the passivation layer 15, and then the ITO film is patterned. In the frame region 11a, the ITO film is patterned to form the second connection line 22. In the display region 11b, the pixel electrode 16 and the second connection line 22 are formed after patterning the ITO film, i.e., the second connection line 22 is disposed at the same layer as the pixel electrode 16. The first drain electrode 1213 is electrically connected to the second gate electrode 1224a by a second connection line 22, so that electrical connection is achieved between the first thin film transistor 121 and the second thin film transistor 122. The pixel electrode 16 is electrically connected to the second drain electrode 1223, so that the second thin film transistor 122 outputs an electrical signal to the pixel electrode 16.
The material of the passivation layer 15 includes a material with good insulating properties, such as soluble Polytetrafluoroethylene (PFA), and can be determined according to actual conditions. The material of the pixel electrode 16 layer is typically a transparent conductive material such as Indium Tin Oxide (ITO).
In some embodiments of the present application, as shown in fig. 11, thin-film transistor layer 12 includes a second gate line 1224b located in display area 11b, and second gate line 1224b is electrically connected to second gate electrode 1224a and disposed on the same layer. It is noted that the second gate electrode 1224a and the second gate line 1224b may be implemented by depositing a metal layer and then patterning the metal layer.
The passivation layer 15 is opened with a fourth via hole 304 corresponding to the first drain electrode 1213 and a fifth via hole 305 corresponding to the second gate line 1224b, the second connection line 22 passes through the fourth via hole 304 and is electrically connected to the first drain electrode 1213, and the second connection line 22 passes through the fifth via hole 305 and is electrically connected to the second gate line 1224 b. Thereby, the electrical connection between the first thin film transistor 121 and the second thin film transistor 122 is achieved.
In order to reduce the resistance between the first thin film transistor 121 and the second thin film transistor 122, the second link line 22 may be connected with the second gate line 1224b to reduce the resistance of the second link line 22. As shown in fig. 11, a sixth through hole 306 is opened on the passivation layer 15, and the second connection line 22 passes through the sixth through hole 306 and is electrically connected to the first gate line 1214 b.
It should be noted that the array substrate 10 includes a plurality of first thin film transistors 121 and a plurality of second thin film transistors 122, and the plurality of second thin film transistors 122 are generally distributed in an array in the display area 11 b. Each of the first thin film transistors 121 is electrically connected to a plurality of second thin film transistors 122 through one scan line to implement driving of the plurality of second thin film transistors 122 connected to the scan line.
In a second aspect, the present application provides a method for manufacturing an array substrate 10, as shown in fig. 12, including the following steps:
s1, providing a substrate 11, where the substrate 11 has a display area 11b and a frame area 11a located on one side of the display area 11 b;
s2, forming a first gate 1214a on the frame region 11a of the substrate 11;
s3, sequentially forming an insulating layer 17 and a first active layer 1211 on the first gate electrode 1214 a;
s4, forming a first source 1212 and a first drain 1213 on the first active layer 1211, such that the first gate 1214a, the first active layer 1211, the first source 1212 and the first drain 1213 form a first thin film transistor 121, and forming a second gate 1224a in the display region 11b of the substrate 11;
s5, forming an interlayer dielectric layer 13 on the first source 1212, the first drain 1213 and the second gate 1224 a;
s6, manufacturing a metal oxide layer 14 on the interlayer dielectric layer 13;
s7, patterning the metal oxide layer 14 to form a second active layer 1221 over the second gate 1224 a;
s8, fabricating a second source 1222 and a second drain 1223 on the second active layer 1221, such that the second gate 1224a, the second active layer 1221, the second source 1222, and the second drain 1223 form a second thin film transistor 122, and the first drain 1213 is electrically connected to the second gate 1224 a.
First, a substrate 11 having a display area 11b and a frame area 11a on one side of the display area 11b is provided. The material of the substrate base plate 11 is usually glass. As shown in fig. 1, a first conductive layer 61 is deposited on the substrate 11 and then patterned to form a first gate electrode 1214a and a first gate line 1214b in the frame region 11 a. The material of the first conductive layer 61 may be copper or aluminum, which has good conductive properties.
With reference to fig. 1 and fig. 2, after the first gate electrode 1214a and the first gate line 1214b are formed, an insulating layer 17 is formed on the first conductive layer 61, and the insulating layer 17 includes silicon nitride or silicon oxide and can be formed by a chemical vapor deposition method. Thereafter, an amorphous silicon layer 50 and a second conductive layer 62 are sequentially deposited on the insulating layer 17, and patterning is performed on the second conductive layer 62 and the amorphous silicon layer 50.
In the frame region 11a, the amorphous silicon layer 50 is patterned to form a first active layer 1211 of the first thin film transistor 121, and the second conductive layer 62 is patterned in the frame region 11a to form a first source 1212 and a first drain 1213 of the first thin film transistor 121. The gate electrode of the second thin film transistor 122 is formed after the second conductive layer 62 is patterned in the display region 11 b.
With reference to fig. 1, 2 and 3, an interlayer dielectric layer 13 is formed on the first source electrode 1212, the first drain electrode 1213 and the second gate electrode 1224a by deposition, such that the interlayer dielectric layer 13 covers the insulating layer 17, the amorphous silicon layer 50 and the second conductive layer 62. The material of the interlayer dielectric layer 13 includes silicon oxide, silicon nitride and other materials with good insulating property.
Next, a metal Oxide layer 14 is deposited on the interlayer dielectric layer 13, wherein the metal Oxide layer 14 is typically Indium Gallium Zinc Oxide (IGZO). It is understood that the material of the metal Oxide layer 14 may also be other types of metal oxides such as Indium Gallium Oxide (IGO), which may be determined according to actual situations.
Referring to fig. 3, 4 and 5, after the metal oxide layer 14 is formed, a patterning process is performed to form the second active layer 1221 of the second thin film transistor 122 in the display region 11 b. The second active layer 1221 corresponds to the position of the second gate electrode 1224a, i.e., the second active layer 1221 is located above the second gate electrode 1224 a.
Finally, a second source electrode 1222 and a second drain electrode 1223 are formed on the second active layer 1221 such that the second gate electrode 1224a, the second active layer 1221, the second source electrode 1222, and the second drain electrode 1223 form the second thin film transistor 122, and the first drain electrode 1213 is electrically connected to the second gate electrode 1224 a. Referring to fig. 3, 4 and 5, a second source electrode 1222 and a second drain electrode 1223 are formed by patterning the third conductive layer 63 deposited on the metal oxide layer 14.
Note that the electrical connection between the first drain 1213 and the second gate 1224a of the first thin film transistor 121 can be achieved in various ways.
As shown in fig. 13, in some embodiments of the present application, step S8 includes the following steps:
s81a, forming a first via 301 and a second via 302 in the metal oxide layer 14 at positions corresponding to the first drain 1213 and the second gate line 1224b, respectively;
s82a, forming a first connecting line 21 on the metal oxide layer 14, and a second source 1222 and a second drain 1223 electrically connected to the second active layer 1221, wherein the first connecting line 21 is electrically connected to the first drain 1213 through a first via 301, and the first connecting line 21 is electrically connected to the second gate line 1224b through a second via 302, such that the first drain 1213 is electrically connected to the second gate 1224 a.
With reference to fig. 2 and 3, a second gate line 1224b is disposed on the display region 11b of the substrate 11, and the second gate line 1224b is electrically connected to the second gate electrode 1224a and disposed on the same layer. After the metal oxide layer 14 is formed on the interlayer dielectric layer 13, a first via hole 301 and a second via hole 302 are respectively formed at positions of the metal oxide layer 14 corresponding to the first drain electrode 1213 and the second gate line 1224 b.
A third conductive layer 63 is then deposited over the metal oxide layer 14, and the third conductive layer 63 is electrically connected to the first drain 1213 through the first via 301, and the third conductive layer 63 is electrically connected to the second gate 1224a through the second via 302.
After patterning the third conductive layer 63, the first connection line 21 electrically connected to the first drain electrode 1213 is formed in the frame region 11a, and the first connection line 21 electrically connected to the second gate electrode 1224a is formed in the display region 11 b. The first drain 1213 and the second gate 1224a are electrically connected by a first connection line 21. The portion of the second conductive layer 62 over the second active layer 1221 in the display region 11b is patterned to form a second source 1222 and a second drain 1223 of the second thin film transistor 122.
With reference to fig. 2, 3 and 4, the first connection line 21 is disposed on the same layer as the second source electrode 1222 and the second drain electrode 1223, and the third conductive layer 63 where the first connection line 21 is disposed is separated from the second conductive layer 62 where the first drain electrode 1213 and the second gate line 1224b are disposed by only one interlayer dielectric layer 13. When the first through hole 301 and the second through hole 302 are formed and the first connection line 21 is connected to the first drain electrode 1213 and the second gate line 1224b, respectively, the process is easily performed, and the process difficulty caused by forming a deep through hole is avoided.
In other embodiments of the present application, as shown in fig. 14, step S8 includes the following steps:
s81b, fabricating a second source 1222 and a second drain 1223 on the second active layer 1221, such that the second gate 1224a, the second active layer 1221, the second source 1222, and the second drain 1223 form a second thin film transistor 122;
s82b, fabricating a passivation layer 15 on the second source 1222 and the second drain 1223;
s83b, forming a fourth via 304 and a fifth via 305 on the passivation layer 15 at positions corresponding to the first drain electrode 1213 and the second gate line 1224b, respectively;
s84b, manufacturing a transparent electrode layer 40 on the passivation layer 15;
s85b, the transparent electrode layer 40 is patterned to form a second connection line 22, the second connection line 22 passes through the fourth through hole 304 to electrically connect to the first drain electrode 1213, and the second connection line 22 passes through the fifth through hole 305 to electrically connect to the second gate line 1224b, such that the first drain electrode 1213 is electrically connected to the second gate electrode 1224 a.
Referring to fig. 2, 8, 9 and 10, after sequentially depositing a metal oxide layer 14 and a third conductive layer 63 on the interlayer dielectric layer 13, the metal oxide layer 14 and the third conductive layer 63 are patterned to form a second active layer 1221, a second source electrode 1222 and a second drain electrode 1223 in the display region 11 b. The second active layer 1221, the second source electrode 1222, and the second drain electrode 1223 form the second thin film transistor 122. Then, an interlayer dielectric layer 13 is formed on the second source 1222 and the second drain 1223 to form the thin film transistor layer 12.
Referring to fig. 9 and 10, after the thin-film transistor layer 12 is fabricated, a passivation layer 15 is fabricated thereon. The material of the passivation layer 15 includes soluble Polytetrafluoroethylene (PFA), polyvinyl chloride (PV), and other materials with good insulating properties, and can be determined according to actual conditions.
Referring to fig. 10 and 11, a fourth via hole 304 and a fifth via hole 305 are formed in the passivation layer 15 at positions corresponding to the first drain electrode 1213 and the second gate line 1224b, respectively, and the via holes may be formed by a photolithography process. Thereafter, a transparent conductive layer is deposited on the passivation layer 15, and electrically connected to the first drain electrode 1213 through the fourth via hole 304, and electrically connected to the second gate line 1224b through the fifth via hole 305, so as to electrically connect the first drain electrode 1213 and the second gate electrode 1224 a. The material of the transparent conductive layer is generally a material having good light transmittance and conductivity, such as Indium Tin Oxide (ITO).
With reference to fig. 10 and 11, the transparent conductive layer is patterned to form the second connection line 22 and the pixel electrode 16. The second connection line 22 is electrically connected to the first drain electrode 1213 of the first tft 121 and the second gate electrode 1224a of the second tft 122, respectively, and the pixel electrode 16 is electrically connected to the second drain electrode 1223 of the second tft 122.
As shown in fig. 11, in order to reduce the connection resistance between the first drain electrode 1213 and the second gate electrode 1224a, a sixth via hole 306 may be opened in the passivation layer 15 at a position corresponding to the first gate line 1214b, and the second connection line 22 may be electrically connected to the first gate line 1214b through the sixth via hole 306.
In a third aspect, the present application provides a display panel. The display panel includes an array substrate 10 provided in the embodiment of the present application.
The array substrate, the manufacturing method of the array substrate, and the display panel provided by the present application are introduced in detail, and specific examples are applied in the present application to explain the principle and the implementation manner of the present application, and the description of the above embodiments is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (11)
1. An array substrate, comprising:
the display device comprises a substrate, a display area and a frame area, wherein the frame area is positioned on one side of the display area;
the thin film transistor layer is arranged on the substrate and comprises a first thin film transistor positioned in the frame area and a second thin film transistor positioned in the display area, and the first thin film transistor comprises a first grid electrode, a first active layer, a first source electrode and a first drain electrode which are sequentially arranged on the substrate and are electrically connected with the first active layer;
the second thin film transistor comprises a second grid electrode, a second active layer, a second source electrode and a second drain electrode, wherein the second grid electrode and the second active layer are sequentially arranged on the substrate base plate; the first source electrode, the first drain electrode and the second grid electrode are arranged on the same layer;
the thin film transistor layer comprises a second grid line positioned in the display area, and the second grid line is electrically connected with the second grid and arranged on the same layer; the first drain electrode is electrically connected to the second gate line so that the first drain electrode and the second gate electrode are electrically connected.
2. The array substrate of claim 1, wherein the thin-film transistor layer comprises a first connection line, and the first drain electrode is electrically connected to the second gate electrode through the first connection line; the first connecting line and the second grid or the second source are arranged on the same layer.
3. The array substrate of claim 2, wherein the first connecting line and the second source electrode are disposed on the same layer; an interlayer dielectric layer is arranged between the first connecting line and the first drain electrode, a first through hole is formed in the interlayer dielectric layer, and the first connecting line penetrates through the first through hole and is electrically connected with the first drain electrode;
the interlayer dielectric layer is arranged between the first connecting line and the second gate line, a second through hole is formed in the interlayer dielectric layer, and the first connecting line penetrates through the second through hole and is electrically connected with the second gate line.
4. The array substrate of claim 3, wherein a metal oxide layer is disposed between the first connecting line and the interlayer dielectric layer, and the metal oxide layer is disposed in the same layer as the second active layer.
5. The array substrate of claim 3, wherein the thin-film transistor layer comprises a first gate line in the frame region, and the first gate line are disposed on the same layer; and a third through hole is formed in the interlayer dielectric layer, and the first connecting wire penetrates through the third through hole and is electrically connected with the first gate line.
6. The array substrate of claim 1, wherein the thin-film transistor layer comprises a second connection line, and the first drain electrode is electrically connected to the second gate electrode through the second connection line; and a passivation layer and a pixel electrode are sequentially arranged on the thin film transistor layer, the pixel electrode is positioned in the display area, the pixel electrode is electrically connected with the second drain electrode, and the second connecting wire and the pixel electrode are arranged on the same layer.
7. The array substrate of claim 6, wherein the passivation layer defines a fourth via corresponding to the first drain electrode and a fifth via corresponding to the second gate line, the second connection line electrically connects to the first drain electrode through the fourth via, and the second connection line electrically connects to the second gate line through the fifth via.
8. The manufacturing method of the array substrate is characterized by comprising the following steps of:
providing a substrate, wherein the substrate is provided with a display area and a frame area positioned on one side of the display area;
manufacturing a first grid electrode on a frame area of the substrate base plate;
sequentially manufacturing an insulating layer and a first active layer on the first grid;
manufacturing a first source electrode and a first drain electrode on the first active layer, so that the first grid electrode, the first active layer, the first source electrode and the first drain electrode form a first thin film transistor, and manufacturing a second grid electrode and a second grid electrode line on a display area of the substrate, so that the second grid electrode line and the second grid electrode are electrically connected and arranged on the same layer;
manufacturing an interlayer dielectric layer on the first source electrode, the first drain electrode and the second grid electrode;
manufacturing a metal oxide layer on the interlayer dielectric layer;
patterning the metal oxide layer to form a second active layer over the second gate electrode;
and manufacturing a second source electrode and a second drain electrode on the second active layer, so that the second grid electrode, the second active layer, the second source electrode and the second drain electrode form a second thin film transistor, and the first drain electrode is electrically connected with the second grid line, so that the first drain electrode is electrically connected with the second grid electrode.
9. The method as claimed in claim 8, wherein the step of forming a second source electrode and a second drain electrode on the second active layer and electrically connecting the first drain electrode to the second gate line so as to electrically connect the first drain electrode to the second gate line comprises:
respectively forming a first through hole and a second through hole in the positions, corresponding to the first drain electrode and the second gate line, of the metal oxide layer;
and manufacturing a first connecting wire on the metal oxide layer, and a second source electrode and a second drain electrode which are electrically connected with the second active layer, wherein the first connecting wire penetrates through the first through hole and is electrically connected with the first drain electrode, and the first connecting wire penetrates through the second through hole and is electrically connected with the second gate line, so that the first drain electrode is electrically connected with the second gate electrode.
10. The method as claimed in claim 8, wherein the step of forming a second source electrode and a second drain electrode on the second active layer and electrically connecting the first drain electrode to the second gate line so as to electrically connect the first drain electrode to the second gate line comprises:
manufacturing a second source electrode and a second drain electrode on the second active layer, so that the second grid electrode, the second active layer, the second source electrode and the second drain electrode form a second thin film transistor;
manufacturing a passivation layer on the second source electrode and the second drain electrode;
respectively forming a fourth through hole and a fifth through hole in positions, corresponding to the first drain electrode and the second gate line, on the passivation layer;
manufacturing a transparent electrode layer on the passivation layer;
and patterning the transparent electrode layer to form a second connecting wire, enabling the second connecting wire to penetrate through the fourth through hole to be electrically connected with the first drain electrode, and enabling the second connecting wire to penetrate through the fifth through hole to be electrically connected with the second gate line, so that the first drain electrode is electrically connected with the second gate electrode.
11. A display panel comprising the array substrate according to any one of claims 1 to 7.
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