JPH05153180A - Demodulator for phase modulated signal - Google Patents

Abstract

PURPOSE:To constitute a demodulator for a digital modulated signal of a demodulated data generation circuit having no relation with the height of receiving local frequency. CONSTITUTION:The phase sampling circuit 5 of a phase modulated signal, a phase difference detection circuit 7, the demodulated data generation circuit 9, and a parallel/serial conversion circuit 10 are provided, and in addition, the demodulates data generation circuit 9 is constituted of a logic circuit. By changing the logic of the logic circuit by impressing a data select signal 13 whose logical output is inputted from the outside, the same demodulated data output is obtained for the same phase modulated signal whether inputted local signal frequency is higher or lower compared with the frequency of a received signal to be demodulated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase modulation signal demodulation device used in a digital transmission device in wireless communication or the like.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a conventional demodulator for a 4 / π shift QPSK signal (hereinafter referred to as a 4-phase phase modulation signal), and FIG. 2 (a) is a schematic block diagram.

In FIG. 2A, 1 is a carrier signal and 2 is a carrier signal.
Is a local signal, 3 is a received signal, 4 is a demodulator,
A phase sampling circuit 5, which performs sampling operation by a sampling signal source 5, a phase difference detection circuit 7 that detects a phase transition between a previous symbol and a current symbol using a symbol synchronization signal 8, and data is demodulated by the phase transition from the phase difference detection circuit. 2 bit parallel data is converted into serial demodulated data by using the demodulated data generation circuit 9 and the bit cycle signal 11.
It is composed of a parallel-serial conversion circuit 10 for converting into 12.

When the frequency of the local signal 2 is lower than the frequency of the carrier signal (hereinafter referred to as A mode)
On the contrary, when it is high (hereinafter, referred to as B mode), the demodulated data generation circuit 9 needs to prepare the logic circuits shown in FIGS. 2B and 2C.

The states of the phase transition in the phase difference detection circuit 7 in the A and B modes are shown in FIGS. 3 (a) and 4 (a), and the data of the demodulation data generation circuit 9 for this phase transition is shown. The correspondence is shown in FIG. 3 (b) and FIG. 4 (b).

First, it is assumed that the carrier signal 1 undergoes a phase transition (1, 2, 3, 4) as shown in Table 1. At this time, in the A mode (when the frequency of the local signal 2 is lower than the frequency of the carrier signal 1), the received signal 3 is input to the demodulator 4 with the same phase transition as in Table 1 as shown in FIG. .. In the demodulation device 4, the phase sampling circuit 5 samples the reception signal 3 using the sampling signal from the sampling signal source 6, and the phase state of the reception signal 3 is represented by 2 bits. The phase difference detection circuit 7 uses the symbol synchronization signal 8 to detect the phase transition between the previous symbol and the current symbol (FIG. 3A). Then, based on this phase transition, the demodulation data generation circuit 9 demodulates the data.
(Fig. 3 (b)).

In this case, the demodulation data generation circuit 9 (see FIG.
(b) is the most significant bit MSB and the least significant bit LSB
For the range, 2-bit parallel data M and L as shown in Table (1) are output. Parallel-serial conversion circuit 10
Converts the 2-bit parallel data M and L into serial demodulated data 12 using the bit synchronization signal 11.

[0008]

As described above, conventionally, in the case of the A mode in which the frequency of the local signal 2 is lower than the frequency of the carrier signal 1, the demodulation operation as described above is performed. Is the phase transition as shown in Table (2)
(1 ', 2', 3 ', 4'), where the frequency of the local signal 2 is higher than the frequency of the carrier signal 1 in B mode, the phase transition of the received signal 3 applied to the demodulator 4 is:
4 (a), and accordingly, when the demodulator 4 degenerates into a 4-phase phase modulation signal, it becomes as shown in FIG. 4 (b). Therefore, if the demodulated data generation circuit 9 has the same configuration as in the A mode shown in FIG.
There is a problem that the bit parallel data M and L are erroneously demodulated.

Although this problem can be solved by a demodulation data generation circuit having a structure in which the most significant bit MSB is used as the upper bit as shown in FIG. 2C, for example, this problem is newly added. In addition, since the demodulation data generation circuit must be configured, the demodulator is not versatile and the number of devices increases, which is a new problem.

An object of the present invention is to solve the problem of erroneous demodulation of the demodulation data generation circuit in the above-described conventional demodulator for phase-modulated signals and to provide a demodulator for phase-modulated signals having general versatility.

[0011]

According to the present invention, a demodulation data generation circuit included in a demodulation device for a phase modulation signal is configured by a logic circuit, and a control signal is input to the logic circuit from the outside, and a local frequency is set to a carrier frequency. On the other hand, by changing the logic formation depending on whether it is high or low, the demodulation output is the same regardless of whether the local frequency is high or low with respect to the carrier frequency.

[0012]

According to the present invention, the demodulation data generation circuit corresponding to the high and low of the local frequency with respect to the carrier frequency of the receiving system of the demodulator of the phase modulation signal is simply constructed, and the local frequency and the carrier frequency are independent of the high and low. One demodulation data generation circuit becomes available.

[0013]

1 shows a demodulator for a four-phase phase modulated signal according to an embodiment of the present invention. FIG. 1 (a) is a block diagram of the demodulator, and FIG. 1 (b) is a block diagram of FIG. 1 (a). A demodulated data generation circuit, 13 in FIG. 1A is a data selection signal (DTSEL) applied to the demodulated data generation circuit 9. Table 3 shows the input / output relationship of the phase shift transitions (0-3, 0'-3 ') according to this embodiment and the logic circuit of FIG. 1 (b).

First, in FIG. 1A, the carrier signal 1
Is assumed to have a phase transition as shown in FIG. At this time, in the case of the A mode in which the frequency of the local signal 2 is lower than the frequency of the carrier signal 1, the received signal 3 is input to the demodulation device 4 with the same phase transition as in FIG. In the demodulator 4, the phase sampling circuit 5 samples the reception signal 3 using the sampling signal of the sampling signal source 6, and the phase state of the reception signal is represented by 2 bits. The phase difference detection circuit 7 detects the phase transition between the previous symbol and the current symbol using the symbol synchronization signal 8. The correspondence of the data to the phase transition at this time has a relationship as shown in FIG.

In the demodulated data generation circuit 9, in the A mode, the data selection signal (DTSEL) 13 is input and the level thereof is set to "0".
The demodulated data generation circuit 9 shown in (b) is configured. Thereafter, the demodulated parallel output data bits are converted into serial demodulated data 12 in the parallel-serial conversion circuit 10 by the bit synchronization signal 11.

In the case of the B mode in which the frequency of the local signal 2 is higher than the frequency of the carrier signal 1, the received signal 3
Is input to the demodulator 4 with a phase transition as shown in FIG. Therefore, the phase transition when this is degenerated into a four-phase phase modulated signal in the demodulator becomes as shown in FIG. 4 (b). Figure 4
In the case of the phase transition as shown in (b), by setting the level of the data selection signal 13 to "1", the demodulation data generation circuit 9 shown in FIG. 2 (c) is configured and normal demodulation is possible.

The demodulated data generation circuit 9 shown in FIG.
Then, by setting the input level of the data selection signal (DTSEL) to "0" or "1", a logic circuit substantially equivalent to the above-mentioned FIG. 2 (b) and FIG. 2 (c) is formed. Is clear by comparing the demodulated signal input and output shown in Table 1, Table 2 and Table 3. The present invention can thus perform error-free demodulation regardless of whether the local frequency is high or low with respect to the carrier frequency.

[0018]

[Table 1]

[0019]

[Table 2]

[0020]

[Table 3]

[0021]

As described above, the phase-modulated signal demodulation device of the present invention controls the demodulation data generation circuit in correspondence with the level of the carrier frequency of the receiving system to always obtain a normal demodulation output. Therefore, the demodulation data generation circuit can be used as a demodulation data generation circuit having general versatility that can be used regardless of whether the local frequency is high or low with respect to the carrier frequency.

[Brief description of drawings]

FIG. 1 is a diagram showing a demodulation device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a conventional demodulator of a four-phase phase modulation signal.

FIG. 3 is a diagram illustrating phase transition of a 4-phase phase modulation signal.

FIG. 4 is a diagram showing another example for explaining the phase transition of the four-phase modulation signal.

[Explanation of symbols]

1 ... Carrier signal, 2 ... Local signal, 3 ... Received signal, 4 ... Demodulator, 5 ... Phase sampling circuit, 6
... Sampling signal source, 7 ... Phase difference detection circuit, 8 ...
Symbol synchronization signal, 9 ... Demodulation data generation circuit, 10 ...
Parallel-serial conversion circuit, 11 ... bit synchronization signal,
12 ... Demodulated data, 13 ... Data selection signal (DTSE
L).

Claims (1)

[Claims] 1. A phase sampling circuit for a phase modulation signal,
Phase difference detection circuit, demodulation data generation circuit, and parallel-
The frequency of the received signal to be demodulated by including a serial conversion circuit and configuring the demodulated data generation circuit by a logic circuit, applying a data selection signal for inputting the logic output from the outside, and changing the logic of the logic circuit In comparison with the above, the demodulator for phase-modulated signal is configured to obtain the same demodulated data output for the same phase-modulated signal regardless of whether the input local signal frequency is high or low.