JPH11243433A - Radio communication device and its quadature amplitude modulating demodulating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the transmission capacity without deteriorating a transmission quality and to miniaturize a circuit scale and improve a processing speed by enabling mapping and de-mapping processings without using a memory. SOLUTION: In a transmission side mapping circuit 342, Q-channel data D2, D4 and D6 from among digital data D1 to D7 of seven systems are converted into four bits from three bits by a bit number conversion circuit 111a. Then, a bit pattern corresponding to a conversion object of a signal point arrangement is detected from the transmission digital data D1 to D7 after bit number conversion by a conversion signal detection circuit 111b, this detected bit pattern is converted by a signal conversion circuit 111c, in accordance with a specified conversion rule, and is supplied for modulation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to, for example, 2 ^m (m
The present invention relates to an improvement of a quadrature amplitude modulation / demodulation circuit provided in a wireless communication device employing a quadrature amplitude modulation method using a natural number of 2 or more or m = 3, 5, 7...

[0002]

2. Description of the Related Art In recent years, various communication systems have been developed with an increase in communication needs and development of communication technology, and among them, there is a digital microwave radio communication system. This type of system uses, for example, a multi-level quadrature amplitude modulation (multi-level QAM: Quadrature Amplitude) for a carrier composed of microwaves.
Modulation) is used to transmit digital data wirelessly by modulating it. Compared to analog wireless transmission systems and wired digital transmission systems, low-cost and high-quality data transmission is possible.

In a digital microwave radio communication system employing a quadrature amplitude modulation system, a conventional 2 ^{2 m} (m =
(1, 2, 3,...) -Valued QAM signal modulation / demodulation system is used, and among them, 16QAM system and 64QAM system in which the number of I-channel and Q-channel signals are equalized are currently in practical use. Also, with the increase in communication needs in recent years, a study for practical use of a multi-level QAM system with a higher transmission rate has been conducted.

In the modulation / demodulation system of the multi-level QAM system, vector synthesis is performed by orthogonally intersecting two series of I-channel and Q-channel signals. For this reason, in order to prevent the signal point arrangement from changing due to the phase state pulled in on the receiving side, a 2 ^2m (m = 1, 2, 3,...) Value in which the number of signals of the I channel and the Q channel is equal, that is, Quaternary,
A multi-value QAM system that takes 16 values, 256 values,... Will be adopted.

However, the conventional 2 ^2m (m = 1,
In the modulation / demodulation system of the (2, 3,...) Value QAM system, increasing the value of m by 1 increases the transmission capacity.
As shown in FIG. 1, since the amplitude fluctuation width increases, it is necessary to use a high-linearity power amplifier or the like used in a transmission unit or the like, and further, technically solves problems such as transmission quality in wireless transmission. Since many problems must be solved, the transmission capacity cannot be easily increased.

[0006]

As described above, the multi-value QA
In the digital microwave radio communication system using the M system, when the transmission capacity becomes an issue when the shortage of the transmission capacity becomes a problem, the radio transmission is performed by using the multi-level QAM system in which the signal point arrangement is quadrupled. , A problem of transmission quality occurs, and it becomes difficult to realize the problem.

The present invention has been made in view of the above circumstances. It is an object of the present invention to reduce the influence of linearity of a high-frequency power amplifier or the like and to increase the transmission capacity as compared with a conventional device. And a quadrature amplitude modulation / demodulation circuit thereof.

Another object of the present invention is to enable the mapping and demapping circuit to be constituted by a simple circuit such as a general-purpose gate array or a PLD, whereby the circuit scale is reduced as compared with a circuit using a conversion table by a memory. It is an object of the present invention to provide a wireless communication device and a quadrature amplitude modulation / demodulation circuit capable of reducing the size of the device and increasing the conversion speed.

[0009]

In order to achieve the above object, a wireless communication apparatus and a quadrature amplitude modulation circuit according to the present invention convert a signal point arrangement on a two-dimensional phase plane of an m-sequence digital signal. In this mapping circuit, the m-sequence digital signal is divided into an I channel and a Q channel by a sequence number conversion circuit, and one of the channels is arranged to equalize the number of sequences of both channels. The number of sequences is converted, a bit pattern to be converted of the signal point arrangement is detected from the digital signal of the m + 1 sequence output from the number-of-sequence conversion circuit, and the detected bit pattern to be converted is converted into a predetermined conversion format. Convert the pattern according to the rules and output,
In addition, a bit pattern that is not subject to conversion of the signal point arrangement is output as it is without conversion.

Further, the radio communication apparatus and the quadrature amplitude demodulation circuit according to the present invention are provided with a demapping circuit for inversely transforming the signal point arrangement on the two-dimensional phase plane of the demodulated signal to reproduce an m-sequence digital signal, In this demapping circuit, a bit pattern to be converted in signal point arrangement is detected from the demodulated signal, and the detected bit pattern to be converted is subjected to pattern conversion in accordance with a predetermined conversion rule and output. Non-target bit patterns are output without conversion, and the number of I-channel or Q-channel sequences of the output digital signal sequence is converted to output an m-sequence digital signal sequence before mapping. It was done.

That is, according to the present invention, by performing pre-conversion for equalizing the number of signal sequences of the I channel and the Q channel, a simple conversion between the bit pattern before conversion and the bit pattern after conversion of the signal point constellation is performed. Focusing on the point where regularity occurs, the modulation side converts the number of signal sequences, detects the bit pattern to be converted from the converted digital signal sequence, and performs conversion based on the detection result. The target bit pattern is subjected to pattern conversion.
On the demodulation side, a circuit is configured to perform the opposite processing.

Therefore, according to the present invention, 128QA
Despite the M system, the number of signals on the I channel and the Q channel can be equalized, thereby realizing digital microwave radio transmission with large capacity and good transmission quality.

[0013] In addition, mapping and demapping can be realized by converting the number of streams and detecting and converting the bit pattern to be converted, whereby the mapping and demapping circuit can be implemented by a general-purpose gate array, PLD, or the like. It is possible to configure with a simple circuit used. Therefore, the circuit scale can be reduced as compared with a conventional circuit using a conversion table using a memory, and the conversion speed can be increased.

The radio communication apparatus and the quadrature amplitude demodulation circuit thereof according to the present invention may be arranged such that the mapping circuit converts the signal point arrangement of the m-sequence digital signal on a two-dimensional phase plane into a rotationally symmetric code arrangement. It is intended to be implemented. Further, the inverse conversion of the signal point arrangement on the two-dimensional phase plane of the demodulated signal in the demapping circuit is performed on a rotationally symmetric code arrangement.

Normally, in this type of wireless communication apparatus, differential logical operation processing is performed in order to transmit and receive data without error. When performing this differential logic operation, usually,
A rotationally symmetric arrangement code that has the least spread to other streams at the time of a bit error is used. Therefore, by adopting the above-described means, it becomes possible to obtain rotationally symmetric arrangement code data for differential logical operation by one conversion process, thereby simplifying the device configuration.

Further, the radio communication apparatus and the quadrature amplitude demodulation circuit according to the present invention include a receiving means having a capability of receiving a signal modulated by a multi-level quadrature amplitude modulation method having a first modulation multi-level number. An analog / digital conversion means for converting an analog reception signal from the reception means into a plurality of series of digital signals, and a second modulation multilevel number corresponding to the multilevel quadrature amplitude modulation signal to be demodulated (the Designation means for designating a natural number equal to or less than one modulation multi-value number), inversion means for logically inverting the digital signals of the plurality of streams, respectively, and the plurality of inverted streams sent from the inversion means. Out of the digital signal of the multi-level quadrature amplitude modulation signal to be demodulated, a digital signal of a sequence located in the next higher order sequence than the main signal, Selecting means for selecting and outputting based on the second modulation multi-level number, a loop filter receiving a digital signal from the selecting means, integrating the digital signal and providing offset control of the analog / digital converting means; It is characterized by having.

In this manner, the digital signal (referred to as an error signal) of a sequence located in the next higher order sequence than the main signal in the multilevel quadrature amplitude modulation signal to be demodulated is inverted,
By giving this to the analog / digital conversion means via the loop filter, negative feedback can be applied to the offset position adjustment. Further, the designation means can change the modulation multi-level number (the number of signal points) of the multi-level modulation signal to be received as desired by the user, thereby enabling various multi-level modulation signals to be received.

In the case where the analog / digital conversion means corresponds to a DRE (Decision Range Expanded) method, an analog reception signal from the reception means is provided outside the identification area of the analog / digital conversion means. Detecting means for detecting whether or not the signal is present; and, when the detecting means detects that an analog received signal from the receiving means is present outside the identification area, the output of the loop filter at that time is detected. For a predetermined time.

As described above, when a received signal is detected outside the identification range, the offset position can be sufficiently corrected by holding the output of the loop filter at that time, thereby avoiding pseudo-stability. It becomes possible.

The radio communication apparatus according to the present invention and the quadrature amplitude demodulation circuit thereof include a receiving means having a capability of receiving a signal modulated by a multilevel quadrature amplitude modulation method having a first modulation multilevel number. An analog / digital conversion means for converting an analog reception signal from the reception means into a plurality of series of digital signals, and a second modulation multilevel number corresponding to the multilevel quadrature amplitude modulation signal to be demodulated (the A natural number less than or equal to one modulation multi-level number), a digital signal of a series positioned at the lowest order in the multi-level quadrature amplitude modulation signal to be demodulated, and a digital signal positioned at other series. Exclusive OR means for calculating an exclusive OR with each of the digital signals for each stream; and among the operation results sent from the exclusive OR means, the multi-level quadrature amplitude change to be demodulated. Selecting means for selecting and outputting an operation result corresponding to a sequence located in a higher-order sequence next to the main signal in the signal based on the second modulation multi-level number specified by the specifying means; And a loop filter for receiving a signal from the means and integrating the signal to provide AGC (Automatic Gain Control) control of the analog / digital conversion means.

As described above, the digital signal (MS) of the sequence located at the lowest order in the multilevel quadrature amplitude modulation signal
B) and the exclusive OR with the error signal.
By providing this to the analog / digital conversion means via a loop filter, the AGC gain adjustment can be controlled to an optimum value. Further, the designation means can change the modulation multi-level number (the number of signal points) of the multi-level modulation signal to be received as desired by the user, thereby enabling various multi-level modulation signals to be received.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Hereinafter, a first embodiment of a quadrature amplitude modulation / demodulation circuit according to the present invention will be described. In this embodiment, it will be described as an example a quadrature amplitude modulation and demodulation circuit 128 QAM ^{(2 7} value QAM) scheme.

FIG. 1 is a circuit block diagram showing the configuration of the quadrature amplitude modulation circuit in this embodiment. In the figure, transmission digital data D1 to D7 of seven sequences are first input to a signal point arrangement conversion circuit 11. The signal point arrangement conversion circuit 11 includes a mapping circuit 111, an addition logic circuit (SMLOG) 112, and roll-off filters (ROF) 113 and 114 for I and Q channels.

When arranging the transmission digital data D1 to D7 on the two-dimensional phase plane, the mapping circuit 111 converts the arrangement of the signal points so that the I and Q channels have the same arrangement. The addition logic circuit 112
An operation for removing the uncertainty of the phase of the mapping data MI1 to MQ4 output from the mapping circuit 111 is performed. The roll-off filters 113 and 114 perform roll-off shaping on the mapping data MI1 'to MQ4' output from the addition logic circuit 112 to reduce intersymbol interference.

Each of the above-mentioned roll-off filters 113 and 114
Are converted into analog signals by digital / analog converters (D / A) 12 and 13, respectively, and then transmitted through low-pass filters 14 and 15 to a quadrature modulation circuit. 16
Is input to The quadrature modulation circuit 16 outputs a signal obtained by modulating the intermediate frequency signal generated from the local oscillator 19 with the transmission baseband signal. The modulated transmission intermediate frequency signal is amplified by an intermediate frequency amplifier 18 via a low-pass filter 17 and then input to a transmission circuit (not shown).

On the other hand, the quadrature amplitude demodulation circuit is configured as follows. FIG. 2 is a circuit block diagram showing the configuration.
A reception intermediate frequency signal output from a reception circuit (not shown) is input to a quadrature demodulation circuit 24 via a roll-off filter (ROF) 22 and a reception intermediate frequency amplifier 23 after the signal level is adjusted by an automatic gain control amplifier 21. You. The quadrature demodulation circuit 24 demodulates the input received intermediate frequency signal by mixing it with a reference carrier generated from a voltage controlled oscillator (VCO) 241 to output a baseband demodulated signal. The frequency of the reference carrier generated from the VCO 241 is determined by the control circuit (CON
T) and a carrier synchronization circuit comprising a loop filter 33 synchronizes with the reception carrier frequency. Also, 3
1 is a clock recovery circuit.

The I- and Q-channel demodulated signals output from the quadrature demodulation circuit 24 are passed through low-pass filters 25 and 26 and amplifiers 27 and 28, respectively, to analog / digital converters (A / D) 29 and 30. , Where it is converted to a digital signal. The received digital data MI1 'to MQ4' are input to the signal point arrangement conversion circuit 34.

The signal point arrangement conversion circuit 34 includes a difference logic circuit (DIFFLOG) 341 and a demapping circuit 342.
It is composed of The differential logic circuit 341 performs a logical operation for removing the uncertainty of the phase of the input received digital data MI1 'to MQ4'. The demapping circuit 42 performs a conversion process for returning the signal point arrangement on the two-dimensional phase plane of the received digital data MI1 to MQ4 output from the difference logic circuit 341 to a state before mapping. The latter data is output as received digital data D1 to D7.

The mapping circuit 111 and the demapping circuit 342 are constructed as follows. 3 and 4 are circuit diagrams respectively.

First, the mapping circuit 111 includes a bit number conversion circuit 111a, a conversion signal detection circuit 111b, and a signal conversion circuit 111c. Bit number conversion circuit 1
11a is Q channel data D2, D4, D composed of three series of transmission digital data D1 to D7 of seven series.
6 by using the inverter INV to logically invert the three most significant data D2, thereby converting the three series of Q channel data D2, D4 and D6 into the four series of data D
2, D2 //, D4, D6.

The signal conversion circuit 111c, based on the transmission digital data which has been converted into 8 series by the bit number conversion by the bit number conversion circuit 111a, has a first data group D1, D2 in which the most significant bit starts from the I channel. , D3, D
2 /, D5, D4, D7, D6 and a second data group D2, D1, D2 //, in which the most significant bit starts from the Q channel.
D3, D4, D5, D6, and D7 are generated. And
Among them, the first data groups D1, D2, D3, D2 //,
D5, D4, D7, and D6 are directly input to the selection circuit SEL1. On the other hand, the second data groups D2, D1, D2 // D
3, D4, D5, D6, and D7 logically invert the lower second bit D5 of the I channel therein by the inverter INV and input the result to the selection circuit SEL1.

The conversion signal detection circuit 111b is composed of two exclusive OR gates and an AND gate for performing an AND operation on the output of the exclusive OR gate. The I-channel data D1, D3, D5
, A bit pattern representing the conversion target of the signal point arrangement is detected. Here, the signal point constellations to be converted are B1 and B2 as shown in FIG. 5, so the bit patterns representing the conversion targets are “000” and “111”.

When the conversion signal detection circuit 111b detects a bit pattern representing a conversion object, the selection circuit SEL1 outputs the second data group D2, D1, D2.
2 /, D3, D4, D5 /, D6, and D7, and when the bit pattern representing the conversion target is not detected, the first data group D1, D2, D3, D2 is selected.
/, D5, D4, D7, D6 are selected. Then, the data group selected by the selection circuit SEL1 is transmitted to the transmission mapping data MI1, MQ1, MI2, MQ2, MI3,
The modulation is performed as MQ3, MI4, and MQ4.

Next, the demapping circuit 342 includes a conversion signal detection circuit 342a, a signal conversion circuit 342b, and a bit number conversion circuit 342c. The conversion signal detection circuit 342a comprises an exclusive OR gate and an inverter for inverting and outputting the output of the conversion signal detection circuit 342a, and the reception data MI1, MQ1, MI2, MQ2, MI3, MQ
3, a bit pattern representing a conversion target is detected from the data MI1 and MI2 of the MQ4. Here, the signal point arrangement to be converted is represented by B1 ′, B1 as shown in FIG.
2 ′, the bit pattern representing the conversion target is “0”.
0 "and" 11 ".

The signal conversion circuit 342b receives the received data MI1, MQ1, MI2, MQ2, MI3, MQ3, M
I4 and MQ4 are the first data groups MI1, MQ1, MI2, MQ2, and MI1, in which the most significant bit starts from the I channel.
3, MQ3, MI4, MQ4 and a second data group MQ1, MI1, MQ whose most significant bit starts from the Q channel.
2, MI2, MQ3, MI3, MQ4, and MI4. Then, the first data group MI1, MQ1
1, MI2, MQ2, MI3, MQ3, MI4, MQ4
Is input to the selection circuit SEL2 as it is. On the other hand, the second data groups MQ1, MI1, MQ2, MI2, MQ3, MI
3, MQ4 and MI4 connect MQ3 therein to inverter I
After the logic is inverted by NV, it is input to the selection circuit SEL2.

When the conversion signal detection circuit 342a detects a bit pattern representing a conversion object, the selection circuit SEL2 outputs the second data group MQ1, MI
1, MQ2, MI2, MQ3 /, MI3, MQ4, MI
4 is selected and output. On the other hand, when the bit pattern representing the conversion target is not detected, the first data group MI1, MQ1, MI2, MQ2, MI3, MQ3, M
I4 and MQ4 are selected and output.

The bit number conversion circuit 342c deletes the fourth most significant bit of the data group output from the selection circuit SEL2 and replaces the remaining seven bits with the reception digital data D1 to D1.
The data is supplied to a data processing circuit (not shown) as D7.

Next, the operation of the apparatus configured as described above will be described. In the transmitting device, the mapping circuit 111
, The Q-channel data D2, D4, and D6 of the seven series of transmission digital data D1 to D7 are first converted from 3 bits to 4 bits by the bit number conversion circuit 111a. This bit number conversion is performed by logically inverting the most significant data of the Q channel as shown in FIG. 6 and inserting the inverted data into the second most significant bit. And
The transmission digital data that has been converted into eight series by converting the number of bits is input to the conversion signal detection circuit 111b and the signal conversion circuit 111c.

The conversion signal detection circuit 111b detects the bit pattern corresponding to the conversion target of the signal point arrangement by monitoring the upper 3 bits of the I channel data in the above-mentioned eight series of transmission digital data. That is, 12
In the case of the 8QAM system, as shown in FIG. 5, the upper three bits of the I channel data corresponding to the signal point arrangements B1 and B2 to be converted are “000” and “111”. Therefore, the upper 3 bits of the I channel data are “000”.
By monitoring whether it is "111" or not, a bit pattern corresponding to the conversion target of the signal point arrangement can be detected.

The signal conversion circuit 111c rearranges the sequence of the transmission digital data, and uses the one logical inversion inverter INV and the selection circuit SEL1 to select the bit pattern to be converted detected by the conversion signal detection circuit 111b. Is converted according to a predetermined conversion rule. That is,
As shown in FIG. 5, the signal point arrangements B1 and B2 to be converted are represented by B
In order to convert the data into 1 'and B2', as shown in FIG. 6, the I channel has the same value as the Q channel, and the Q channel has the inverted lower second bit of the I channel data. Therefore, if a circuit is configured according to this conversion rule, the signal conversion circuit 111c shown in FIG.
The conversion of the bit pattern corresponding to the signal point arrangement to be converted is performed by this circuit. That is, signal point conversion can be realized with a simple circuit configuration using a gate circuit or the like without using a memory table.

The mapping data MI 1, MQ 1, MI 2, MQ 2, MI 3, MQ which have been subjected to the signal point conversion are
After the phase uncertainty is removed by the addition logic circuit 112 and the roll-off shaping for reducing the inter-symbol interference is performed by the roll-off filter 113, the analog signal is processed by the D / A 12 and 13. Is converted to Then, after being converted into a modulated wave signal of an intermediate frequency by the quadrature modulation circuit 16, it is wirelessly transmitted from a transmission circuit (not shown).

On the other hand, in the receiving apparatus, the level of the received intermediate frequency signal output from the receiving circuit (not shown) is adjusted by the automatic gain control amplifier 21, and then the roll-off filter 2 is turned on.
In 2, roll-off shaping is performed to reduce intersymbol interference, and is further amplified by an intermediate frequency amplifier 23, input to a quadrature demodulation circuit 24, and quadrature demodulated here. The demodulated signals are input to A / Ds 29 and 30 via intermediate frequency filters 25 and 26 and intermediate frequency amplifiers 27 and 28, where they are converted into digital signals. The demodulated digital data is input to the signal point arrangement conversion circuit 23, where an operation for removing the phase uncertainty is first performed by the difference logic circuit 341, and then the demapping circuit 3
42.

In the demapping circuit 342, the input demodulated digital data MI1, MQ1, MI2, MQ
2, MI3, MQ3, MI4, and MQ4 are input to the conversion signal detection circuit 342a and the signal conversion circuit 342b.
The conversion signal detection circuit 342a detects the bit pattern corresponding to the conversion target of the signal point arrangement by monitoring the upper two bits of the Q channel data in the demodulated digital data of the eight sequences. That is, as shown in FIG. 5, the upper two bits of the Q channel data corresponding to the signal point arrangements B1 ′ and B2 ′ to be de-mapped are “0”.
0 "and" 11 ". Therefore, by monitoring whether or not the upper two bits of the Q channel data are “00” and “11”, the bit pattern to be demapped can be detected.

The signal conversion circuit 342b rearranges the sequence of the demodulated digital data, and uses the one logic inverting inverter INV and the selection circuit SEL2 to detect the bits to be de-mapped detected by the conversion signal detection circuit 342a. The pattern is converted according to a predetermined conversion rule. That is, in order to convert the signal point constellations B1 'and B2' to be demapped into the original signal point constellations B1 and B2 as shown in FIG. 5, the Q channel has the same value as the I channel as shown in FIG. For the I channel, the second lower bit of the Q channel data may be inverted. Therefore, if a circuit is configured according to this conversion rule, the signal conversion circuit 342b shown in FIG. 4 is used, and the conversion of the bit pattern corresponding to the signal point arrangement to be converted is performed by this circuit.

That is, also for the demapping circuit 342, signal point conversion can be realized with a simple circuit configuration using a gate circuit and the like without using a memory table, similarly to the mapping circuit 111 described above.

The demodulated digital data of the eight series obtained by signal conversion is deleted by the bit number conversion circuit 342c to form the seven series by removing the upper 2 bits, and then the data processing circuit (not shown) is used as reproduced received digital data. Is input to

As described above, in the present embodiment, the mapping circuit 342 on the transmitting side sets the Q channel data D2 out of the seven series of transmission digital data D1 to D7.
D4 and D6 are converted from 3 bits to 4 bits by the bit number conversion circuit 111a. Then, the conversion signal detection circuit 111
In b, the conversion target of the signal point arrangement, that is, the bit pattern to be mapped is detected from the transmission digital data after the bit number conversion, and the detected bit pattern is subjected to pattern conversion by the signal conversion circuit 111c according to a predetermined conversion rule. For modulation.

Further, in the demapping circuit 342 on the receiving side, the converted signal detection circuit 342a detects a signal point whose arrangement is to be restored from the demodulated digital data, that is, a bit pattern to be demapped. The converted bit pattern is converted by the signal conversion circuit 342b according to a conversion rule reverse to the conversion rule at the time of mapping. The Q of the converted received digital data
The channel data is converted from 4 bits to 3 bits by the bit number conversion circuit 342c to reproduce the 7-series received digital data D1 to D7.

Therefore, according to this embodiment, 128
Although the QAM system is used, the number of signals of the I channel and the Q channel can be equalized, thereby realizing digital microwave radio transmission with large capacity and good transmission quality.

Further, since the mapping and demapping processing is realized by converting the number of streams and detecting and converting the bit pattern to be converted, the mapping and demapping circuit can be implemented by a general-purpose gate array or P-gate.
The circuit can be configured by a simple circuit using an LD or the like. As a result, the circuit scale can be reduced as compared with a conventional circuit using a conversion table using a memory, and the conversion speed can be increased. Can be.

(Second Embodiment) FIGS. 7 and 8 are circuit diagrams showing a mapping circuit and a demapping circuit according to a second embodiment of the present invention.

First, the mapping circuit 111 includes a bit number conversion circuit 111a, a conversion signal detection circuit 111b, and a signal conversion circuit 111c '. The bit number conversion circuit 111a includes seven series of transmission digital data D1 to D7.
Of these, Q channel data D2, D4,
By logically inverting the most significant data D2 of D6 using the inverter INV, the three series of Q channel data D2, D4, and D6 are converted into four series of data D2, D2 //, D4, and D6 that are the same as the I channel. I do.

The signal conversion circuit 111c 'sets the most significant bit to I based on the transmission digital data which has been converted into 8 series by the bit number conversion by the bit number conversion circuit 111a.
First data group D1, D2, D3 starting from channel
D2 //, D5, D4, D7, D6 and the most significant bit is Q
Second data group D2, D1, D2 starting from channel
/, D3, D4, D5, D6, and D7. Then, the first data group D1, D2, D3, D2 among these
/, D5, D4, D7, D6 are directly selected by the selection circuit SEL
Enter 1 On the other hand, the second data groups D2, D1, D2
/, D3, D4, D5, D6, D7 are the upper two bits D1, D3 and the least significant bit D7 of the I channel therein.
Are logically inverted by the inverter INV and input to the selection circuit SEL1.

The conversion signal detection circuit 111b is composed of two exclusive OR gates and an AND gate for performing an AND operation on the output of the exclusive OR gate, and the I channel data D1, D3, D5
, A bit pattern representing the conversion target of the signal point arrangement is detected. Here, the signal point constellations to be converted are B1 and B2 as shown in FIG. 5, so the bit patterns representing the conversion targets are “000” and “111”.

When the conversion signal detection circuit 111b detects a bit pattern representing a conversion target, the selection circuit SEL1 outputs the second data group D2, D1 /,.
Select D2 //, D3 /, D4, D5, D6, D7 /
On the other hand, when the bit pattern representing the conversion object is not detected, the first data group D1, D2, D3, D
2 /, D5, D4, D7, D6 are selected. The data group selected by the selection circuit SEL1 is transmitted to the transmission mapping data MI1, MQ1, MI2, MQ2, MI2.
3, MQ3, MI4, and MQ4 for modulation.

Next, the demapping circuit 342 includes a conversion signal detection circuit 342a, a signal conversion circuit 342b ', and a bit number conversion circuit 342c. The conversion signal detection circuit 342a comprises an exclusive OR gate and an inverter for inverting and outputting the output of the conversion signal detection circuit 342a, and the reception data MI1, MQ1, MI2, MQ2, MI3, MQ
3, a bit pattern representing a conversion target is detected from data MQ1 and MQ2 of MI4 and MQ4. Here, the signal point arrangement to be converted is represented by B1 ′, B1 as shown in FIG.
2 ′, the bit pattern representing the conversion target is “0”.
0 "and" 11 ".

The signal conversion circuit 342b 'receives the received data MI1, MQ1, MI2, MQ2, MI3, MQ3,
MI4, MQ4 are the first data groups MI1, MQ1, MI2, MQ2, M2 whose most significant bits start from the I channel.
I3, MQ3, MI4, and MQ4, and second data groups MQ1, MI1, and MQ whose most significant bits start from the Q channel
2, MI2, MQ3, MI3, MQ4, and MI4. Then, the first data group MI1, MQ1
1, MI2, MQ2, MI3, MQ3, MI4, MQ4
Is input to the selection circuit SEL2 as it is. On the other hand, the second data groups MQ1, MI1, MQ2, MI2, MQ3, MI
3, MQ4, and MI4 are MQ1, MQ2, and MQ therein.
4 are inverted by the inverter INV, and then input to the selection circuit SEL2.

When the conversion signal detection circuit 342a detects a bit pattern representing an object to be converted, the selection circuit SEL2 outputs the second data group MQ1 /, MI
1, MQ2 //, MI2, MQ3, MI3, MQ4 /, M
I4 is selected and output. On the other hand, when the bit pattern representing the conversion object is not detected, the first data group MI1, MQ1, MI2, MQ2, MI3, MQ3,
MI4 and MQ4 are selected and output.

The bit number conversion circuit 342c deletes the fourth most significant bit of the data group output from the selection circuit SEL2 and replaces the remaining seven bits with the reception digital data D1 to D1.
The data is supplied to a data processing circuit (not shown) as D7.

Next, the operation of the apparatus configured as described above will be described. In the transmitting device, the mapping circuit uses Q out of the seven series of transmission digital data D1 to D7.
Channel data D2, D4 and D6 are converted to bit number conversion circuit 1
At 11a, 3 bits are first converted to 4 bits. This bit number conversion is performed by logically inverting the most significant data of the Q channel as shown in FIG. 10 and inserting the inverted data into the second most significant bit. The transmission digital data that has been converted into 8 series by the number of bits is converted into a converted signal detection circuit 111b and a signal conversion circuit 11b.
1c '.

The conversion signal detection circuit 111b detects the bit pattern corresponding to the conversion target of the signal point arrangement by monitoring the upper 4 bits of the I channel data in the above-mentioned eight series of transmission digital data. That is, 12
In the case of the 8QAM system, as shown in FIG. 9, upper three bits of I channel data corresponding to signal point constellations B1 and B2 to be converted are “000” and “111”. Therefore, the upper 3 bits of the I channel data are “000”.
By monitoring whether it is "111" or not, a bit pattern corresponding to the conversion target of the signal point arrangement can be detected.

The signal conversion circuit 111c 'rearranges the sequence of the transmission digital data, and uses the three logical inversion inverters INV and the selection circuit SEL1 to select the conversion target bit detected by the conversion signal detection circuit 111b. The pattern is converted according to a predetermined conversion rule. That is, as shown in FIG.
Is converted to B1 'and B2', as shown in FIG. 10, the I channel has the same value as the Q channel, and the Q channel has the upper two bits and the least significant bit of the I channel data inverted. I just need. Therefore, if a circuit is configured according to this conversion rule, the signal conversion circuit 111c 'shown in FIG. 7 is obtained, and the conversion of the bit pattern corresponding to the signal point arrangement to be converted is performed by this circuit. That is, signal point conversion can be realized with a simple circuit configuration using a gate circuit or the like without using a memory table.

The mapping data MI 1, MQ 1, MI 2, MQ 2, MI 3, MQ which have undergone signal point conversion are
After the phase uncertainty is removed by the addition logic circuit 112 and the roll-off shaping for reducing the inter-symbol interference is performed by the roll-off filter 113, the analog signal is processed by the D / A 12 and 13. Is converted to Then, after being converted into a modulated wave signal of an intermediate frequency by the quadrature modulation circuit 16, it is wirelessly transmitted from a transmission circuit (not shown).

On the other hand, in the receiving apparatus, the level of the received intermediate frequency signal output from the receiving circuit (not shown) is adjusted by the automatic gain control amplifier 21, and then the roll-off filter 2 is turned on.
In 2, roll-off shaping is performed to reduce intersymbol interference, and is further amplified by an intermediate frequency amplifier 23, input to a quadrature demodulation circuit 24, and quadrature demodulated here. The demodulated signals are input to A / Ds 29 and 30 via intermediate frequency filters 25 and 26 and intermediate frequency amplifiers 27 and 28, where they are converted into digital signals. The demodulated digital data is input to the signal point arrangement conversion circuit 23, where an operation for removing the phase uncertainty is first performed by the difference logic circuit 341, and then the demapping circuit 3
42.

In the demapping circuit 342, the input demodulated digital data MI1, MQ1, MI2, MQ
2, MI3, MQ3, MI4, and MQ4 are input to the conversion signal detection circuit 342a and the signal conversion circuit 342b '. The conversion signal detection circuit 342a detects the bit pattern corresponding to the conversion target of the signal point arrangement by monitoring the upper two bits MQ1 and MQ2 of the Q channel data in the eight series of demodulated digital data. That is, signal point arrangements B1 'and B2' to be de-mapped
As shown in FIG. 9, the upper two bits of the Q-channel data corresponding to are "00" and "11". Therefore, by monitoring whether or not the upper two bits of the Q channel data are “00” and “11”, the bit pattern to be demapped can be detected.

In the signal conversion circuit 342b ', the sequence of the demodulated digital data is rearranged, the three inverters INV for logical inversion, and the selection circuit SEL2 select the demapped data detected by the conversion signal detection circuit 342a. The bit pattern is converted according to a predetermined conversion rule.
That is, in order to convert the signal point constellations B1 'and B2' to be demapped into the original signal point constellations B1 and B2 as shown in FIG.
The same value as that of the channel is used, and for the I channel, the upper two bits and the least significant bit of the Q channel data may be inverted. Therefore, if a circuit is configured according to this conversion rule, the signal conversion circuit 342 shown in FIG.
b ′, and this circuit converts the bit pattern corresponding to the signal point arrangement to be converted.

That is, also for the demapping circuit 342, signal point conversion can be realized with a simple circuit configuration using a gate circuit or the like without using a memory table, similarly to the mapping circuit 111 described above.

The demodulated digital data of the eight series obtained by the signal conversion is deleted by the bit number conversion circuit 342c to form the seventh series by removing the upper 4th bit, and then reproduced as digital data processing circuit (not shown). Is input to

As described above, also in the second embodiment, the number of signals of the I channel and the Q channel can be equalized in spite of the 128 QAM system, thereby providing a large-capacity digital transmission with good transmission quality. Microwave wireless transmission can be realized.

The mapping and demapping processing is realized by converting the number of streams, detecting the bit pattern to be converted, and performing the conversion. For this reason, the mapping and demapping circuits can be configured by simple circuits using a general-purpose gate array, PLD, or the like. As a result, the circuit scale can be reduced as compared with a conventional circuit using a conversion table using a memory. And the conversion speed can be increased.

(Third Embodiment) The mapping methods shown in the first and second embodiments are both called conversion on a natural binary code arrangement. In the present embodiment, another type of mapping, that is, a case where mapping is performed on a rotationally symmetric code arrangement will be described.

FIGS. 12 and 13 are circuit diagrams showing a third embodiment of the mapping circuit and the demapping circuit according to the present invention, respectively.

First, the mapping circuit 111 includes a bit number conversion circuit 111a ', a conversion signal detection circuit 111b',
And a signal conversion circuit 111c ''. The bit number conversion circuit 111a 'includes seven series of transmission digital data D
Another series of TTL level H (High) signals are added to 1 to D7 to create eight series of digital data. At this time, Q channel data D2, D4, D
The logical data of the middle data D4 out of 6 is inverted using the inverter INV.

The signal conversion circuit 111c '' converts D3, H, and D4 of the transmission digital data which has been converted into eight streams by the bit number conversion by the bit number conversion circuit 111a '.
/, D5, the first data group D3, H, D5, D
4 / and the second data groups H, D3, D4 /, D5 /. Here, the second data groups H, D3, D4 /,
When generating D5 /, the upper 3 bits D5 of the original I channel are logically inverted by the inverter INV. And
The first data group D3, H, D5, D4 / and the second data group H, D3, D4 /, D5 / are selected by the selection circuit S.
Input to EL3.

The conversion signal detection circuit 111b 'is composed of one inverter INV and two AND gates, and detects a bit pattern representing a signal point arrangement conversion target from the I channel data D3, D5 and H. . here,
When (D3, D5) = (0, 0), it is detected that the signal is a signal to be converted.

When the conversion signal detection circuit 111b 'detects a bit pattern representing a conversion target, the selection circuit SEL3 outputs the second data group H, D3, D
4 /, D5 /, while the first data group D3, H, D5, D4 / is selected when the bit pattern representing the conversion target is not detected. The data group selected by the selection circuit SEL3 is transmitted to the transmission mapping data MI1, MQ1, MI2, MQ2, MI3, M
The modulation is performed as Q3, MI4, and MQ4.

Next, the demapping circuit 342 includes a conversion signal detection circuit 342a ′, a signal conversion circuit 342b ″,
And a bit number conversion circuit 342c '. The conversion signal detection circuit 342a 'includes two AND gates and two inverters.
MQ1, MI2, MQ2, MI3, MQ3, MI4, M
A bit pattern representing a conversion target is detected from MI2, MQ2, and MQ3 of Q4.

The signal conversion circuit 342b "" receives the received data MI1, MQ1, MI2, MQ2, MI3, MQ
3, MI4 and MQ4, MI2, MQ2, MI3
A first data group MI2, MQ2, MI3, MQ3 in which the most significant bit starts from the I channel;
Second data group M whose most significant bit starts from Q channel
Q2, MI2, MQ3 /, MI3 are generated. Here, the second data groups MQ2, MI2, MQ3 /, MI3
Is generated, the upper 3 bits MQ3 of the original Q channel are used.
Is logically inverted by the inverter INV. Then, these first data groups MI2, MQ2, MI3, MQ3
And the second data group MQ2, MI2, MQ3 /, MI3
Are input to the selection circuit SEL4.

When the conversion signal detection circuit 342a 'detects a bit pattern representing a conversion object, the selection circuit SEL4 outputs the second data group MQ2, MI
2, MQ3 /, and MI3 are selected and output. On the other hand, when the bit pattern representing the conversion target is not detected, the first data groups MI2, MQ2, MI3, and MQ3 are selected and output.

The bit number conversion circuit 342c 'deletes the upper 2 bits of the data group output from the selection circuit SEL4, and removes the remaining 3 bits and the received data MI1, M
Q1, MI4 and MQ4 are received digital data D1 to D
7 is supplied to a data processing circuit (not shown).

Next, the operation of the apparatus configured as described above will be described. In the transmitting device, the mapping circuit uses Q out of the seven series of transmission digital data D1 to D7.
Channel data D2, D4 and D6 are converted to bit number conversion circuit 1
At 11a ', 3 bits are first converted to 4 bits. This bit number conversion is performed by inserting H between D2 and D4 and inverting the logic of D4 as shown in FIG. The transmission digital data that has been converted into a total of eight sequences by converting the number of bits is converted into a converted signal detection circuit 111
b 'and the signal conversion circuit 111c'.

The conversion signal detection circuit 111b '
I-channel data D in the transmission digital data of the series
By monitoring D3 and D5, a bit pattern corresponding to the conversion target of the signal point arrangement is detected.

Referring to FIGS. 15 and 16, a description will be given of a method of detecting a conversion-symmetric bit pattern in the present embodiment. FIG. 15 shows 128 QA on a rotationally symmetric code arrangement.
FIG. 3 is a diagram illustrating an example of a signal point arrangement to be converted in the M system. Here, in order to perform mapping with regularity, the points B1 to B4 in FIG. 15 (indicated by white circles in the figure) are set to be conversion symmetric.

FIG. 16 shows a rotationally symmetric code arrangement in 256QAM. In order to avoid complication, only the minimum necessary parts are shown. The arrangement of the signal points by the rotationally symmetric code arrangement is given by replacing the position of a point at a predetermined position in the signal point arrangement obtained by performing the gray conversion on the natural binary code arrangement. In comparison with FIG. 15, the point at the position to be converted at the time of mapping is a point indicated by a shaded portion in the figure.

As is apparent from the figure, the points located in this portion have the characteristic that "the second path is (01) and the third path is (00) or (01)". ing. Therefore, by monitoring the I-channel data D3 and D5 and detecting a case where they both become 0, it is possible to detect a bit pattern corresponding to the conversion target of the signal point arrangement.

In the signal conversion circuit 111c ', the bit pattern to be converted detected by the conversion signal detection circuit 111b' is rearranged by the sequence of the transmission digital data, the inverter INV for logical inversion, and the selection circuit SEL3. It is converted according to a predetermined conversion rule. That is, as shown in FIG. 15, the signal point arrangements B1, B2, B
3, B4 into B1 ', B2', B3 ', B4', the second for the I channel as shown in FIG.
The third path may be replaced with the Q channel, the second and third paths of the Q channel may be replaced with the I channel, and the third path of the Q channel data may be inverted.
Therefore, if a circuit is configured according to this conversion rule,
This becomes the signal conversion circuit 111c '' shown in FIG. 12, and the conversion of the bit pattern corresponding to the signal point arrangement to be converted is performed by this circuit. Thus, also in the present embodiment, signal point conversion can be realized with a simple circuit configuration using a gate circuit or the like without using a memory table.

The mapping data MI 1, MQ 1, MI 2, MQ 2, MI 3, MQ which have undergone signal point conversion are
After the phase uncertainty is removed by the addition logic circuit 112 and the roll-off shaping for reducing the inter-symbol interference is performed by the roll-off filter 113, the analog signal is processed by the D / A 12 and 13. Is converted to Then, after being converted into a modulated wave signal of an intermediate frequency by the quadrature modulation circuit 16, it is wirelessly transmitted from a transmission circuit (not shown).

On the other hand, in the receiving apparatus, the level of the received intermediate frequency signal output from the receiving circuit (not shown) is adjusted by the automatic gain control amplifier 21, and then the roll-off filter 2 is turned on.
In 2, roll-off shaping is performed to reduce intersymbol interference, and is further amplified by an intermediate frequency amplifier 23, input to a quadrature demodulation circuit 24, and quadrature demodulated here. The demodulated signals are input to A / Ds 29 and 30 via intermediate frequency filters 25 and 26 and intermediate frequency amplifiers 27 and 28, where they are converted into digital signals. The demodulated digital data is input to the signal point arrangement conversion circuit 23, where an operation for removing the phase uncertainty is first performed by the difference logic circuit 341, and then the demapping circuit 3
42.

In the demapping circuit 342, the input demodulated digital data MI1, MQ1, MI2, MQ
2, MI3, MQ3, MI4, and MQ4 are input to the conversion signal detection circuit 342a 'and the signal conversion circuit 342b''. The converted signal detecting circuit 342a 'detects the bit pattern corresponding to the conversion target of the signal point arrangement by monitoring MI2, MQ2, and MQ3 of the eight series of demodulated digital data. That is, as shown in FIG. 17, the data corresponding to the signal point constellations B1 ', B2', B3 ', and B4' to be demapped have the upper two bits of "1" for the I channel and "1" for the Q channel. The upper two bits and three bits are “01”.
Therefore, by monitoring whether or not MI2, MQ2, and MQ3 are (101), the bit pattern to be demapped can be detected.

In the signal conversion circuit 342b '', the sequence of the demodulated digital data is rearranged, the inverter INV for logical inversion, and the selection circuit SEL4 select the bit to be de-mapped detected by the conversion signal detection circuit 342a '. The pattern is converted according to a predetermined conversion rule. That is, in order to return the signal point arrangements B1 ', B2', B3 ', B4' to be demapped to the original signal point arrangements B1, B2, B3, B4 as shown in FIG. 15, as shown in FIG. For the Q channel, the second and third paths may be replaced with I channels, for the I channel, the second and third paths may be replaced with Q channels, and the third path of I channel data may be inverted. Therefore, if a circuit is configured in accordance with this conversion rule, the signal conversion circuit 342b '' shown in FIG. 13 is used, and the conversion of the bit pattern corresponding to the signal point arrangement to be converted is performed by this circuit.
Thus, also in the present embodiment, signal point conversion can be realized with a simple circuit configuration using a gate circuit or the like without using a memory table.

That is, also for the demapping circuit 342, signal point conversion can be realized with a simple circuit configuration using a gate circuit or the like without using a memory table, similarly to the mapping circuit 111 described above.

The signal-converted eight-sequence demodulated digital data is deleted by the bit number conversion circuit 342c to remove the fourth most significant bit to form a seven-sequence digital data. Is input to

As described above, even in the third embodiment, the number of signals of the I channel and the Q channel can be equalized in spite of the 128 QAM system, whereby a large capacity and good transmission quality digital signal can be obtained. Microwave wireless transmission can be realized.

The mapping and demapping processing is realized by converting the number of streams, detecting the bit pattern to be converted, and converting the bit pattern. For this reason, the mapping and demapping circuits can be configured by simple circuits using a general-purpose gate array, PLD, or the like. As a result, the circuit scale can be reduced as compared with a conventional circuit using a conversion table using a memory. And the conversion speed can be increased.

Further, as an advantage unique to performing mapping and demapping on a rotationally symmetric code arrangement,
The circuit configuration can be further simplified. That is, as described above, 2 ^m (m = 3, 5, 7
...) In the modulation / demodulation method of the value QAM method, mapping, demapping, summation, and difference operation (differential logic operation) are performed in order to correctly reproduce data regardless of the four types of pull-in phases generated in synchronous detection demodulation. Do.

When performing a differential logic operation, usually, a rotationally symmetric arrangement code which has the least influence on other streams at the time of a bit error is used. However, since the digital / analog converter and the analog / digital converter used in the modulation / demodulation circuit usually perform processing using a natural binary code, it is necessary to convert to a natural binary arrangement after a differential logical operation.

For this reason, in the conventional system in which mapping and demapping are performed on a natural binary code arrangement, FIG.
As shown in the figure, on the transmitting side, on the natural binary code arrangement (Na
Tal) → conversion from natural binary code arrangement to Gray code arrangement → Gray code arrangement to rotationally symmetric code arrangement (QS (Quadrant Symmetric)
: Rotational symmetry)) → Summation operation → Conversion from rotationally symmetric code arrangement to Gray code arrangement → Conversion from Gray code arrangement to natural binary code arrangement
A conversion and modulation processing will be performed. On the receiving side, after demodulation and A / D conversion processing, conversion from gray code arrangement to natural binary code arrangement → conversion from natural binary code arrangement to rotationally symmetric code arrangement → difference operation → rotationally symmetric code arrangement From a gray code arrangement to a natural binary code arrangement → on a natural binary code arrangement (Na
Tal) demapping.

On the other hand, in the configuration according to the present embodiment, FIG.
As shown in (a), the transmitting side can perform the sum calculation processing immediately after the mapping. Also, on the receiving side, demapping can be performed immediately after the difference calculation processing. This is because the mapping and demapping processes are performed on the rotationally symmetric code arrangement, thereby making it possible to reduce the circuit scale, and further contribute to further simplification, miniaturization, and weight reduction of the device.

(Fourth Embodiment) In the first to third embodiments, communication performed at a fixed bit rate (accordingly, a fixed transmission capacity) is assumed. In the present embodiment, an example will be described in which the transmission capacity can be freely changed according to the user's request.

FIG. 19 is a circuit block diagram showing a configuration of a quadrature amplitude demodulation circuit in this embodiment. The quadrature amplitude demodulation circuit in the figure has substantially the same configuration as the quadrature amplitude demodulation circuit shown in FIG. 2, but differs in the control circuit (CONT) and the demapping circuit. The demapping circuit is denoted by reference numeral 361, and the signal point arrangement conversion circuit is denoted by reference numeral 36. The loop filters 332, 33 in FIG.
2 (the loop filter 331 is the same as the reference numeral 33 in FIG. 2), an interface unit (I / F) 40, an operation unit 50, and control signal lines related thereto are not shown in FIG. , Are not newly added in the present embodiment.

The demapping circuit 361 can switch on / off the demapping function according to a given control signal. That is, when the demapping function is turned off, a given data signal is transparently output as it is.

The operation unit 50 responds to the operation of the operator (user) by issuing an instruction to the control circuit 37 via the interface unit 40 and a control signal to the demapping circuit (ie, turning on / off the demapping function). Signal for switching)
give. Further, a control signal for switching a data acquisition position according to the transmission rate is also provided.

The control circuit 37 is configured as follows. FIG. 20 is a block diagram showing the configuration of the main part. That is, the control circuit 37 controls the inverter (INV) 3
71, an exclusive OR gate (EX-OR) 372,
And selectors (SEL) 374, 375.

That is, the eight-channel I-channel and Q-channel data output from the analog / digital converters 29 and 30 in FIG.
FFLOG) 341, and is branched before this and guided to the control circuit 37.

I channel and Q applied to control circuit 37
The channel data is both supplied to the inverter 371 and the exclusive OR gate 372. The inverter 371 logically inverts these 16 series of I-channel and Q-channel data and sends them to the selector 374.

On the other hand, the I-channel and Q-channel data given to exclusive OR gate 372 include the MSB (Most Significant Bit) of each channel, that is, D1
And exclusive OR operation with the lower bits (D2 to D8) are performed (thus, a total of 14 operation results are output for each channel, seven for each channel).
Sent to

Selectors 374 and 375 selectively output data at a position corresponding to a specified bit rate (ie, the value of m in the 2m QAM modulation method) among the given data, for each channel. , AGC (Automatic G) by the offset control and automatic gain control amplifier 21 in the analog / digital converters 29 and 30
ain Control).

Next, the operation of the apparatus configured as described above will be described. It is to be noted that this apparatus is originally provided with a receiving capability of the 256 QAM modulation scheme, and among these, switching of the modulation scheme (for example, 4 QPS
K, 16, 64, 128 QAM, etc.). In the receiving side device, the demodulated digital data output from the A / Ds 29 and 30 are
6 is provided to the differential logic circuit 341 and the control circuit 37. In the difference logic circuit 341, an operation for removing the uncertainty of the phase of the demodulated digital data is performed.
1 to D8 are output.

On the other hand, the control section 37 adjusts the offset amount at the time of data discrimination in the analog / digital converters 29 and 30 and controls the A / A by the automatic gain control amplifier 21.
Processing for adjusting the gain of the GC is performed.

First, the offset control will be described with reference to FIGS. In this case, 64QAM, 16QAM, and 4QPSK are taken as modulation methods.
Description will be made assuming a case where these methods are switched.

FIG. 21 shows a signal point arrangement diagram in a natural binary code arrangement in 64QAM. In FIG. 21, 16
Identification point (LSB: Least Sign) in QAM system
significant bits) correspond to the 16 positions indicated by crosses in the figure. A position indicated by a mark in the figure corresponds to an identification point in the 4QPSK system, and is generally called an MSB. The positions indicated by black circles in the figure correspond to the identification points in the 64QAM system, and these points are called (error signals for 16QAM).

FIG. 22 shows identification points related to the I channel in the 16QAM system. The offset control is to shift the position of each identification point and adjust to the optimum position. In the case of 16QAM, up to the data D1 and D2 of the first and second passes are called a main signal, and the lower bit D3 is called an error signal. In the present embodiment, 16
In the case of QAM, the error signal D3 is logically inverted.

In FIG. 21, the offset control is regarded as positioning the identification point at the center of the error range when performing data identification. For example, an X mark (1
Focusing on (corresponding to 100), the first shaded portion consisting of A, B, C, and D in the figure can be used as the error range.

For example, when the identification point corresponding to the point (1100) is biased to A and B in the figure, the output data by 64QAM is biased to (xxxxxx1) (xx
xxx corresponds to 10100). That is, the third of the Q channel
The path data D3 is biased toward 1. Conversely, the point (11
When the identification point corresponding to (00) is biased to C and D in the figure, the third path data D3 of the Q channel is biased to 0. Similarly, when the identification points are biased toward A and C in the figure, D3 of the I channel is biased to 0, and when the identification points are biased to B and D, the D3 of the I channel is biased to 1.

Therefore, taking advantage of this fact, 0 or 1
By applying negative feedback in order to eliminate the bias toward (in other words, to set the ratio of the number of 0s and 1s (mark rate) to 0.5), it is possible to adjust the discrimination point to a just good position. Become. That is, in the case of 16QAM, the D3 data as an error signal is logically inverted (by the inverter 371), averaged by the loop filter 333 and subjected to offset control, thereby controlling the offset of the analog / digital converters 29 and 30. This can be done automatically.

Next, the AGC control will be described with reference to FIGS. In FIG. 21, AGC control can be understood as controlling the distance of the received signal from the intersection of the I axis and the Q axis to an optimum length. For example, 64Q
In the AM system, the analog / digital converter 2
The identification points 9 and 30 are black circles in the figure.

Now, suppose that the reception was performed by the 64QAM system, and it became necessary to receive the radio wave transmitted by the 16QAM system. Then, it is necessary to perform AGC control on this radio wave to match the position of the received signal with the mark x.

Therefore, in the present embodiment, an exclusive OR circuit 372 is provided to take the EX-OR of the MSB of the received signal and the error signal according to the modulation method, and use this to perform AGC.
It is used for control.

For example, consider a state in which the reception gain for radio waves by 16QAM is lower than the optimum value. In this case, in the area where the first path is (11), the received signal is shifted as indicated by the symbol in the figure (the same applies to other areas). Here, for example, when attention is paid to the point (p), the output data by 64QAM is biased to (111100). That is, the error signal is biased toward (00). Then, the EX-O of the MSB (11) and the error signal (00) is obtained.
If we take R, the result will be biased towards 1. Conversely, if the receiving gain is too high, the EX-OR output will be biased to zero.

Therefore, taking advantage of this fact, the EX-OR
By applying feedback so as to eliminate the bias of the output toward 0 or 1, it is possible to set the reception gain to a just good value. That is, in the case of 16QAM, the MSB
The exclusive OR of the D1 data as D1 and the D3 data as the error signal is obtained (by the exclusive OR gate 372), and this is averaged by the loop filter 332 to obtain A.
By providing for GC control, A
GC control can be automatically performed.

In both the offset control and the AGC control,
Any inversion result and EX according to the reception bit rate
The selector 374, 375 determines whether to select the result of -OR.
Determined by In FIG. 20, each selector has a QA
Although control signals M DATA A and B are given, the selectors 374 and 375 are switched by this. That is, these control signals are transmitted to the operation unit 50.
Is a control signal given by the user's will through Also, bits below the error signal are not required for reception demodulation, so bits below that are discarded.

As described above, in the present embodiment, the control unit 37 has the inverter (INV) 371, the exclusive OR gate (EX-OR) 372, the selector (SEL) 374,
375 are provided. Analog / digital converter 2
Eight-channel I-channel data and Q-channel data from Q30 are supplied to an inverter (INV) 371 and an exclusive OR gate (EX-OR) 372, respectively. Then, according to the reception bit rate, the inversion of the error signal is averaged and applied to the amplifiers 27 and 28 to perform offset control of the analog / digital converters 29 and 30. The AGC control of the analog / digital converters 29 and 30 is performed by averaging the exclusive OR of the MSB and the error signal and applying the average to the automatic gain control amplifier 21.

With this configuration, it is possible to easily change the quadrature modulation method and change the transmission capacity at the request of the user without, for example, replacing the unit. It should be noted that the transmission capacity can be changed in a modulation scheme such as 32QAM or 128QAM based on the same concept, and in that case, the function of the demapping circuit 361 may be turned on.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described with reference to FIG. 19 and FIGS. Here, an A / D converter (reference numeral 2 in FIG. 19) is used.
An embodiment relating to the improvement of the offset control method for (9, 30) will be described. Prior to this, DRE (Decisi
One method of data identification called the “on Range Expanded” method will be described.

[0125] FIG. 24, 128QAM ^{(2 7} value QAM)
FIG. 3 is a diagram illustrating a method of identifying an A / D converter (not denoted by a reference numeral for general purpose) with respect to a signal of a system. In the figure, a demodulated baseband signal indicated by a black circle is normally included in the identification area of the A / D converter, and is identified as data having a correct value. On the other hand, if waveform distortion occurs due to fading or the like, a signal located particularly at the end may exceed the identification area of the A / D converter (overflow), and accurate reception and demodulation cannot be performed.

In order to avoid this, the DRE method has been conventionally applied. FIG. 25 is a diagram illustrating a method of identifying an A / D converter when the DRE method is applied to a signal of the 128 QAM system. That is, the DRE method refers to A / D
The amplitude of the converter input signal is reduced to a fraction of an integer, thereby expanding the apparent identification range of the A / D converter. FIG. 25 shows the case where the amplitude of the A / D converter input signal is set to 1/2 (referred to as DRE1 / 2). By reducing the amplitude of the input signal of the A / D converter to 1/2, the reproduced signal is shifted to the lower bit side by one bit in the second and subsequent paths.

Incidentally, the fact that the offset adjustment of the A / D converter is necessary is the same in this embodiment. Conventionally, an error signal corresponding to the bit rate of the output of the A / D converter is inverted, and feedback control is performed on the basis of the integrated signal so that the mark ratio of the error signal becomes 0.5. . Also, DRE1 / 2
In this case, since the amplitude of the input signal of the A / D converter is １ ／, a region where the converging point of the demodulated baseband signal must not exist (a region indicated by an arrow in FIG. 25: referred to as a prohibited region for convenience). There is. When the focal point enters this area, the offset voltage is controlled in the opposite direction to cope with the problem.

However, in this method, in particular, the multi-valued Q
In the case of the AM system, even if a signal is detected in the forbidden region and the offset voltage is controlled in the reverse direction, the signal point (convergence point)
Is large, the change in the value after integration is small, and it may not be possible to return to the correct offset position. Under such circumstances, for example, if the offset voltage is unstable immediately after the power is turned on, the offset voltage of the demodulated baseband signal may not be stabilized at the position but may be stabilized at an erroneous offset (pseudo-stability). There was a problem. FIG. 26 shows a state where the offset position is pseudo-stable to the positive side.

Therefore, the present embodiment discloses an offset control circuit shown in FIG. This offset control circuit is a control circuit (CO) in the quadrature amplitude demodulation circuit of FIG.
NT) 37, an offset circuit 375, an identification area detection circuit 376, a clock (CLK) inhibition time control circuit 377, and a clock (CLK) inhibition circuit 378.
And a flip-flop (FF) 379.

In FIG. 27, the identification area detection circuit 376
Monitors the prohibited area of FIG. 25 and detects the presence or absence of a signal in this area. When a signal is detected in this prohibited area, the identification area detection circuit 376 outputs a pulse indicating this to C
It is sent to the LK inhibition time control circuit 377. At this time, the offset circuit 375 sends an offset control signal in a correct direction. This offset control signal is latched by a flip-flop (FF) 379 and then applied to a loop filter 333 to be subjected to offset control of the A / D converters 29 and 30.

In the CLK inhibition time control circuit 377, after the above-mentioned pulse is given from the identification area detection circuit 376,
The clock inhibit signal is output for a predetermined time T. That is, if 'H' is active, 'L' is output. This clock inhibition signal is applied to the CLK inhibition circuit 378, and the logical product (AND) of the clock inhibition signal with the clock signal applied from the clock recovery circuit 31 is obtained. Then, the AND of the clock inhibition signal and the clock signal is applied to the flip-flop (FF) 379, and the offset control signal is latched according to this signal.

With this configuration, the supply of the clock signal to the flip-flop (FF) 379 is controlled by C
The operation is stopped only during the clock inhibition time T set by the LK inhibition time control circuit 377. Therefore,
The offset control signal is held for this time T, and the offset control is continuously applied. As a result, the offset control amount can be increased, and it is possible to avoid pseudo-stability and to stabilize with a correct offset voltage.

This will be described in more detail with reference to FIG. The LSB error signal is inverted by the offset circuit 375, and for example, in the 128 QAM system, a logical operation result shown in the identification area of FIG. 28 is output.

Here, when a signal exists in the prohibited area shown by the thick frame in FIG. 28, an “H” level pulse is output from the identification area detection circuit 376. The CLK prohibition time control circuit 377 receiving this pulse outputs the clock prohibition circuit 3 only for a time T corresponding to, for example, 16 clocks.
A prohibition signal (“L” level signal) is given to the signal 78. As a result, the supply of the clock to the flip-flop (FF) 379 is stopped only during the period T.

In this way, when a signal is detected in the region of FIG. 28, the offset control signals applied to A / D converters 29 and 30 via loop filter 333 are forcibly latched to 0, This is held for several clocks (for example, 16 clocks). Similarly, when a signal is detected in the area, the offset control signal is forcibly set to 1
And this is held for several clocks.

Therefore, when a signal is detected in an area that should not exist, the offset control signal is held for a long time (or for a necessary time). As a result, the offset control amount at the time of pseudo pull-in increases, and it becomes possible to pull the received signal into a correct state without generating a pseudo-stable state.

As described above, in the present embodiment, the presence / absence of a signal outside the identification area of the A / D converters 29 and 30 (prohibited area) is detected by the identification area detection circuit 376. , Clock inhibition time control circuit 377
Output the clock inhibit signal. The clock inhibition signal is supplied to the clock inhibition circuit 378 together with the clock signal to obtain a logical product, and the supply of the clock is stopped for a predetermined time. Then, the offset control signal from the offset circuit 375 is latched by the clock signal passed through the clock inhibition circuit 378, and supplied to the A / D converters 29 and 30 via the loop filter 333.

With this configuration, not only is the decrease in the amount of offset control due to the use of the DRE method canceled, but also the amount of offset control can be increased depending on how the clock inhibition period T is set. Therefore, it is possible to prevent the offset position at the time of identifying data in the A / D converter from being stabilized at an erroneous position (voltage), prevent pseudo-stability, and always perform correct reception demodulation. Becomes possible. That is, it is possible to provide a wireless communication device capable of synchronizing with an accurate offset regardless of external influences such as voltage fluctuations due to temperature, power-on, and a pull-in process at the start of reception signal input. .

(Other Embodiments) The present invention is not limited to the above embodiments. For example, in the first and second embodiments, both the mapping circuit and the demapping circuit are configured using gate circuits, but the data before and after the conversion shown in FIGS. 6 and 10 are stored in a memory table. The mapping and demapping may be performed by providing the pre-conversion data to the memory table as an address and reading out the corresponding post-conversion data from the memory table. Good.

In the fourth embodiment, the position of the inverter (INV) 371 in FIG. 20 is not limited to this, and the signal output from the selector 374 may be inverted. Further, the selectors 374 and 375 are not limited to this position. Exclusive OR gate 37
The position and the method of selection may be changed as appropriate according to the type 2 and the number of input terminals.

Also, the bit number conversion circuit of the mapping circuit and the demapping circuit, the circuit configuration of the converted signal detection circuit and the signal conversion circuit, etc. can be variously modified without departing from the gist of the present invention.

[0142]

As described above in detail, according to the present invention, the modulation side performs conversion for equalizing the number of signal sequences between the I channel and the Q channel, and converts the converted digital signal sequence from the converted digital signal sequence. The circuit is configured to detect a target bit pattern and pattern-convert the conversion target bit pattern based on the detection result. On the demodulation side, a circuit is configured to perform the opposite processing.

Therefore, according to the present invention, there is provided a radio communication apparatus and a quadrature amplitude modulation / demodulation circuit thereof which are not affected by the linearity of a high frequency power amplifier or the like and which can increase the transmission capacity as compared with the conventional apparatus. can do.

Further, the mapping and demapping circuit can be constituted by a simple circuit such as a general-purpose gate array or PLD, whereby the circuit size can be reduced as compared with a circuit using a conversion table using a memory.
In addition, it is possible to provide a wireless communication device capable of increasing the conversion speed and a quadrature amplitude modulation / demodulation circuit thereof.

According to the present invention, the conversion and inverse conversion of the signal point arrangement on the two-dimensional phase plane of the m-sequence digital signal in the mapping circuit and the demapping circuit are performed on the rotationally symmetric code arrangement. As described above, this also contributes to simplification of the configuration.

According to the present invention, the transmission capacity can be freely changed according to the user's request.
It is possible to avoid pseudo-stability in the offset control of the analog / digital converter supporting RE.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a first embodiment of a quadrature amplitude modulation circuit according to the present invention.

FIG. 2 is a circuit block diagram showing a first embodiment of a quadrature amplitude demodulation circuit according to the present invention.

FIG. 3 is a circuit configuration diagram of a mapping circuit in the quadrature amplitude modulation circuit shown in FIG.

4 is a circuit configuration diagram of a demapping circuit in the quadrature amplitude demodulation circuit shown in FIG.

FIG. 5 is a diagram for explaining a signal point arrangement conversion operation by the mapping circuit and the demapping circuit shown in FIGS. 3 and 4;

FIG. 6 is a view showing a conversion rule of a signal point arrangement conversion operation by the mapping circuit and the demapping circuit shown in FIGS. 3 and 4;

FIG. 7 is a circuit configuration diagram showing a second embodiment of the mapping circuit according to the present invention.

FIG. 8 is a circuit diagram showing a second embodiment of the demapping circuit according to the present invention.

FIG. 9 is a diagram for explaining a signal point arrangement conversion operation by the mapping circuit and the demapping circuit shown in FIGS. 7 and 8;

FIG. 10 is a view showing a conversion rule of a signal point arrangement conversion operation by the mapping circuit and the demapping circuit shown in FIGS. 7 and 8;

FIG. 11 is a diagram for explaining the amplitude fluctuation width of the 2 ^2m (m = 1, 2, 3,...) QAM system.

FIG. 12 is a circuit configuration diagram showing a third embodiment of the mapping circuit according to the present invention.

FIG. 13 shows a third example of the demapping circuit according to the present invention.
FIG. 2 is a circuit configuration diagram showing the embodiment.

FIG. 14 is a view for explaining how to convert the number of bits in the third embodiment of the present invention.

FIG. 15 is a diagram for explaining a signal point arrangement conversion operation by the mapping circuit and the demapping circuit shown in FIGS. 12 and 13;

FIG. 16 is a diagram showing a rotationally symmetric code arrangement in 256QAM.

FIG. 17 is a diagram showing a conversion rule of a signal point arrangement conversion operation by the mapping circuit and the demapping circuit shown in FIGS. 12 and 13;

FIG. 18 is a system diagram showing a modulation and demodulation method according to a third embodiment of the present invention in comparison with a conventional method.

FIG. 19 is a circuit block diagram showing a configuration of a quadrature amplitude demodulation circuit according to a fourth embodiment of the present invention.

FIG. 20 is a block diagram showing a main part configuration of a control circuit 37 in FIG. 19;

FIG. 21 is a diagram showing a signal point arrangement diagram in a natural binary code arrangement in 64QAM.

FIG. 22 is a diagram showing identification points related to an I channel in 16QAM.

FIG. 23 shows A related to the I channel in the 16QAM system.
FIG. 4 is a diagram for explaining how to perform GC control.

FIG. 24 is a diagram showing a method of identifying an A / D converter for a 128-QAM signal.

FIG. 25 shows a DRE for a signal of the 128 QAM system.
The figure which shows the identification method of A / D converter at the time of applying a method.

FIG. 26 is a diagram showing a state where the offset position is pseudo-stable to the positive side.

FIG. 27 is a block diagram showing a configuration of an offset control circuit according to a fifth embodiment of the present invention.

FIG. 28 is a view for explaining the principle of offset control according to the fifth embodiment of the present invention.

[Explanation of symbols]

11 signal point arrangement conversion circuit 12, 13 digital / analog conversion circuit (D / A) 14, 15 low-pass filter 16 orthogonal modulation circuit 17 intermediate frequency filter 18 intermediate frequency amplifier 19 local oscillator 111 Mapping circuit 112 Addition logic circuit (SUMLOG) 113, 114 Roll-off filter 21 Automatic gain control amplifier 22 Roll-off filter 23 Receive intermediate frequency amplifier 24 Quadrature demodulation circuit 25, 26 Low-pass filter 27, 28 ... Amplifiers 29, 30 ... Analog / digital converters (A / D) 31 ... Clock recovery circuit 32 ... Control circuit (CONT) 33, 331, 332, 333 ... Loop filter 34 ... Signal point arrangement conversion circuit 37 ... Control circuit ( CONT) 371 ... Inverter (INV) 372 ... Exclusive OR gate EX-OR) 374, 375 selector (SEL) 40 interface unit (I / F) 50 operation unit 341 difference logic circuit (DIFFLOG) 342 demapping circuit 111a, 111a ', 342c, 342c' ... number of bits Conversion circuits 111b, 111b ', 342a, 342a' ... conversion signal detection circuits 111c, 342b, 111c ', 111c ", 34
2b ′, 342b ″ Signal conversion circuit 375 Offset circuit 376 Identification area detection circuit 377 Clock (CLK) inhibition time control circuit 378 Clock (CLK) inhibition circuit 379 Flip flop

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Satoshi Hashiya 7-1-1 Nisshin-cho, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Inside Tokyo Electronic Systems Co., Ltd. Tokyo Electronic Systems Co., Ltd.

Claims (14)

[Claims] 1. A quadrature amplitude modulation circuit for modulating an m-sequence (m = 3, 5, 7,...) Digital signal by 2 ^m- value quadrature amplitude modulation, comprising: a signal point on a two-dimensional phase plane of the m-sequence digital signal. A mapping circuit for converting the arrangement to be used for modulation; the mapping circuit distributes the m-sequence digital signal to an I channel and a Q channel, and sets a sequence of one channel to equalize the number of sequences of both channels. A number-of-sequences conversion circuit for converting the number, a detection circuit for detecting a bit pattern to be converted of the signal point arrangement from the m + 1-sequence digital signal output from the number-of-sequences conversion circuit, The converted bit pattern to be converted is subjected to pattern conversion according to a predetermined conversion rule and output,
On the other hand, a quadrature amplitude modulation circuit comprising: a signal point arrangement conversion circuit that outputs a bit pattern that is not to be converted in signal point arrangement without converting it. 2. The mapping circuit according to claim 1, wherein the mapping circuit converts the signal point arrangement of the m-sequence digital signal on a two-dimensional phase plane on a rotationally symmetric code arrangement. Quadrature amplitude modulation circuit. 3. The received signal is 2 ^m (m = 3, 5, 7,...)
A quadrature amplitude demodulation circuit for demodulating an m-sequence digital signal in accordance with a value quadrature amplitude modulation method, comprising a demapping circuit for inversely transforming a signal point arrangement of a demodulated signal on a two-dimensional phase plane to reproduce an m-sequence digital signal. The demapping circuit includes a detection circuit for detecting a conversion target bit pattern from the demodulated signal, and a conversion target bit pattern detected by the detection circuit according to a predetermined conversion rule. A signal point arrangement conversion circuit for converting and outputting a bit pattern which is not subjected to signal point arrangement without conversion, and an I channel or Q channel of a digital signal sequence output from the signal point arrangement conversion circuit. And a sequence number conversion circuit for converting the number of sequences and outputting an m-sequence digital signal sequence before mapping. Quadrature amplitude demodulation circuit of symptoms. 4. The quadrature according to claim 3, wherein the demapping circuit performs an inverse transformation of a signal point arrangement on the two-dimensional phase plane of the demodulated signal on a rotationally symmetric code arrangement. Amplitude demodulation circuit. In the wireless communication apparatus transmits the 2 ^m quadrature amplitude modulates a digital signal by quadrature amplitude modulation circuit 5. The m-sequence (m = 3,5,7, ...), the quadrature amplitude modulation circuit, m A mapping circuit is provided for converting the signal point arrangement on the two-dimensional phase plane of the digital signal of the series for modulation, and the mapping circuit distributes the digital signal of the m series to the I channel and the Q channel. A sequence number conversion circuit for converting the number of sequences of one channel to make the number of channels the same, and a bit pattern to be converted for signal point arrangement based on the m + 1 sequence digital signal output from the number of sequences conversion circuit And a pattern conversion circuit for converting the bit pattern to be converted detected by the detection circuit according to a predetermined conversion rule. And a signal point arrangement conversion circuit for outputting a bit pattern which is not subject to the conversion of the signal point arrangement without conversion. 6. The mapping circuit according to claim 5, wherein the mapping circuit converts the signal point arrangement on the two-dimensional phase plane of the m-sequence digital signal on a rotationally symmetric code arrangement. Wireless communication device. 7. A quadrature amplitude demodulation circuit converts a received signal into 2 ^m (m
= 3,5,7, ...) value In a wireless communication apparatus that demodulates into an m-sequence digital signal in accordance with the quadrature amplitude modulation method, the quadrature amplitude demodulation circuit inversely converts a signal point arrangement of the demodulated signal on a two-dimensional phase plane. A demapping circuit for reproducing an m-sequence digital signal; and a demapping circuit for detecting a bit pattern to be converted in signal point arrangement from the demodulated signal; A signal point arrangement conversion circuit for pattern-converting and outputting a bit pattern to be converted detected according to a predetermined conversion rule, and outputting without converting a bit pattern not to be subjected to signal point arrangement; An m-sequence digital signal system before mapping by converting the number of I-channel or Q-channel sequences of the digital signal sequence output from the conversion circuit. Radio communication apparatus characterized by comprising a sequence number conversion circuit for outputting. 8. The radio according to claim 7, wherein the demapping circuit performs an inverse transformation of a signal point arrangement on the two-dimensional phase plane of the demodulated signal on a rotationally symmetric code arrangement. Communication device. 9. A receiving means capable of receiving a signal modulated by a multi-level quadrature amplitude modulation method having a first modulation multi-level number, an analog receiving signal from the receiving means, Analog-to-digital conversion means for converting into a series of digital signals, and a second modulation multi-level number (a natural number equal to or less than the first modulation multi-level number) corresponding to the multi-level quadrature amplitude modulation signal to be demodulated. Designation means; and inversion means for logically inverting the plurality of series of digital signals, respectively, of the plurality of series of inverted digital signals sent from the inversion means, the multi-level quadrature amplitude to be demodulated. Selecting means for selecting and outputting a digital signal of a sequence located in a higher-order sequence next to the main signal in the modulated signal based on the second modulation multi-level number specified by the specifying means; Given digital signal from the selecting means, a radio communication apparatus characterized by comprising a loop filter to provide by integrating the digital signal to the offset control of the analog / digital converter. 10. When the analog / digital conversion means corresponds to a DRE (Decision Range Expanded) method, an analog reception signal from the reception means is provided outside an identification area of the analog / digital conversion means. Detecting means for detecting whether or not the loop filter is present; and detecting, by the detecting means, that an analog reception signal from the receiving means is present outside the identification area. 10. A wireless communication apparatus according to claim 9, further comprising: holding means for holding for a predetermined time. 11. A receiving means capable of receiving a signal modulated by a multi-level quadrature amplitude modulation method having a first modulation multi-level number, and a second means corresponding to a multi-level quadrature amplitude modulation signal to be demodulated. 2. A quadrature amplitude demodulation circuit used in a wireless communication apparatus comprising: a designation unit for designating a modulation multi-level number (a natural number equal to or less than the first modulation multi-level number) of 2; Analog / digital converting means for converting the received signal into digital signals of a plurality of streams, inverting means for logically inverting the digital signals of the plurality of streams, and the plurality of inverted signals sent from the inverting means, respectively. Out of the series of digital signals, a digital signal of a series located in a higher-order series next to the main signal in the multilevel quadrature amplitude modulation signal to be demodulated is designated by the designation means. Selecting means for selecting and outputting based on the second modulation multi-valued number; a digital signal supplied from the selecting means; a loop for integrating the digital signal and providing an offset control of the analog / digital converting means A quadrature amplitude demodulation circuit comprising a filter. 12. When the analog / digital conversion means corresponds to a DRE (Decision Range Expanded) method, an analog reception signal from the reception means is out of the identification area of the analog / digital conversion means. Detecting means for detecting whether or not the loop filter is present; and detecting, by the detecting means, that an analog reception signal from the receiving means is present outside the identification area. 12. A quadrature amplitude demodulation circuit according to claim 11, further comprising: holding means for holding the signal for a predetermined time. 13. A receiving means capable of receiving a signal modulated by a multi-level quadrature amplitude modulation system having a first modulation multi-level number, a plurality of analog reception signals from the receiving means, Analog-to-digital conversion means for converting into a series of digital signals, and a second modulation multi-level number (a natural number equal to or less than the first modulation multi-level number) corresponding to the multi-level quadrature amplitude modulation signal to be demodulated. Means for specifying the exclusive OR of each of the digital signals of the sequence located in the lowest order sequence in the multilevel quadrature amplitude modulation signal to be demodulated and the digital signals located in the other sequences for each sequence. Exclusive OR means for performing an operation, and of operation results transmitted from the exclusive OR means,
The operation result corresponding to the sequence located in the next higher-order sequence of the main signal in the multilevel quadrature amplitude modulation signal to be demodulated,
Selecting means for selecting and outputting based on the second modulation multi-level number specified by the specifying means; receiving a signal from the selecting means, integrating the signal and AGC of the analog / digital converting means (Autom
and a loop filter for performing atic gain control. 14. A receiving means capable of receiving a signal modulated by a multi-level quadrature amplitude modulation method having a first modulation multi-level number, and a receiving means corresponding to a multi-level quadrature amplitude modulation signal to be demodulated. 2. A quadrature amplitude demodulation circuit used in a wireless communication apparatus comprising: a designation unit for designating a modulation multi-level number (a natural number equal to or less than the first modulation multi-level number) of 2; Analog-to-digital conversion means for converting the received signal into a plurality of series of digital signals; a series of digital signals positioned at the lowest order in the multi-level quadrature amplitude modulation signal to be demodulated; Exclusive OR means for calculating an exclusive OR with each of the located digital signals for each sequence; and among operation results sent from the exclusive OR means,
The operation result corresponding to the sequence located in the next higher-order sequence of the main signal in the multilevel quadrature amplitude modulation signal to be demodulated,
Selecting means for selecting and outputting based on the second modulation multi-level number specified by the specifying means; receiving a signal from the selecting means, integrating the signal and AGC of the analog / digital converting means (Autom
a quadrature amplitude demodulation circuit comprising: a loop filter for performing atic gain control.