JP2992851B2 - Phase modulation signal demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase modulation signal demodulation device used for a digital transmission device in wireless communication or the like.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a conventional 4 / π-shifted QPSK signal (hereinafter, referred to as a four-phase modulated signal) demodulator, and FIG. 2A is a schematic block diagram.

In FIG. 2A, 1 is a carrier signal,
2 is a local signal, 3 is a received signal, 4 is a demodulation device, and a phase sampling circuit 5 that performs sampling operation by a sampling signal source 6, a phase difference for detecting a phase transition between a previous symbol and a current symbol using a symbol synchronization signal 8. A detection circuit 7, a demodulation data generation circuit 9 for demodulating data by a phase transition from the phase difference detection circuit, and a parallel-serial conversion circuit 10 for converting 2-bit parallel data into serial demodulation data 12 using a bit synchronization signal 11.
It consists of.

Here, when the frequency of the local signal 2 is lower than the frequency of the carrier signal (hereinafter, referred to as A mode).
On the other hand, when the demodulation data generation circuit 9 is high (hereinafter referred to as B mode), it is necessary for the demodulation data generation circuit 9 to prepare the logic circuits shown in FIGS. 2B and 2C.

FIGS. 3 (a) and 4 (a) show the state of the phase transition in the received signal 3 in the A and B modes, and the state of the phase transition in the phase sampling circuit 5 for this phase transition. 3 (b) and 4 (b). In addition , FIG.
The state of the phase transition in the phase sampling circuit 5 and the MSB and LS output signals of the phase difference detection circuit 7 shown in FIG.
Table 1 and Table 2 show the relationship with B.

First, it is assumed that the carrier signal 1 makes a phase transition as shown in FIG. At this time A mode
In the case of (when the frequency of the local signal 2 is lower than the frequency of the carrier signal 1), the received signal 3 is input to the demodulation device 4 with the same phase transition as in FIG. In this demodulation device 4, a sampling signal source 6 is provided by a phase sampling circuit 5.
The received signal 3 is sampled by using the sampling signal from, and the phase state of the received signal 3 is represented by 2 bits. The phase difference detection circuit 7 detects the phase transition between the previous symbol and the current symbol (FIG. 3B) using the symbol synchronization signal 8. Here, the relationship between the phase transition of FIG. 3B and the MSB and LSB output signals of the phase difference detection circuit 7 is defined as shown in Table 1. That is, the phase difference detection circuit 7 is configured as shown in FIG.
Is the phase transition from the first quadrant to the first quadrant.
(Indicating character 0) is (MSB, LSB) = (0, 0) in the first quadrant
(MSB, LSB)
= (0,1), phase transition from the first quadrant to the third quadrant
From (MSB, LSB) = (1, 0), from the first quadrant to the second quadrant
(MSB, LSB) = (1, 1)
It shall be encoded. The data is demodulated by the demodulation data generation circuit 9 based on the phase transition. What
In the case of the A mode, the frequency of the carrier signal 1 is set to f _C ,
The frequency of the local signal 2 is f _LL and the frequency of the received signal 3 is
f _R , the frequency of the sampling signal source 6 is f _L2 ,
Assuming that the modulation speed of the signal is f _S ,
And

F _C = f _LL + f _R , f _R = f _L2 −f _S × {(π / 4) / (2π)}

In this case, the demodulated data generation circuit 9 (FIG. 2)
(B)) outputs 2-bit parallel data M and L as shown in Table 1 with respect to the input signals MSB and LSB. The parallel-serial conversion circuit 10 converts 2-bit parallel data M and L into serial demodulated data 12 using a bit synchronization signal 11.

[0008]

As described above, conventionally, in the case of the A mode in which the frequency of the local signal 2 is lower than the frequency of the carrier signal 1, the demodulation operation is performed as described above. Is a phase transition as shown in FIG. 3A, and in the case of the B mode in which the frequency of the local signal 2 is higher than the frequency of the carrier signal 1, the phase transition of the reception signal 3 applied to the demodulation device 4 is as shown in FIG. As shown in FIG. 4A, the rotation direction of the phase is reversed. Accordingly, when the demodulation device 4 degenerates the signal into a four-phase modulated signal, the result becomes as shown in FIG. Therefore, the configuration of the demodulation data generation circuit 9, remains the same as A mode FIG. 2 (b), a problem that erroneous demodulation data M 2-bit parallel as shown in Table 2, the L . In the case of the B mode, the carrier signal
The frequency of 1 is f _C , the frequency of local signal 2 is f _LH , reception
The frequency of the signal 3 is f _R , the frequency of the sampling signal source 6
_Is f _L2 and the modulation speed of the modulated signal is f _S ,
It is assumed that there is a relationship.

F _C = f _LH −f _R , f _R = f _L2 −f _S × {(π / 4) / (2π)}

This problem can be solved by a demodulation data generation circuit having a configuration in which the input signal MSB is used as it is as the output signal M as shown in FIG. 2C, for example. In addition, a demodulation data generation circuit must be configured, and the problem that the demodulation device is not versatile and the number of devices increases increases.

An object of the present invention is to solve the problem of erroneous demodulation of a demodulation data generation circuit in the conventional phase modulation signal demodulation apparatus described above, and to provide a phase modulation signal demodulation apparatus having general versatility.

[0011]

According to the present invention, a demodulation data generation circuit included in a phase modulation signal demodulation device is constituted by a logic circuit, and a control signal is externally input to the logic circuit, and the frequency of the local signal is controlled by a carrier. by changing the logical form in the case when a high relative frequency and low signals, even when the height relationship between the frequency of the carrier signal of the local signal either to obtain a normal demodulated output configuration Becomes

[0012]

According to the present invention, a local signal with respect to the frequency of the carrier signal in the reception system of the demodulator of the phase-modulated signal
No. demodulated data generation circuit in correspondence with the high and low frequency is simply constructed of, frequency of the local signal and the carrier signal
Independently, one demodulated data generation circuit becomes available high and low.

[0013]

1 shows a demodulator for a four-phase modulated signal according to an embodiment of the present invention. FIG. 1A is a block diagram of the demodulator, and FIG. 1B is a block diagram of FIG. A demodulation data generation circuit 13 in FIG. 1A is a data selection signal (DTSEL) applied to the demodulation data generation circuit 9. Table 3 shows the phase transitions ($ 0, $ 0 '~) according to this embodiment.
1) and the input / output relationship of the logic circuit of FIG.

First, in FIG. 1A, it is assumed that the carrier signal 1 has a phase transition as shown in FIG. 3A. At this time, in the case of the A mode in which the frequency of the local signal 2 is lower than the frequency of the carrier signal 1, the received signal 3 is as shown in FIG.
Is input to the demodulation device 4 with the same phase transition as. Demodulator 4
In the above, the received signal 3 is sampled by the phase sampling circuit 5 using the sampling signal of the sampling signal source 6, and the phase state of the received signal is represented by 2 bits.
The phase difference detection circuit 7 detects a phase transition between the previous symbol and the current symbol using the symbol synchronization signal 8. The correspondence of the data to the phase transition at this time has a relationship as shown in FIG.

In the A mode, the demodulation data generation circuit 9 inputs a data selection signal (DTSEL) 13 and sets its level to "0", thereby, for example, the demodulation shown in FIG. The data generation circuit 9 is configured.
Thereafter, the demodulated parallel output data bits are converted by the bit synchronization signal 11 into the parallel-serial conversion circuit 1.
At 0, it is converted to serial demodulated data 12.

When the frequency of the local signal 2 is higher than the frequency of the carrier signal 1 in the B mode, the reception signal 3
Is input to the demodulation device 4 with a phase transition as shown in FIG. Therefore, the phase transition when this is degenerated into a four-phase modulated signal in the demodulator is as shown in FIG. In the case of a phase transition as shown in FIG.
Is set to "1", the demodulation data generation circuit 9 shown in FIG. 2C is formed, and normal demodulation can be performed.

The demodulated data generation circuit 9 shown in FIG.
By setting the input level of the data selection signal (DTSEL) 13 to "0" or "1", a logic circuit substantially equivalent to that of FIGS. 2B and 2C is formed. This is apparent from a comparison between the demodulated signal input and output shown in Tables 1, 2 and 3. The present invention is thus a local signal
Error-free demodulation can be performed irrespective of the frequency of the carrier signal .

[0018]

[Table 1]

[0019]

[Table 2]

[0020]

[Table 3]

[0021]

As described above, the phase modulation signal demodulation apparatus of the present invention controls the demodulation data generation circuit in accordance with the level of the frequency of the local signal with respect to the frequency of the carrier signal in the receiving system, and always operates normally. A demodulated data generation circuit which can be used regardless of the level of the frequency of the local signal with respect to the carrier signal can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a demodulation device according to one embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a conventional four-phase phase modulation signal demodulation device.

FIG. 3 is a diagram illustrating a phase transition of a four-phase modulation signal.

FIG. 4 is a diagram showing another example for explaining the phase transition of a four-phase modulation signal.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Carrier signal, 2 ... Local signal, 3 ... Received signal, 4 ... Demodulation device, 5 ... Phase sampling circuit, 6
... Sampling signal source, 7 ... Phase difference detection circuit, 8 ...
Symbol synchronization signal, 9 ... demodulation data generation circuit, 10
... Parallel-serial conversion circuit, 11 ... Bit synchronization signal, 12 ... Demodulation data, 13 ... Data selection signal (D
TSEL).

Claims (1)

(57) [Claims] 1. A phase sampling circuit for a phase modulation signal,
Phase difference detection circuit, demodulation data generation circuit, and parallel
A serial conversion circuit, and constitute the demodulated data generation circuit by a logic circuit, the phase sampling times
Data indicating the phase state of the received signal to be demodulated by the channel
The phase difference detection circuit detects a phase transition and detects the phase difference.
Of the data selection signal input from outside
By the demodulation data generation circuit which is changed by application,
Compared to the frequency of the carrier signal of the received signal, or the frequency of the input local signal high, the phase modulation signal, wherein the benzalkonium get the same demodulated data output for the same phase-modulated signal regardless of whether the lower Demodulator.