JPH05152503A - Semiconductor chip double-sided mounting lead frame - Google Patents
Semiconductor chip double-sided mounting lead frameInfo
- Publication number
- JPH05152503A JPH05152503A JP3314694A JP31469491A JPH05152503A JP H05152503 A JPH05152503 A JP H05152503A JP 3314694 A JP3314694 A JP 3314694A JP 31469491 A JP31469491 A JP 31469491A JP H05152503 A JPH05152503 A JP H05152503A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- lead frame
- mounting
- island
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、アイランド部の両面に
半導体チップを搭載する形式の半導体チップ両面搭載用
リードフレームに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip double-sided mounting lead frame in which semiconductor chips are mounted on both sides of an island portion.
【０００２】[0002]
【従来の技術】従来、アイランド部、該アイランド部外
周に離間対向するインナーリード部、インナーリード部
外側にアウターリード部を備えた鉄−ニッケル合金製の
パターンエッチングされた薄板状のリードフレームにお
いて、そのアイランド部に、半導体チップを搭載して、
該半導体とリードフリームに半導体を実装する場合は、
アイランド部の片面にのみ半導体を搭載していた。2. Description of the Related Art Conventionally, a pattern-etched thin plate-shaped lead frame made of an iron-nickel alloy having an island portion, an inner lead portion spaced apart from and facing the outer periphery of the island portion, and an outer lead portion outside the inner lead portion, A semiconductor chip is mounted on the island part,
When mounting a semiconductor on the semiconductor and the lead-freem,
The semiconductor was mounted only on one side of the island.
【０００３】[0003]
【発明が解決しようとする課題】上記のように片面のみ
に半導体を搭載する従来の方式では、搭載する半導体チ
ップ個数分の搭載スペースを必要としていた。本発明
は、２個乃至は複数個の半導体チップを、少スペースの
アイランド部にコンパクトに搭載することを目的とする
ものである。As described above, the conventional method of mounting a semiconductor on only one surface requires a mounting space for the number of mounted semiconductor chips. An object of the present invention is to compactly mount two or more semiconductor chips on an island portion having a small space.
【０００４】[0004]
【課題を解決するための手段】本発明は、アイランド部
１、インナーリード部２、アウターリード部３を備え、
該アイランド部の両面に半導体チップを搭載する形式の
半導体チップ両面搭載用リードフレームにおいて、アイ
ランド部１外周に離間対向する複数本の各々インナーリ
ード部２は、アイランド部１の外周に近接する長端子部
２２と、該長端子部２２より短い短端子部２３とを備え
ていることを特徴とする半導体チップ両面搭載用リード
フレームである。The present invention comprises an island portion 1, an inner lead portion 2 and an outer lead portion 3,
In a semiconductor chip double-sided mounting lead frame of the type in which semiconductor chips are mounted on both sides of the island portion, a plurality of inner lead portions 2 facing each other on the outer periphery of the island portion 1 are long terminals close to the outer periphery of the island portion 1. A lead frame for mounting on both sides of a semiconductor chip, comprising a portion 22 and a short terminal portion 23 shorter than the long terminal portion 22.
【０００５】[0005]
【実施例】本発明を、実施例に従って詳細に説明する。
図１は、本発明の半導体チップ両面搭載用リードフレー
ムＡの全体平面図であり、単位リードフレームＲを複数
単位横方向に、カッティング線Ｃを介して一体に連設
（多面付け）したものである。EXAMPLES The present invention will be described in detail with reference to examples.
FIG. 1 is an overall plan view of a semiconductor chip double-sided mounting lead frame A according to the present invention, in which a plurality of unit lead frames R are integrally connected in a row in a lateral direction through a cutting line C (multi-face attachment). is there.
【０００６】上記各単位リードフレームＲには、その中
央部に、半導体チップを搭載するためのアイランド部１
と、該アイランド部１の外周に向かって対向する複数本
のインナーリード部２と、該インナーリード部２の延長
方向に前記アイランド部に対して外側方向に向かうアウ
ターリード部３とを備えるものである。In each of the unit lead frames R, an island portion 1 for mounting a semiconductor chip is provided at the center thereof.
And a plurality of inner lead portions 2 facing each other toward the outer periphery of the island portion 1, and an outer lead portion 3 extending in an extension direction of the inner lead portion 2 toward the outer side of the island portion. is there.
【０００７】本発明においては、アイランド部１方向に
リードフレーム内側に向かうインナーリード部２の互い
に隣設する先端部２１を、先端部と短い先端部とに交互
に配列して長端子部２２と短端子部２３を設けたもので
ある。In the present invention, the leading end portions 21 of the inner lead portions 2 facing the inner side of the lead frame in the direction of the island portion 1 and adjacent to each other are alternately arranged into the leading end portion and the short leading end portion and the long terminal portion 22. The short terminal portion 23 is provided.
【０００８】図２は、本発明の半導体チップ両面搭載リ
ードフレームＡにおける１単位の半導体チップ両面搭載
リードフレームＲのＬ−Ｌ断面図である。アイランド部
１の両面（表裏）には、それぞれ半導体チップＤ1 ，Ｄ
2がエポキシ樹脂などの接合樹脂、半田金属など接合部
材によって接合されて搭載されている。FIG. 2 is a sectional view of a lead frame A for mounting both sides of a semiconductor chip of the present invention, taken along line LL of a lead frame R for mounting both sides of a semiconductor chip. The semiconductor chips D 1 and D are provided on both sides (front and back) of the island portion 1, respectively.
2 is mounted by bonding with a bonding resin such as epoxy resin or a solder metal.
【０００９】インナーリード部２におけるその先端部２
１の長端子部２２上面には、ボンディングワイヤ（金
線）が容易に接合可能なように、金メッキ層２２ａが施
されている。又、短端子部２３下面には、同様に、金メ
ッキ層２３ａが施されている。The tip portion 2 of the inner lead portion 2
On the upper surface of the long terminal portion 22 of No. 1, a gold plating layer 22a is applied so that a bonding wire (gold wire) can be easily joined. Similarly, a gold plating layer 23a is applied to the lower surface of the short terminal portion 23.
【００１０】図３は、本発明の１単位の半導体チップ両
面搭載リードフレームＲのアイランド部１の上面（表
面）に搭載した、一方側の半導体チップＤ1 の電極端子
部１１は、ボンディングワイヤＷによって長端子部２２
の金メッキ層２２ａとボンディングされる。FIG. 3 shows the bonding wire W for the electrode terminal portion 11 of the semiconductor chip D 1 on one side mounted on the upper surface (front surface) of the island portion 1 of the lead frame R for mounting the semiconductor chip on both sides of the present invention. By the long terminal portion 22
Is bonded to the gold plating layer 22a.
【００１１】一方、該アイランド部１の下面（裏面）に
搭載した、他方側の半導体チップＤ 2 の電極端子部１２
は、ボンディングワイヤＷによって短端子部２３の金メ
ッキ層２３ａとボンディングされる。On the other hand, on the lower surface (back surface) of the island portion 1,
The mounted semiconductor chip D on the other side 2Electrode terminal part 12
The bonding wire W is used to
It is bonded to the kick layer 23a.
【００１２】図３におけるワイヤボンディングにおいて
は、インナーリード２の各先端部２１は、かなり高密度
（超多ピンに対応するような密度）に設定された線数で
配列されており、又、各先端部２１は、その上面（表
面）にボンディングする先端部２１と、下面（裏面）に
ボンディングする先端部２１とにそれぞれ仕分けてボン
ディングする必要がある。In the wire bonding shown in FIG. 3, the respective tip portions 21 of the inner leads 2 are arranged with the number of wires set to a considerably high density (density corresponding to an ultra-high pin count), and It is necessary to separately bond the tip portion 21 to the tip portion 21 to be bonded to the upper surface (front surface) and the tip portion 21 to be bonded to the lower surface (back surface).
【００１３】本発明の半導体チップ両面搭載用リードフ
レームＲの表裏に対して、図３に示すようなボンディン
グをする場合には、先ず、リードフレームＲの上面（表
面）側を全部ボンディングした後に、下面（裏面）側を
ボンディングすることが行われる。In the case of performing the bonding as shown in FIG. 3 on the front and back of the semiconductor chip double-sided mounting lead frame R of the present invention, first, all the upper surface (front surface) side of the lead frame R is bonded, Bonding of the lower surface (back surface) side is performed.
【００１４】その場合、上面側をボンディングする時は
それと相対する下面側を支持台（又は支持部材、支持治
具）などによって平坦に支持し、一方、下面側をボンデ
ィングする時は、上面側を支持台（又は支持部材、支持
治具）などによって支持することによって、ワイヤボン
ディング手段のボンディング作動が円滑にできるように
する必要がある。In this case, when the upper surface side is bonded, the lower surface side opposite thereto is supported flat by a support (or a supporting member, a supporting jig) or the like, while the lower surface side is bonded, the upper surface side is supported. It is necessary to make the bonding operation of the wire bonding means smooth by supporting it by a support (or a support member, a support jig) or the like.
【００１５】図４（ａ），（ｂ）は、本発明の半導体チ
ップ両面搭載リードフレームＲのアイランド部１の両面
に搭載されたそれぞれ半導体チップＤ1 ，Ｄ2 に、ワイ
ヤボンディングする場合の一例を説明するＬ−Ｌ側断面
図であり、図４（ａ）、前記リードフレームＲのインナ
ーリード部２における先端部２１下面（裏面）側及びア
イランド部１の下面（裏面）側を少なくともアイランド
部１の下面に搭載した半導体チップＤ2 が陥入できる凹
部２５ａと、インナーリード部２における先端部２１の
少なくとも長端子部２２下面側を平坦に支持する支持台
２５ｂ，２５ｂを備える支持治具２５によって支持し
て、ワイヤボンディング手段（図示せず）によって、長
端子部２２上面と、アイランド部１の上面に搭載した半
導体Ｄ1 上面とをワイヤＷによってボンディングする。FIGS. 4A and 4B show an example of wire bonding to the semiconductor chips D 1 and D 2 mounted on both sides of the island portion 1 of the semiconductor chip double-sided mounting lead frame R of the present invention. 4A is a sectional view taken along line L-L of FIG. 4A, in which at least the island portion is formed on the lower surface (back surface) side of the tip portion 21 of the inner lead portion 2 of the lead frame R and the lower surface (back surface) side of the island portion 1. 1. A supporting jig 25 including a recess 25a into which the semiconductor chip D 2 mounted on the lower surface of 1 and a supporting base 25b, 25b for flatly supporting at least the lower terminal side of the long terminal portion 22 of the tip portion 21 of the inner lead portion 2 can be provided. supported by the wire bonding means (not shown), and a long terminal portion 22 upper surface, and a semiconductor D 1 top mounted on the upper surface of the island portion 1 Wye Bonding by W.
【００１６】次に、図４（ｂ）に示すように、前記ワイ
ヤボンディングされた半導体チップＤ1 搭載側（図４
（ｂ）に示す図面における下側）より、該半導体チップ
Ｄ1 にボンディングされたワイヤＷを回避して、該チッ
プＤ1 の少なくとも中央部を支持する支持台２６ｃと、
短端子部２３の半導体チップＤ1 搭載側を支持する支持
台２６ｂ，２６ｂを備え、少なくとも前記半導体チップ
Ｄ1 と長端子部２２ａとの間をボンディングしたワイヤ
Ｗを回避するための凹部２６ａ，２６ａを備える支持治
具２６によって、前記半導体チップ両面搭載リードフレ
ームＲを支持して、ワイヤボンディング手段（図示せ
ず）によって、短端子部２３の半導体チップＤ2 搭載側
と、アイランド部１に搭載した半導体チップＤ2 とをワ
イヤＷによってボンディングするものである。Next, as shown in FIG. 4B, the wire-bonded semiconductor chip D 1 mounting side (see FIG.
From the bottom side in the drawing shown in (b)), a support base 26c for supporting the wire W bonded to the semiconductor chip D 1 and supporting at least the central portion of the chip D 1 ;
Supports 26b and 26b for supporting the semiconductor chip D 1 mounting side of the short terminal portion 23 are provided, and recesses 26a and 26a for avoiding at least the wire W bonded between the semiconductor chip D 1 and the long terminal portion 22a are provided. The semiconductor chip double-sided mounting lead frame R is supported by the supporting jig 26 including the semiconductor chip D 2 mounting side of the short terminal portion 23 and the island portion 1 by wire bonding means (not shown). The semiconductor chip D 2 is bonded by the wire W.
【００１７】なお、前記支持治具２５，２６は、前記ワ
イヤボンディング手段（図示せず）に対して適宜方向
（前記支持台の水平面内において縦横方向、及び水平面
に対して垂直方向に自在に適宜駆動手段（サーボモータ
ー、パルスモーターなど電動モーター、あるいはエアー
シリンダーなど）によって移動動作可能にすることは可
能である。The support jigs 25 and 26 are freely movable in appropriate directions with respect to the wire bonding means (not shown) (vertically and horizontally in the horizontal plane of the support base, and vertically in the horizontal plane). It is possible to make it movable by a driving means (an electric motor such as a servo motor or a pulse motor, or an air cylinder).
【００１８】又、本発明においては、半導体チップ両面
搭載用リードフレームＲのアイランド部１の表裏にそれ
ぞれ搭載する半導体チップＤ（Ｄ1 ，Ｄ2 ）は、表裏同
一の半導体チップ、若しくは異なる半導体チップのいず
れでもよく、又、搭載する半導体チップＤの個数は、ア
イランド部１の一方面（例えば表面）側及び他方面（例
えば裏面）側に１個乃至複数個搭載するようにしてもよ
い。Further, in the present invention, the semiconductor chips D (D 1 , D 2 ) mounted on the front and back of the island portion 1 of the semiconductor chip double-sided mounting lead frame R are the same semiconductor chip on the front and back or different semiconductor chips. Any one of them may be mounted, and one or more semiconductor chips D may be mounted on one side (for example, front surface) side and the other side (for example, rear surface) side of the island portion 1.
【００１９】[0019]
【作用】本発明は、半導体チップ両面搭載リードフレー
ムにおけるインナーリード先端部を、一方面（例えば上
面）に搭載する半導体チップに対してボンディングされ
る先端部と、他方面（例えば下面）に搭載する半導体チ
ップに対してボンディングされる先端部とのいずれかに
それぞれ仕分けされる長端子部と短端子部とを、必要に
応じて交互に配列して設けたので、長端子部又は短端子
部のいずれか一方のインナーリード端子部に最初にボン
ディングされたワイヤが変形しないように回避して、他
方のインナーリード端子部を支持しながら、該他方のイ
ンナーリード端子部と半導体チップとをワイヤボンディ
ングすることができるものである。According to the present invention, the tip end portion of the inner lead in the semiconductor chip double-sided mounting lead frame is mounted on the tip portion to be bonded to the semiconductor chip mounted on one surface (for example, the upper surface) and the other surface (for example, the lower surface). Since the long terminal portions and the short terminal portions, which are respectively sorted to either the tip portion to be bonded to the semiconductor chip, are arranged alternately as needed, the long terminal portion or the short terminal portion The wire first bonded to one of the inner lead terminal portions is prevented from being deformed, and the other inner lead terminal portion is wire-bonded to the semiconductor chip while supporting the other inner lead terminal portion. Is something that can be done.
【００２０】[0020]
【発明の効果】本発明の半導体チップ両面搭載用リード
フレームは、アイランド部の表裏両面に搭載した一方面
側半導体チップと、それに対応する一方面側インナーリ
ード部先端部に対して、及び、他方面側半導体チップ
と、それに対応する他方面側インナーリード部先端部に
対して、それぞれ反対面側より支持治具によって支持し
た状態で、及び、該反対面側に既にボンディングされた
ワイヤに支持治具を接触させることなく該ワイヤを回避
した状態で、円滑にワイヤボンディングを実施すること
ができ、リードフレームアイランド部の両面に半導体チ
ップを搭載する際のワイヤの変形や断線などの危険を無
くし、両面ワイヤボンディング実装工程における品質向
上に顕著な効果を発揮するものである。The lead frame for double-sided mounting of semiconductor chips of the present invention has one side semiconductor chips mounted on both front and back surfaces of the island portion, and the corresponding one side inner lead portion front end portion, and others. The semiconductor chip on one side and the corresponding tip of the inner lead portion on the other side are supported by supporting jigs from the opposite side, and are supported and fixed on the wires already bonded to the opposite side. In a state where the wire is avoided without contacting the tool, wire bonding can be smoothly performed, eliminating the risk of wire deformation or disconnection when mounting the semiconductor chip on both sides of the lead frame island portion, This is a remarkable effect in quality improvement in the double-sided wire bonding mounting process.
【図１】本発明の半導体チップ両面搭載用リードフレー
ムの全体平面図である。FIG. 1 is an overall plan view of a lead frame for mounting both sides of a semiconductor chip of the present invention.
【図２】本発明半導体チップ両面搭載用リードフレーム
のＬ−Ｌ拡大側断面図である。FIG. 2 is an enlarged side cross-sectional view taken along line L-L of a lead frame for mounting a semiconductor chip on both sides of the present invention.
【図３】本発明半導体チップ両面搭載用リードフレーム
におけるインナーリード部先端部と半導体チップとを両
面においてワイヤボンディングした状態を説明する側断
面図である。FIG. 3 is a side sectional view for explaining a state in which the front end portion of the inner lead portion and the semiconductor chip are wire-bonded on both sides of the lead frame for mounting the semiconductor chip on both sides of the present invention.
【図４】（ａ）本発明の半導体チップ両面搭載用リード
フレームを用いて、その一面側にワイヤボンディングす
る場合の工程を説明する側断面図である。 （ｂ）本発明の半導体チップ両面搭載用リードフレーム
の一面側にワイヤボンディングした後に、多面側に対し
てワイヤボンディングする場合の工程を説明する側断面
図である。FIG. 4 (a) is a side sectional view for explaining a process for wire bonding to one surface side of the lead frame for mounting both sides of the semiconductor chip of the present invention. (B) It is a side sectional view explaining the process in the case of wire-bonding to one surface side of the semiconductor chip double-sided mounting lead frame of the present invention, and then wire bonding to the multi-sided surface.
Ａ…多面付けされた半導体両面搭載用リードフレーム
Ｒ…単位半導体両面搭載用リードフレーム Ｄ，Ｄ1 ，
Ｄ2 …半導体チップ １…アイランド部 ２…インナー
リード部 ３…アウターリード部 １１…電極部 １２
…電極部 ２１…先端部 ２２…長端子部 ２２ａ…金
メッキ層 ２３…短端子部 ２３ａ…金メッキ層 ２５
…支持治具 ２６…支持治具A: Lead frame for multi-sided mounting on both sides of semiconductor
R ... Lead frame for mounting both sides of unit semiconductor D, D 1 ,
D 2 ... Semiconductor chip 1 ... Island portion 2 ... Inner lead portion 3 ... Outer lead portion 11 ... Electrode portion 12
... Electrode part 21 ... Tip part 22 ... Long terminal part 22a ... Gold plated layer 23 ... Short terminal part 23a ... Gold plated layer 25
… Support jig 26… Support jig
Claims (1)
ウターリード部３を備え、該アイランド部の両面に半導
体チップを搭載する形式の半導体チップ両面搭載用リー
ドフレームにおいて、アイランド部１外周に離間対向す
る複数本の各々インナーリード部２は、アイランド部１
の外周に近接する長端子部２２と、該長端子部２２より
短い短端子部２３とを備えていることを特徴とする半導
体チップ両面搭載用リードフレーム。1. A semiconductor chip double-sided mounting lead frame having an island portion 1, an inner lead portion 2, and an outer lead portion 3, and a semiconductor chip being mounted on both sides of the island portion. The inner lead portion 2 of each of the plurality of
1. A lead frame for double-sided mounting of semiconductor chips, comprising: a long terminal portion 22 adjacent to the outer periphery of the semiconductor chip; and a short terminal portion 23 shorter than the long terminal portion 22.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3314694A JPH05152503A (en) | 1991-11-28 | 1991-11-28 | Semiconductor chip double-sided mounting lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3314694A JPH05152503A (en) | 1991-11-28 | 1991-11-28 | Semiconductor chip double-sided mounting lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05152503A true JPH05152503A (en) | 1993-06-18 |
Family
ID=18056427
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3314694A Pending JPH05152503A (en) | 1991-11-28 | 1991-11-28 | Semiconductor chip double-sided mounting lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05152503A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069025A (en) * | 1994-11-15 | 2000-05-30 | Lg Semicon Co., Ltd. | Method for packaging a semiconductor device |
| US7414300B2 (en) | 2005-09-26 | 2008-08-19 | Mitsubishi Denki Kabushiki Kaisha | Molded semiconductor package |
| US7521778B2 (en) | 2005-11-15 | 2009-04-21 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
-
1991
- 1991-11-28 JP JP3314694A patent/JPH05152503A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6069025A (en) * | 1994-11-15 | 2000-05-30 | Lg Semicon Co., Ltd. | Method for packaging a semiconductor device |
| US7414300B2 (en) | 2005-09-26 | 2008-08-19 | Mitsubishi Denki Kabushiki Kaisha | Molded semiconductor package |
| US7521778B2 (en) | 2005-11-15 | 2009-04-21 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
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