JPH05152276A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05152276A
JPH05152276A JP3312068A JP31206891A JPH05152276A JP H05152276 A JPH05152276 A JP H05152276A JP 3312068 A JP3312068 A JP 3312068A JP 31206891 A JP31206891 A JP 31206891A JP H05152276 A JPH05152276 A JP H05152276A
Authority
JP
Japan
Prior art keywords
thin film
resist pattern
ferroelectric thin
ferroelectric
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3312068A
Other languages
Japanese (ja)
Other versions
JP3169654B2 (en
Inventor
Toru Nasu
徹 那須
Eiji Fujii
英治 藤井
Toshiyuki Ueda
利之 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP31206891A priority Critical patent/JP3169654B2/en
Publication of JPH05152276A publication Critical patent/JPH05152276A/en
Application granted granted Critical
Publication of JP3169654B2 publication Critical patent/JP3169654B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To provide a manufacturing method of a semiconductor device which enables pattern formation by a wet etching method of a ferroelectric thin film or a thin film of a substance having perovskite crystal structure. CONSTITUTION:Solution containing a ferroelectric element is applied by revolution to an Si substrate 11 and thermally treated at 450 deg.C or lower to remove an element excepting ferroelectric composition from the solution and to form a ferroelectric thin film 12. Then, a resist pattern 13 is formed on the ferroelectric thin film 12 by using photolithography and the ferroelectric thin film 12 is etched by weak acid of pH 6.5 or less using the resist pattern 13 as a mask. Lastly, the resist pattern 13 is removed and the ferroelectric thin film 12 is sintered and crystallized by performing heat treatment of 600 deg.C or higher. Thereby, pattern formation of a ferroelectric thin film by wet etching becomes possible.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、種々の電気的特性に優
れていることで知られる強誘電体薄膜またはペロブスカ
イト型結晶構造を有する物質の薄膜を用いた半導体装置
の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device using a ferroelectric thin film or a thin film of a substance having a perovskite type crystal structure, which is known to have various electrical characteristics.

【0002】[0002]

【従来の技術】強誘電体薄膜のパターン形成方法として
は、ウェットエッチング法では強誘電体薄膜のみを選択
的にエッチングすることが困難であるため、従来イオン
ミリング法が多く用いられていた。
2. Description of the Related Art As a method for forming a pattern of a ferroelectric thin film, it is difficult to selectively etch only the ferroelectric thin film by a wet etching method, and thus an ion milling method has been widely used.

【0003】以下に従来の製造方法について説明する。
図3(a)〜(d)は従来の半導体装置の製造方法であ
る。まず図3(a)に示すようにSi基板1上に強誘電
体成分を含む溶液をスピナーにより回転塗布し、大気中
で450℃以下の熱処理を2〜3分行うことにより前記
溶液から強誘電体組成以外の成分を除去して多孔質かつ
非晶質の強誘電体薄膜2を形成し、600℃以上の熱処
理を行うことにより焼結および結晶化させる。次に図3
(b)に示すように強誘電体薄膜2上にリソグラフィー
法を用いてレジストパターン3を形成する。次に図3
(c)に示すように電界で高速に加速したアルゴンイオ
ンをSi基板1の表面に斜めより入射させることにより
強誘電体薄膜2を削り取る。最後に図3(d)に示すよ
うにレジストパターン3を酸素プラズマアッシャーによ
り炭化して除去することにより強誘電体薄膜2のパター
ンが形成される。
A conventional manufacturing method will be described below.
3A to 3D show a conventional semiconductor device manufacturing method. First, as shown in FIG. 3A, a solution containing a ferroelectric component is spin-coated on a Si substrate 1 by a spinner, and a heat treatment at 450 ° C. or less is performed in the atmosphere for 2 to 3 minutes to remove the ferroelectric from the solution. Components other than the body composition are removed to form a porous and amorphous ferroelectric thin film 2, which is then sintered and crystallized by heat treatment at 600 ° C. or higher. Next in FIG.
As shown in (b), a resist pattern 3 is formed on the ferroelectric thin film 2 by using a lithography method. Next in FIG.
As shown in (c), the ferroelectric thin film 2 is scraped off by causing argon ions accelerated at high speed by an electric field to obliquely enter the surface of the Si substrate 1. Finally, as shown in FIG. 3D, the resist pattern 3 is carbonized and removed by an oxygen plasma asher to form a pattern of the ferroelectric thin film 2.

【0004】[0004]

【発明が解決しようとする課題】しかしなから上記の従
来の構成では、イオンをSi基板1の表面より斜めに入
射するため、強誘電体薄膜のパターンはレジストパター
ンに対してずれる。またこの方法では物理的な機構を利
用しているので強誘電体薄膜だけを削るといった選択性
に欠けるため、強誘電体薄膜のみを削るためには時間で
正確に制御を行わなければならない。さらにこの方法で
は電界で高速に加速したイオンを用いるためSi基板1
へダメージを与えるといった課題があった。
However, in the above conventional structure, since the ions are obliquely incident from the surface of the Si substrate 1, the pattern of the ferroelectric thin film is displaced from the resist pattern. In addition, since this method uses a physical mechanism, it lacks selectivity such that only the ferroelectric thin film is removed. Therefore, in order to remove only the ferroelectric thin film, precise control must be performed in time. Furthermore, since this method uses ions accelerated at high speed by an electric field, the Si substrate 1
There was a problem such as damage to.

【0005】本発明は上記従来の課題を解決するもの
で、Si基板にダメージを与えず、強誘電体薄膜の精度
あるパターン形成を可能にする半導体装置の製造方法を
提供することを目的とするものである。
The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device which enables accurate pattern formation of a ferroelectric thin film without damaging the Si substrate. It is a thing.

【0006】[0006]

【課題を解決するための手段】本発明は上記目的を達成
するために、支持基板の表面に非晶質の強誘電体薄膜を
形成する工程と、その強誘電体薄膜上にフォトリソグラ
フィー法を用いてレジストパターンを形成する工程と、
そのレジストパターンをマスクとして強誘電体薄膜をp
H6.5以下の弱酸によりエッチングする工程と、レジ
ストパターンを除去する工程と、強誘電体薄膜を結晶化
させる工程とを有する構成による。
In order to achieve the above object, the present invention provides a step of forming an amorphous ferroelectric thin film on the surface of a supporting substrate and a photolithography method on the ferroelectric thin film. A step of forming a resist pattern using
Using the resist pattern as a mask, the ferroelectric thin film is
It has a structure including a step of etching with a weak acid of H6.5 or less, a step of removing the resist pattern, and a step of crystallizing the ferroelectric thin film.

【0007】[0007]

【作用】この構成によって、強誘電体薄膜は非晶質状態
でpH6.5以下の弱酸でウェットエッチング法により
容易にエッチングされるため、強誘電体薄膜のみを選択
比よくエッチングすることができる。したがって従来困
難であったウェットエッチング法によるパターン形成が
可能となる。
With this structure, the ferroelectric thin film is easily etched by the wet etching method in the amorphous state with a weak acid having a pH of 6.5 or less, so that only the ferroelectric thin film can be etched with a high selective ratio. Therefore, it becomes possible to form a pattern by the wet etching method, which has been difficult in the past.

【0008】[0008]

【実施例】(実施例1)本発明の半導体装置の製造方法
の第1の実施例について図1(a)〜(d)を参照しな
がら説明する。
(Embodiment 1) A first embodiment of a method of manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 1 (a) to 1 (d).

【0009】従来例と同じように図1(a)に示すよう
に、Si基板11の上に、強誘電体成分を含む溶液をス
ピナーにより回転塗布し、大気中で450℃以下の熱処
理を2〜3分行うことにより前記溶液から強誘電体組成
以外の成分を除去して多孔質かつ非晶質の強誘電体薄膜
12を形成する。なお、所定の膜厚を得るために前記回
転塗布および熱処理の工程を数回繰り返してもよい。次
に従来例同様図1(b)に示すように強誘電体薄膜12
上にフォトリソグラフィー法を用いてレジストパターン
13を形成する。次に本発明の特徴として図1(c)に
示すようにレジストパターン13をマスクとして強誘電
体薄膜12を、水で10〜100分の1程度に希釈した
弗酸によりエッチングする。この後図1(d)に示すよ
うにレジストパターン13を酸素プラズマアッシャーに
より炭化して除去し、600℃以上の熱処理を施して強
誘電体薄膜12を焼結および結晶化させることにより強
誘電体薄膜12のパターンが形成される。
As in the conventional example, as shown in FIG. 1A, a solution containing a ferroelectric component is spin-coated on a Si substrate 11 by a spinner, and a heat treatment at 450.degree. By carrying out for about 3 minutes, components other than the ferroelectric composition are removed from the solution to form a porous and amorphous ferroelectric thin film 12. The steps of spin coating and heat treatment may be repeated several times to obtain a predetermined film thickness. Next, as in the conventional example, as shown in FIG.
A resist pattern 13 is formed on the top by photolithography. Next, as a feature of the present invention, as shown in FIG. 1C, the ferroelectric thin film 12 is etched with hydrofluoric acid diluted with water to about 1/100 to 1/100 using the resist pattern 13 as a mask. Thereafter, as shown in FIG. 1D, the resist pattern 13 is carbonized and removed by an oxygen plasma asher, and the ferroelectric thin film 12 is sintered and crystallized by performing a heat treatment at 600 ° C. or higher to obtain the ferroelectric substance. A pattern of thin film 12 is formed.

【0010】(実施例2)次に本発明の第2の実施例に
ついて図2(a)〜(d)を参照しながら説明する。図
2において、図1の第1の実施例と同一部分には同一番
号を付し、説明を省略する。すなわち第2の実施例の特
徴は図2(a)に示すようにSi基板11の上に、スパ
ッタ法またはCVD法を用いて基板温度300℃以下で
非晶質の強誘電体薄膜を蒸着して非晶質の強誘電体薄膜
21を形成することである。
(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. In FIG. 2, the same parts as those in the first embodiment of FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. That is, the feature of the second embodiment is that as shown in FIG. 2A, an amorphous ferroelectric thin film is vapor-deposited on a Si substrate 11 by using a sputtering method or a CVD method at a substrate temperature of 300 ° C. or lower. To form an amorphous ferroelectric thin film 21.

【0011】図2(b),(c)の工程は図1(b),
(c)と同様であり、図2(d)の工程でレジストパタ
ーン13を酸素プラズマアッシャーにより炭化して除去
した後、600℃以上の熱処理を施して強誘電体薄膜2
1を結晶化させることにより強誘電体薄膜21のパター
ンが形成される。
The steps of FIGS. 2B and 2C are as shown in FIG.
Similar to (c), the resist pattern 13 is carbonized and removed by an oxygen plasma asher in the step of FIG. 2D, and then the ferroelectric thin film 2 is heat-treated at 600 ° C. or higher.
The pattern of the ferroelectric thin film 21 is formed by crystallizing the ferroelectric thin film 1.

【0012】また強誘電体薄膜の代りにペロブスカイト
型結晶構造を有する物質の薄膜を用いることもできる。
Further, instead of the ferroelectric thin film, a thin film of a substance having a perovskite type crystal structure can be used.

【0013】すなわち支持基板の表面にペロブスカイト
型結晶構造を有する成分を含む溶液を回転塗布し、45
0℃以下の熱処理を行うことにより溶液からペロブスカ
イト型結晶構造を構成する組成以外の成分を除去して薄
膜を形成する。つぎにその薄膜上にフォトリソグラフィ
ー法を用いてレジストパターンを形成し、そのレジスト
パターンをマスクとして上記薄膜をpH6.5以下の弱
酸によりエッチングする。その後レジストパターンを除
去し、600℃以上の熱処理を施して上記薄膜を焼結お
よび結晶化させてペロブスカイト型結晶構造を有する薄
膜を形成した。
That is, a solution containing a component having a perovskite type crystal structure is spin-coated on the surface of the supporting substrate, and 45
By performing heat treatment at 0 ° C. or lower, components other than the composition constituting the perovskite type crystal structure are removed from the solution to form a thin film. Next, a resist pattern is formed on the thin film by photolithography, and the thin film is etched with a weak acid having a pH of 6.5 or less using the resist pattern as a mask. After that, the resist pattern was removed, and heat treatment was performed at 600 ° C. or higher to sinter and crystallize the thin film to form a thin film having a perovskite type crystal structure.

【0014】また本発明は同様に蒸着法にも適用でき
る。すなわち、支持基板の表面にスパッタ法またはCV
D法を用いて支持基板の温度300℃以下の条件でペロ
ブスカイト型結晶構造を構成する組成を有する非晶質薄
膜を蒸着する。つぎにその非晶質薄膜上にフォトリソグ
ラフィー法を用いてレジストパターンを形成し、そのレ
ジストパターンをマスクとして非晶質薄膜をpH6.5
以下の弱酸によりエッチングする。その後レジストパタ
ーンを除去し、600℃以上の熱処理を施して非晶質薄
膜を結晶化させてペロブスカイト型結晶構造を有する薄
膜を形成した。
The invention is likewise applicable to vapor deposition processes. That is, the surface of the supporting substrate is sputtered or CV
Using method D, an amorphous thin film having a composition that constitutes a perovskite type crystal structure is deposited under the condition that the temperature of the supporting substrate is 300 ° C. or lower. Next, a resist pattern is formed on the amorphous thin film by a photolithography method, and the amorphous thin film is adjusted to pH 6.5 using the resist pattern as a mask.
Etching is performed with the following weak acid. After that, the resist pattern was removed, and heat treatment was performed at 600 ° C. or higher to crystallize the amorphous thin film to form a thin film having a perovskite type crystal structure.

【0015】なお、上記2つの実施例では支持基板にS
i基板を用いたが、GaAs基板、石英基板、ガラス基
板等の他の支持基板を用いてもよく、また表面にトラン
ジスタ等の素子を作成した支持基板を用いてもよく、あ
るいは支持基板表面の少なくとも一部に金属薄膜を作成
し、その金属薄膜の上に強誘電体薄膜、ペロブスカイト
型結晶構造を有する薄膜等を形成してもよい。さらに上
記2つの実施例ではエッチング液に水で希釈した弗酸を
用いたが、酢酸や水で希釈した塩酸、硝酸等のpH6.
5以下の弱酸を用いてもよい。
In the above two embodiments, the support substrate is made of S.
Although the i substrate is used, other supporting substrates such as a GaAs substrate, a quartz substrate, and a glass substrate may be used, or a supporting substrate having elements such as transistors formed on the surface may be used, or A metal thin film may be formed at least partially, and a ferroelectric thin film, a thin film having a perovskite type crystal structure, etc. may be formed on the metal thin film. Further, although hydrofluoric acid diluted with water was used as the etching solution in the above two examples, the pH of hydrochloric acid, nitric acid, etc. diluted with acetic acid or water was adjusted to pH 6.
A weak acid of 5 or less may be used.

【0016】[0016]

【発明の効果】以上のように本発明の半導体装置の製造
方法は、pH6.5以下の弱酸でウェットエッチング法
によりパターン形成する構成によるので、強誘電体薄膜
のみを選択比よく、精度のあるパターンで形成できる半
導体装置の製造方法を提供できる。
As described above, since the method for manufacturing a semiconductor device of the present invention has a structure in which a pattern is formed by a wet etching method with a weak acid having a pH of 6.5 or less, only the ferroelectric thin film has a good selection ratio and is highly accurate. A method for manufacturing a semiconductor device that can be formed in a pattern can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例における半導体装置の製
造方法の工程断面図
FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

【図2】本発明の第2の実施例における半導体装置の製
造方法の工程断面図
FIG. 2 is a process sectional view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

【図3】従来の半導体装置の製造方法の工程断面図FIG. 3 is a process sectional view of a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

11 Si基板(支持基板) 12 強誘電体薄膜 13 レジストパターン 11 Si substrate (supporting substrate) 12 Ferroelectric thin film 13 Resist pattern

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】支持基板の表面に強誘電体成分を含む溶液
を回転塗布し、450℃以下の熱処理を行い、強誘電体
薄膜を形成する工程と、その強誘電体薄膜上にフォトリ
ソグラフィー法を用いてレジストパターンを形成する工
程と、そのレジストパターンをマスクとして前記強誘電
体薄膜をpH6.5以下の弱酸によりエッチングする工
程と、前記レジストパターンを除去する工程と、600
℃以上の熱処理を施して前記強誘電体薄膜を焼結および
結晶化させる工程とを有することを特徴とする半導体装
置の製造方法。
1. A step of spin-coating a solution containing a ferroelectric component on the surface of a supporting substrate and performing a heat treatment at 450 ° C. or lower to form a ferroelectric thin film, and a photolithography method on the ferroelectric thin film. A step of forming a resist pattern using the resist pattern, a step of etching the ferroelectric thin film with a weak acid having a pH of 6.5 or less using the resist pattern as a mask, a step of removing the resist pattern,
And a step of subjecting the ferroelectric thin film to a heat treatment at a temperature of not less than 0 ° C. to sinter and crystallize the ferroelectric thin film.
【請求項2】支持基板の表面にスパッタ法またはCVD
法を用いて前記支持基板の温度が300℃以下の条件で
非晶質の強誘電体薄膜を形成する工程と、その強誘電体
薄膜上にフォトリソグラフィー法を用いてレジストパタ
ーンを形成する工程と、そのレジストパターンをマスク
として前記強誘電体薄膜をpH6.5以下の弱酸により
エッチングする工程と、前記レジストパターンを除去す
る工程と、600℃以上の熱処理を施して前記強誘電体
薄膜を結晶化させる工程とを有することを特徴とする半
導体装置の製造方法。
2. A sputtering method or a CVD method on the surface of a supporting substrate.
Forming an amorphous ferroelectric thin film under the condition that the temperature of the supporting substrate is 300 ° C. or less by using a photolithography method, and forming a resist pattern on the ferroelectric thin film by using a photolithography method. A step of etching the ferroelectric thin film with a weak acid having a pH of 6.5 or less using the resist pattern as a mask; a step of removing the resist pattern; and a heat treatment at 600 ° C. or more to crystallize the ferroelectric thin film. A method of manufacturing a semiconductor device, comprising:
【請求項3】支持基板の表面にペロブスカイト型結晶構
造を有する成分を含む溶液を回転塗布し、450℃以下
の熱処理を行うことにより前記溶液から前記ペロブスカ
イト型結晶構造を構成する組成以外の成分を除去して薄
膜を形成する工程と、その薄膜上にフォトリソグラフィ
ー法を用いてレジストパターンを形成する工程と、その
レジストパターンをマスクとして前記薄膜をpH6.5
以下の弱酸によりエッチングする工程と、前記レジスト
パターンを除去する工程と、600℃以上の熱処理を施
して前記薄膜を焼結および結晶化させてペロブスカイト
型結晶構造を有する薄膜を形成する工程とを有すること
を特徴とする半導体装置の製造方法。
3. A solution containing a component having a perovskite type crystal structure is spin-coated on the surface of a supporting substrate, and a heat treatment at 450 ° C. or lower is performed to remove components other than the composition constituting the perovskite type crystal structure from the solution. A step of removing and forming a thin film, a step of forming a resist pattern on the thin film by using a photolithography method, and a pH of the thin film of 6.5 using the resist pattern as a mask.
The method has the following steps of etching with a weak acid, removing the resist pattern, and performing heat treatment at 600 ° C. or higher to sinter and crystallize the thin film to form a thin film having a perovskite crystal structure. A method of manufacturing a semiconductor device, comprising:
【請求項4】支持基板の表面にスパッタ法またはCVD
法を用いて前記支持基板の温度300℃以下の条件でペ
ロブスカイト型結晶構造を構成する組成を有する非晶質
薄膜を蒸着する工程と、その非晶質薄膜上にフォトリソ
グラフィー法を用いてレジストパターンを形成する工程
と、前記レジストパターンをマスクとして前記非晶質薄
膜をpH6.5以下の弱酸によりエッチングする工程
と、前記レジストパターンを除去する工程と、600℃
以上の熱処理を施して前記非晶質薄膜を結晶化させてペ
ロブスカイト型結晶構造を有する薄膜を形成する工程と
を有することを特徴とする半導体装置の製造方法。
4. A sputtering method or a CVD method on the surface of a supporting substrate.
Using the method to deposit an amorphous thin film having a composition forming a perovskite type crystal structure under the condition that the temperature of the supporting substrate is 300 ° C. or lower, and a resist pattern on the amorphous thin film using a photolithography method. , A step of etching the amorphous thin film with a weak acid having a pH of 6.5 or less using the resist pattern as a mask, a step of removing the resist pattern, and 600 ° C.
And a step of crystallizing the amorphous thin film by the above heat treatment to form a thin film having a perovskite type crystal structure.
【請求項5】支持基板が、その表面の所定部にあらかじ
め金属薄膜が形成された支持基板であることを特徴とす
る請求項1,2,3または4記載の半導体装置の製造方
法。
5. The method of manufacturing a semiconductor device according to claim 1, wherein the support substrate is a support substrate having a metal thin film formed in advance on a predetermined portion of the surface thereof.
JP31206891A 1991-11-27 1991-11-27 Method for manufacturing semiconductor device Expired - Fee Related JP3169654B2 (en)

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Application Number Priority Date Filing Date Title
JP31206891A JP3169654B2 (en) 1991-11-27 1991-11-27 Method for manufacturing semiconductor device

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JPH05152276A true JPH05152276A (en) 1993-06-18
JP3169654B2 JP3169654B2 (en) 2001-05-28

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245433A (en) * 2005-03-04 2006-09-14 Oki Electric Ind Co Ltd Method of manufacturing semiconductor device
JP2014067808A (en) * 2012-09-25 2014-04-17 Fujifilm Corp Etchant, method for manufacturing piezoelectric element, and etching method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006245433A (en) * 2005-03-04 2006-09-14 Oki Electric Ind Co Ltd Method of manufacturing semiconductor device
JP2014067808A (en) * 2012-09-25 2014-04-17 Fujifilm Corp Etchant, method for manufacturing piezoelectric element, and etching method

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