JPH05144846A - Compound semiconductor field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce a leakage current in the reverse direction to a Schottky junction in an FET using a heat-resisting metal film for its gate electrode by a method wherein the gate electrode using the heat-resisting metal film is formed into a constitution of a very thin film thickness within a specified extent. CONSTITUTION:In an FET using a heat-resisting metal film for its gate electrode 3, the gate electrode 3 is constituted very thin in a thickness of 100 to 200Angstrom . For example, Si is ion-implanted ion a semi-cinsulative GaAs substrate 1 to form a channel 2 and moreover, after a WSi film is deposited, the substrate is processed in a prescribed length and a gate electrode 3 is formed. Then, Si is ion-planted slightly deeper than the depth of the channel 2 to form N<+> layers 4 and moreover, an SiO2 film is deposited on the whole surface and Si is ion-implanted at a distance of about 1500Angstrom from the electrode 3 utilizing the film thickness of the SiO2 film to form N<+> layers 5. After that, the SiO2 film is removed and the electrode 3 is etched back to a thickness of 100 to 200Angstrom . Then, an annealing is performed to activate each ion-implanted layer and moreover, after an SiN film 6 is deposited, ohmic electrodes 7 are formed and a FET is completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor field effect transistor (FET) using a Schottky junction, which has improved Schottky reverse characteristics.

[0002]

2. Description of the Related Art A conventional method of manufacturing an FET will be described by taking a case of using gallium arsenide as a substrate.
As shown in FIGS. 6A to 6D, Si 29 is selectively formed on the semi-insulating gallium arsenide substrate 41 by ion implantation.
Ion acceleration energy 25 keV, dose 7.0 × 10 ¹²
After forming the channel 42 by ion-implanting (cm ^-2 ), a conventional method such as tungsten silicon (WSi) is used.
Thereby forming the gate electrode 43. By using this gate electrode 43, Si 29 ions are accelerated in self-alignment with an acceleration energy of 50 k.
Ions are implanted with eV and a dose of 2.0 × 10 ¹² (cm ⁻² ) to form the n ′ layer 44. Next, for example, a silicon dioxide film of 2000 A is deposited on the entire surface of the substrate, and this thickness is used to form the gate electrode 43.
About 150A away from Si28 ions at an acceleration energy of 150
Ions are implanted with keV and a dose amount of 5.0 × 10 ¹³ (cm ⁻² ) to form an n ⁺ layer 45. Then, after removing the silicon dioxide film, annealing is performed at 820 ° C. for 15 minutes by a usual method to activate each ion implantation layer. Further, a silicon nitride film (SiN) 46 of 2000 A is deposited by a usual method, and then an ohmic electrode 47 is formed to complete the FET.

However, the FE created in this way
At T, as shown in the Schottky reverse characteristic of FIG. 7A, a large leak current with a step near -3 V may be observed in the reverse gate-drain characteristic. Such anomalous reverse characteristic is caused by p in Si.
It is considered that dislocations in the semiconductor substrate in the vicinity of the Schottky junction (gate electrode) are considered to be the cause, as in the case of the abnormal reverse characteristic of the n-junction (so-called microplasma phenomenon). In such an FET, even if the gate voltage is made sufficiently negative (V _GS = -0.7 V) as shown in FIG. 7 (b) due to the leakage current as shown in FIG. 7 (a), When V _DS ≧ 3V, I _DS flows, resulting in an FET that does not pinch the drain current sufficiently.

[0004]

In the conventional compound semiconductor field effect transistor described above, since the gate edge is steep (the gate edge is substantially perpendicular to the semiconductor substrate), it is located in the gate metal or the region surrounding the gate metal. Due to the stress of the insulating film and the stress of the semiconductor substrate itself, as shown in FIG.
location) is easy to generate (for example, the document Jpn.J.App
l.Phys.30 (1991) L551, J.Electrochem.Soc.138 (1991) 143
9). In FIG. 8, 51 is a semi-insulating gallium arsenide substrate, 5
2 is an active layer, 53 is a gate electrode, 54 is a dislocation, and 55 is SiN.
The film and 56 are ohmic electrodes.

Further, when a reverse bias is applied between the gate and drain of the FET, a high electric field region is normally generated directly below the gate end in the longitudinal direction of the gate, and as shown in FIG. Such a luminescence phenomenon (avalanche) is observed. However, if dislocations occur in a portion just below the gate edge, the electric field concentrates near this dislocation, and the high electric field region that should be uniform becomes non-uniform near the dislocations. Light emission in the local area at the edge (microplasma)
Is observed. The generation of such a non-uniform high electric field region leads to generation of a leak current at a relatively low gate-drain reverse bias (for example, V _GD = −1 to −2 V). In FIGS. 9A and 9B, 61 is an active layer region, 62 is a source electrode, 63 is a gate electrode, 64 is a drain electrode, 65 is a uniform light emitting region, and 66 is a non-uniform light emitting region.

The present invention solves the above problems, and an object of the present invention is to provide a compound semiconductor field effect transistor in which a Schottky junction reverse leakage current is reduced in the compound semiconductor field effect transistor using a refractory metal for a gate electrode. It is what

[0007]

In order to solve the above problems, the present invention is directed to a compound semiconductor field effect transistor in which the gate electrode is a refractory metal, and the gate electrode on the channel of the FET is 100 to 200 A. It has a thin film thickness.

Further, in the compound semiconductor field effect transistor of the present invention, the gate electrode is a refractory metal, and the cross section of the gate electrode is trapezoidal. Further, in the compound semiconductor field effect transistor of the present invention, the gate electrode is a refractory metal, and after forming the gate electrode and annealing and activating each ion implantation layer, the surface of the semiconductor substrate around the gate electrode is etched. It is formed thin.

Further, in the compound semiconductor field effect transistor of the present invention, the gate electrode is a refractory metal, the semiconductor substrate around the gate electrode is etched to be thin, and the portion including the gate electrode and the semiconductor substrate immediately below the gate electrode. Is configured to have a trapezoidal shape.

[0010]

With the above structure, since the gate electrode on the channel of the FET is extremely thin, 100 to 200 A, the stress of the gate electrode can be almost ignored, and the occurrence of dislocations in the semiconductor substrate immediately below the gate end is reduced. In addition, since the gate electrode has a trapezoidal cross-sectional shape, the influence of the stress of the insulating film in the gate electrode or the region surrounding the gate electrode and the stress of the semiconductor substrate itself is mitigated. The generation of dislocations in the gate electrode can be reduced, and the surface of the semiconductor substrate around the gate electrode is thinly etched, so that the stress of the gate electrode or the insulating film in the region surrounding the gate electrode and the stress of the semiconductor substrate itself cause the gate Even if dislocations occur in the semiconductor substrate directly under the edge, they can be removed. In addition, the gate electrode has a trapezoidal cross section and the periphery of the gate electrode is By thinly etching the surface of the surrounding semiconductor substrate, the effects of the stress of the gate electrode or the insulating film in the region surrounding the gate electrode and the stress of the semiconductor substrate itself are mitigated, and dislocations occur in the semiconductor substrate immediately below the gate edge. It is difficult to do, and even if it occurs, it will occur at a place away from just below the gate end. Therefore, F
When a voltage is applied between the gate and drain of ET, it is possible to suppress the generation of a local high electric field region at the gate end due to the generation of dislocations, and it is possible to reduce the reverse leakage current of the Schottky junction.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 (a) to 1 (e) are sectional views showing a manufacturing process of a compound semiconductor field effect transistor of a first embodiment of the present invention. Here, gallium arsenide (Ga) is used as a compound semiconductor.
The case of using As) will be described as an example. Figure 1 (a)
In (e), first, for example, Si 29 ions are accelerated to a predetermined portion on the semi-insulating GaAs substrate 1 at an acceleration energy of 25 keV,
A channel 2 is formed by ion implantation with a dose amount of 8.0 × 10 ¹² (cm ⁻² ). Further, for example, WSi is sputtered
After depositing 2000 A, the gate electrode 3 is formed by processing to a predetermined length. This gate electrode 3 is used to accelerate Si 29 ions in a self-aligned manner and slightly deeper than the channel 2.
KeV with a dose amount of 2.0 × 10 ¹² (cm ⁻² ) is ion-implanted to form an n ′ layer 4, and a silicon dioxide film, for example, of 2500 A is further deposited on the entire surface of the substrate. Accelerating energy of Si 28 ions at a distance of 1500 A 150
Ions are implanted with keV and a dose amount of 5.0 × 10 ¹³ (cm ⁻² ) to form the n ⁺ layer 5.

Then, after removing the silicon dioxide film, as shown in FIG. 1D, the gate electrode 3 is formed to a thickness of 100 to 200 A, for example, reactive ion etching (RIE).
Etch back at. This is possible by strictly controlling the etching rate of the gate metal by RIE. Then, each ion-implanted layer is activated by annealing at 820 ° C. for 15 minutes by a usual method. Further, a silicon nitride film (SiN) 6 of 2000 A is deposited by a usual method, and then an ohmic electrode 7 is formed to complete the FET.

As described above, since the gate electrode portion on the channel of the FET has an extremely thin film thickness of 100 to 200 A, the stress of the gate electrode can be almost ignored. Therefore, dislocation occurs in the semiconductor substrate just below the gate end. Can be reduced. Therefore, when a voltage is applied between the gate and drain of the FET, it is possible to suppress the generation of a local high electric field region at the gate end due to the generation of dislocations, and reduce the Schottky junction reverse leakage current.

2 (a) to 2 (e) are sectional views showing a manufacturing process of the compound semiconductor field effect transistor of the second embodiment of the present invention. Here again, the case of using gallium arsenide (GaAs) as the compound semiconductor will be described as an example. Figure 2
In (a) to (e), first, for example, Si29 ions are accelerated to a predetermined portion on the semi-insulating GaAs substrate 11 at an acceleration energy of 25 k.
A channel 12 is formed by ion implantation with eV and a dose amount of 8.0 × 10 ¹² (cm ⁻² ). Further, for example, by a sputtering method, W
After depositing 2000 A of Si, using the resist as a mask, the gate electrode 13 having a trapezoidal cross section is processed into a predetermined length by an ion milling method with an incident angle of 30 ° as shown by the arrow in FIG. 2 (b). To form. Utilizing this gate electrode 13, Si 29 ions are self-aligned and slightly deeper than the channel 12 with an acceleration energy of 50 keV and a dose of 2.0 × 10 ¹² (cm ⁻² ).
Then, the n'layer 14 is formed by ion implantation.

Next, a silicon dioxide film, for example, is formed on the entire surface of the substrate.
Deposit 2500A and use this film thickness from gate electrode 13 to about 15
Accelerating energy of Si28 ions at a distance of 00A 150 keV,
Ion implantation with a dose of 5.0 × 10 ¹³ (cm ^-2 ) n ⁺ layer 15
To form. Then, after removing the silicon dioxide film, annealing is performed at 820 ° C. for 15 minutes by a usual method to activate each ion implantation layer. Further, a silicon nitride film (Si
After depositing N) 16 for 2000 A, an ohmic electrode 17 is formed to complete the FET.

Since the gate electrode has a trapezoidal cross section as described above, the influence of the stress of the insulating film in the gate electrode or the region surrounding the gate electrode and the stress of the semiconductor substrate itself is mitigated, and the semiconductor substrate immediately below the gate end is relaxed. It is possible to reduce the generation of dislocations therein. Therefore, when a voltage is applied between the gate and drain of the FET, it is possible to suppress the generation of a local high potential region at the gate end due to the generation of dislocations, and to reduce the Schottky junction reverse leakage current.

3 (a) to 3 (e) are cross-sectional views showing a manufacturing process of the compound semiconductor field effect transistor of the third embodiment of the present invention. Here again, the case of using gallium arsenide (GaAs) as the compound semiconductor will be described as an example. Figure 3
In (a) to (e), first, for example, Si 29 ions are accelerated to a predetermined portion on the semi-insulating GaAs substrate 21 at an acceleration energy of 30 k.
A channel 22 is formed by ion implantation with eV and a dose amount of 8.0 × 10 ¹² (cm ⁻² ). Further, for example, by a sputtering method, W
After depositing 2000 A of Si, it is processed into a predetermined length to form a gate electrode 23. Using this gate electrode 23, Si 29 ions are ion-implanted in a self-aligned manner slightly deeper than the channel 22 with an acceleration energy of 60 keV and a dose of 2.0 × 10 ¹² (cm ⁻² ) to form an n ′ layer 24.

Next, for example, a silicon dioxide film is formed on the entire surface of the substrate.
2000A was deposited, and using this film thickness, about 1500 from the gate electrode
Si 28 ions are separated from A and ion implantation is performed at an acceleration energy of 160 keV and a dose amount of 5.0 × 10 ¹³ (cm ⁻² ), to form an n ⁺ layer 25. Then, after removing the silicon dioxide film, annealing is performed at 820 ° C. for 15 minutes by a usual method to activate each ion implantation layer. Next, a gate pattern is formed on the gate electrode 23 with a resist, and the resist is used as a mask with tartaric acid, as shown in FIG. 3 (e). Lightly etch a few hundred A. Further, a silicon nitride film (Si
After depositing N) 26 for 2000 A, an ohmic electrode 27 is formed to complete the FET.

As described above, the surface of the semiconductor substrate around the gate electrode is thinly etched after annealing,
Even if dislocations occur in the semiconductor substrate directly below the gate end due to the stress of the gate electrode or the insulating film in the region surrounding the gate electrode and the stress of the semiconductor substrate itself, the dislocations can be removed by this etching process. Therefore,
When a voltage is applied between the gate and drain of the FET, it is possible to suppress the generation of a local high electric field region at the gate end due to the generation of dislocations, and it is possible to reduce the reverse leakage current of the Schottky junction.

4 (a) to 4 (e) are sectional views showing steps of manufacturing a compound semiconductor field effect transistor according to still another embodiment of the present invention. Here again, the case of using gallium arsenide (GaAs) as the compound semiconductor will be described as an example. In FIGS. 4 (a) to 4 (e), first, for example, Si29 ions are accelerated at a predetermined position on the semi-insulating GaAs substrate 31 with an acceleration energy of 30.
A channel 32 is formed by ion implantation with keV and a dose amount of 8.0 × 10 ¹² (cm ⁻² ). Further, for example, WSi of 2000 A is deposited by the sputtering method, and the resist is used as a mask.
For example, a gate electrode 33 having a trapezoidal cross-section is formed by processing to a predetermined length by an ion milling method with an incident angle of 30 ° as shown by the arrow in FIG. 4 (b). At this time, the substrate surface is further etched deep by several tens of A along the inclined surface of the trapezoidal gate electrode 33 by the ion milling method. Using this gate electrode, the Si is slightly deeper than the channel 32 in a self-aligned manner.
29 ions acceleration energy 50 keV, dose 2.0 × 10
Ions are implanted at ¹² (cm ⁻² ) to form the n ′ layer 34.

Next, a silicon dioxide film, for example, is formed on the entire surface of the substrate.
Deposit 2500A and use this film thickness from gate electrode 33 to about 15
Accelerating energy of Si28 ions at a distance of 00A 150 keV,
Ion implantation is performed at a dose of 5.0 × 10 ¹³ (cm ^-2 ), and n ⁺ layer 35
To form. Then, after removing the silicon dioxide film, annealing is performed at 820 ° C. for 15 minutes by a usual method to activate each ion-implanted layer. Further, a silicon nitride film (Si
After depositing N) 36 for 2000 A, an ohmic electrode 37 is formed to complete the FET.

As described above, the cross-sectional shape of the gate electrode is trapezoidal, and the surface of the semiconductor substrate around the gate electrode is thinly etched, so that the stress of the insulating film in the gate electrode or the region surrounding the gate electrode and the semiconductor substrate The effect of its own stress is mitigated, and dislocations are unlikely to occur in the semiconductor substrate just below the gate end, and even if they occur, they occur away from just below the gate end. Therefore,
When a voltage is applied between the gate and drain of the FET, it is possible to suppress the generation of a local high electric field region at the gate end due to the generation of dislocations, and it is possible to reduce the reverse leakage current of the Schottky junction.

FIG. 5 shows an example of the voltage-current characteristic and the Schottky reverse direction characteristic of the FET in the second embodiment. As shown in FIG. 5 (b), the Schottky reverse direction characteristic has a small leak current, and accordingly, the voltage-current characteristic is set to V _GS = −0.8 V as shown in FIG. 5 (a). A satisfactory FET can be obtained with a sufficient pinch characteristic.
The FE having the same good characteristics in the other examples.
T is obtained.

[0024]

As described above, according to the present invention, it is possible to reduce or eliminate the occurrence of dislocations in the semiconductor substrate immediately below the gate end. Therefore, when a voltage is applied between the gate and drain of the FET, It is possible to suppress the occurrence of a local high electric field region near the dislocations at the gate edge, and reduce the Schottky junction reverse leakage current.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a compound semiconductor field effect transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a compound semiconductor field effect transistor according to a second embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a compound semiconductor field effect transistor according to a third embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a manufacturing process of a compound semiconductor field effect transistor according to a fourth embodiment of the present invention.

FIG. 5 is a voltage-current characteristic diagram and a Schottky reverse direction characteristic diagram of a compound semiconductor field effect transistor according to a second example of the present invention.

FIG. 6 is a cross-sectional view showing a manufacturing process of a conventional compound semiconductor field effect transistor.

7A and 7B are a Schottky junction reverse direction characteristic diagram and a current-voltage characteristic diagram of a compound semiconductor field effect transistor according to a conventional example.

FIG. 8 is a cross-sectional view of the FET when dislocations occur in the semiconductor substrate just below the end of the gate electrode.

9A and 9B are diagrams respectively showing a state in which uniform light emission when dislocations do not occur and nonuniform light emission when dislocations occur are viewed from the upper surface of the FET.

[Explanation of symbols]

1,11,21,31 Semi-insulating gallium arsenide substrate 2,12,22,32 Channel 3,13,23,33 Gate electrode 4,14,24,34 n'layer 5,15,25,35 n ⁺ layer 6,16,26,36 SiN film 7,17,27,37 Ohmic electrode

Claims (4)

[Claims] 1. A compound semiconductor field effect transistor using a refractory metal for a gate electrode, wherein the gate electrode is
A compound semiconductor field effect transistor characterized by being made thin including 100 to 200 A. 2. A compound semiconductor field effect transistor using a refractory metal for a gate electrode, wherein the gate electrode has a trapezoidal cross section. 3. A compound semiconductor field effect transistor using a refractory metal for a gate electrode, which is formed by thinly etching a semiconductor substrate around the gate electrode. 4. A compound semiconductor field effect transistor using a refractory metal for a gate electrode, which is formed by thinly etching a semiconductor substrate around a gate electrode, and a portion including the gate electrode and a semiconductor substrate immediately below is trapezoidal. A compound semiconductor field effect transistor, characterized in that