JPH05142295A - Method for burn-in test and pattern generating circuit for the test - Google Patents

Abstract

PURPOSE:To execute a dynamic burn-in test accurately and at the low cost by supplying separate LSIs with a plurality of active signals different in the timing from one another, respectively. CONSTITUTION:Each LSI is constructed as memory LSI formed of static RAM, and a large number of memory LSIs 1 are arranged on a burn-in board 3. Moreover, such burn-in boards 3 as the above are put together in large numbers and disposed in a high-temperature furnace 4. The LSIs 2 are divided into four groups (A to D) when they are disposed on the burn-in board 3. Chip enable signal lines C1 to C4 and read-write signal lines W2 to W4 forming active signal lines of the burn-in board 3 supply chip enable signals and read-write signals respectively to each of the groups A to D of the LSIs 2. Each chip enable signal and each read-write signal are supplied respectively from a pattern generating board 2 disposed outside the high-temperature furnace 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a burn-in test method for a semiconductor integrated circuit and a pattern generation circuit for the test, and more particularly to a large number of semiconductor integrated circuits of a type which receives an active signal and becomes an operating state. The present invention relates to a burn-in test method for a dynamic burn-in test performed while supplying an active signal to the circuit, and a pattern generation circuit for the test.

In a semiconductor integrated circuit, a reliability acceleration test called a burn-in test is performed in order to guarantee the reliability of the product. In this burn-in test, the semiconductor integrated circuit is stressed by a minimum predetermined high temperature and a power supply voltage to accelerate the manifestation of a potential defective portion, and at the time of the burn-in test. , Or subsequent functional testing, eliminates products with exposed defects.

In the burn-in test, in order to accelerate the manifestation of defective parts, a predetermined high power supply voltage is applied,
A static burn-in test is performed by simply maintaining all inputs of the integrated circuit at a constant voltage (for example, zero potential or -2 V), and a signal pattern for operating the integrated circuit is applied to the integrated circuit. There is a dynamic burn-in test conducted while

For example, in a memory integrated circuit configured as a Bi-CMOS LSI, each circuit element does not become in an operating state only by applying a power supply voltage and maintaining a constant voltage of an input section, so that a chip enable that generates an active signal is generated. Signal or a chip select signal (hereinafter simply referred to as a chip enable signal) and a signal for operating a read / write signal, etc., while sufficiently operating each circuit element,
It is necessary to make the defective part visible. For this signal supply, a pattern generation circuit in which a predetermined signal pattern is stored in advance is adopted.

[0005]

2. Description of the Related Art FIG. 6 is a block diagram showing a partial configuration of a test circuit in a conventional dynamic burn-in test in a memory integrated circuit (static RAM). In the figure, for example, several hundreds of LSIs 1 forming each memory integrated circuit are arranged on one burn-in board 3, and several dozens of such burn-in boards 3 are grouped together to form a high temperature furnace 4. It is placed inside. The temperature in the furnace is maintained around 120 degrees, for example.

From the pattern generation circuit 2, a chip enable signal XCE (with a top bar of CE, which forms an active signal, is provided to each LSI 1 via a wiring path and a connector of each burn-in board 3 corresponding thereto. And a read / write signal XWE are periodically supplied, and at this time, a data signal for writing to the cell is supplied or a signal is read from the cell. For this reason, each memory integrated circuit 1 is brought into a sufficiently operating state, and a sufficient dynamic burn-in test is performed as a reliability acceleration test.

[0007]

In the dynamic burn-in test described above, since all the memory integrated circuits operate simultaneously, the peak current consumption flowing through the power supply line in the high temperature furnace becomes extremely large. Therefore, in the high temperature furnace, it is necessary to increase the current capacity of the power supply line such as each board portion of the burn-in test apparatus, which causes a problem of increase in equipment cost.

Further, since crosstalk is unavoidable in each signal line in each memory integrated circuit due to power fluctuations occurring in the power supply line due to simultaneous operation of each memory integrated circuit, it is necessary to perform a functional test at the same time. There is also a problem that there is a high possibility that an error will occur in signal transmission.

In view of the above-mentioned problems in the conventional dynamic burn-in test of the semiconductor integrated circuit, the present invention increases the margin of the power supply line as much as possible and, at the time of the functional test, an error in signal transmission in the signal line of each semiconductor integrated circuit. It is an object of the present invention to provide a burn-in test method in which a dynamic burn-in test is performed accurately and at low cost, and a pattern generation circuit for the test.

[0010]

FIG. 1 shows the burn of the present invention.
FIG. 2 is a block diagram showing the configuration of a test circuit for explaining the principle of the in-test method, and FIG. 2 is an example of a timing chart of each active signal in the test circuit of FIG. In FIG. 1, 1 is an LSI, 2 is a pattern generation circuit, and A1 to A
Reference numerals 4 denote active signal lines, respectively, and the active signals illustrated in FIG. 2 are supplied to the four groups of LSIs via the signal lines A1 to A4, respectively.

In order to achieve the above object, the burn-in test method according to the present invention has a large number of LSs of a type which becomes active by receiving an active signal, as illustrated in FIGS.
In the burn-in test method for supplying at least the active signals to I (1), a plurality of active signals having different timings are supplied to the LSIs (1), respectively. To do.

Further, the pattern generating circuit of the present invention includes a large number of LSIs of a type that is activated when receiving an active signal.
In (1), in a pattern generating circuit (2) for burn-in test for supplying at least the active signals, the pattern generating circuit (2) includes a plurality of active signal output lines (A1 to A4). The active signal output line outputs a plurality of active signals having different timings.

[0013]

Since the pattern generation circuit outputs a plurality of active signals having different timings from each other and each LSI receives any one of the active signals, the operation timing of each LSI can be shifted. By reducing the current peak at the time of LSI operation that occurs in the power supply line of the test equipment, the power-carrying capacity of the power supply line is suppressed to a small level, the equipment cost of the burn-in test equipment is reduced, and the fluctuation of the power supply in the power supply line is reduced. Suppressing and preventing crosstalk etc. that occur in each signal line enables an accurate functional test.

[0014]

Embodiments of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram showing a partial configuration of a test circuit for explaining a burn-in test method according to an embodiment of the present invention. In the figure, each LSI is configured as a memory LSI composed of a static RAM, and a large number of memory LSIs 1 are arranged on the burn-in board 3. Further, a large number of such burn-in boards 3 are collected and arranged in the high temperature furnace 4.

Each LSI 1 has a burn-in board 3 respectively.
Burn-in board 3 is arranged in the above four groups divided into groups A to D.
Chip enable signal lines C1 to C4 and read / write signal lines W1 to W1
W4 supplies a chip enable signal and a read / write signal to each of the groups A to D of each LSI 1, respectively.

Each chip enable signal and each lead
The write signal is supplied from the pattern generation board 2 which is arranged outside the high temperature furnace 4 and constitutes a pattern generation circuit.
The circuit configuration of the active signal circuit in the pattern generation board 2 is shown in FIG.

As shown in FIG. 4, in this active signal circuit, from the original chip enable signal XCE and the original read / write signal XWE which have been conventionally used as active signals in the memory LSI, the inverters INV1 to INV1 are respectively supplied. Via INV4 or directly
Chip enable signals XCE1 to XC for each group
E4 and read / write signals XWE1 to XWE4 are obtained.

FIG. 5 shows the chip enable signals XCE1 to XCE4 and the read / write signals XWE1 to XWE4 for each group, and the output timing of the LSI of each group in the read mode. In the figure, a cycle T indicates an operation cycle of the memory performed in this test, the address signal Add makes an address change once within the operation cycle T, and one memory cell is sequentially operated at each operation cycle T. Is specified.

As the active signals given to the LSIs in the A group, the same signals XCE1 and XWE1 as the original chip enable signal XCE and the original read / write signal XWE which have been used conventionally are given, and these are respectively the operating cycle T. There are two and one L level periods within.

While the chip enable signal XCE1 is at the L level and the read / write signal XWE1 is at the H level ((a) in the figure), the LSI of the A group is in the read mode and the signal of any memory cell is Since the data is read, the bipolar transistors and the like that form the sense amplifier of the LSI of the group A are turned on in the latter half period (a) of the operation cycle T.

The active signal given to the LSI of the B group is different from the active signal given to the LSI of the A group in that the chip enable signal XCE2 is an inverted signal of the original chip enable signal XCE.

Therefore, the read mode of the LSI of the B group is, as shown in the figure, the chip enable signal XC.
E2 is L level and read / write signal XWE2 is H
Occurs during the level period ((b) in the figure) and is in the latter half of the operating period T and in the read mode period (a) of the A group
It occurs twice before and after. As a result, the ON period of the sense amplifier of the LSI of the B group occurs twice, and the operating time thereof is the same as the operating time of the A group.

Similarly, LS of C group and D group
The respective active signals of I have different timings from the active signals of the A and B groups, respectively, and as shown in the figure, C
The active period in the LSI of the group is the operation cycle T
In the first half of the figure ((c) in the figure)
In the first half of the operation cycle T and before and after the active period (c) of the group C (illustrated in (d)).

Since the operation time of the bipolar transistors in the LSIs of the groups A to D is the same in the groups A to D, the dynamic burn-in test in each of the LSIs is performed under the same operating condition.

As described above, since the burn-in test of each LSI 1 is performed under the same condition and the timings of the operation periods thereof are deviated from each other, the peak of the current consumption in the power supply line of the test apparatus is almost the same as that of the conventional one. 1/4,
In addition to the provision of equipment margin in the power supply line, the voltage fluctuation in the power supply line can be suppressed to a small level, the generation of an erroneous signal due to this can be suppressed, and an accurate functional test can be performed.

In the above embodiment, the LSIs are grouped for each board to suppress the fluctuation of the power supply line for each board. However, for example, all the LSIs mounted on one board are integrated. It is also possible to make each board into a group different from each other.

Further, an example has been shown in which the pattern generation board is arranged outside the high temperature furnace and the operation timing of each LSI is changed by inverting the chip enable signal and the read / write signal in the pattern generation board. However, the present invention is not necessarily limited to such a configuration, and for example, only a part of the function of the pattern generation circuit may be arranged in the high temperature furnace, and the operation timing may be changed by a delay circuit or the like.

Further, in the above embodiment, the case where the LSI to be tested is a memory integrated circuit and is a static RAM is illustrated, but the LSI to be tested is not limited to the static RAM,
The same operation is performed whether it is a dynamic RAM, a microprocessor, a controller, or the like. In the case of the dynamic RAM, the row address strobe signal XRAS and the output enable signal XOE are used as the active signal in addition to the chip enable signal and the read / write signal exemplified in the above embodiment.
Etc. are also included.

[0029]

As described above, according to the burn-in test method and the pattern generation circuit for the test of the present invention, the power supply line of the test apparatus can be kept small in capacity and the facility cost can be reduced. When the tests are performed simultaneously, the remarkable effect that the oscillation of the power supply line can be suppressed to a low level and the occurrence of an error in signal transmission can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram of a test circuit for showing the principle of a burn-in test method of the present invention.

FIG. 2 is an example of signal timing in an active signal line of FIG.

FIG. 3 is a block diagram showing a configuration of a burn-in test circuit according to an embodiment of the present invention.

4 is a circuit diagram of an active signal circuit in the pattern generation board of FIG.

5 is a timing chart of active signals in the embodiment of FIG.

FIG. 6 is a block diagram showing a configuration of a conventional burn-in test circuit.

[Explanation of symbols]

 1: LSI 2: Pattern generation circuit A1 to A4: Active signal line C1 to C4: Chip enable signal line W1 to W4: Read / write signal line XCE1 to XCE4: Chip enable signal XWE1 to XWE4: Read / write signal

Claims (5)

[Claims] 1. A burn-in test method in which a large number of LSIs (1) of a type which receive an active signal and are activated are supplied with at least the respective active signals, and a plurality of timings different from each other are provided. The L is characterized in that the active signal is supplied to each of the LSIs (1).
SI burn-in test method. 2. The LSI (1) is configured as a memory LSI, and each of the active signals includes a chip selection signal or a chip enable signal and a read / write signal, respectively. Burn-in test method. 3. The burn-in test method according to claim 1, wherein each active signal is obtained from a common original active signal. 4. The burn-in test method according to claim 1, wherein any one of the active signals is obtained from an original active signal through an inverter. 5. A pattern generation circuit (2) for a burn-in test, which supplies at least the active signal to a large number of LSIs (1) of a type which receives an active signal and is activated. The pattern generating circuit, wherein the generating circuit (2) includes a plurality of active signal output lines (A1 to A4), and the active signal output lines respectively output a plurality of active signals having different timings.