JP2011145207A - Apparatus for manufacturing and inspecting semiconductor, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an apparatus for manufacturing and inspecting semiconductors, capable of increasing the number of semiconductor devices to be mounted. <P>SOLUTION: Semiconductor devices 310-380 to be tested are disposed in a cascaded state on a burn-in board. A test signal is input to a cascaded first-stage semiconductor device 310 and sequentially sent to later-stage semiconductor devices via cascading. The test signal is input to the respective semiconductor devices 310-380 at each different delay timing according to a delay time that the respective semiconductor devices 310-380 have. Thus, a risk of exceeding a current limit value of the burn-in board 200 or a burn-in device 500 is eliminated collectively. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor manufacturing inspection apparatus and a semiconductor device. Specifically, the present invention relates to a semiconductor manufacturing / inspection apparatus used when a burn-in test of a semiconductor device is performed, and a semiconductor device manufactured using the semiconductor manufacturing / inspection apparatus.

In the development of semiconductor devices, demand for products that require reliability, such as in-vehicle products, is increasing.
A burn-in test is known as a semiconductor device reliability test. In recent years, in the field of burn-in test, the current that flows instantaneously per semiconductor device mounted on a burn-in board has increased with the increase in the scale of semiconductor devices. For this reason, due to the current limitation on the burn-in test apparatus or the burn-in board, the number of semiconductor devices that can be simultaneously mounted on the burn-in test apparatus has decreased, and the test time per unit has become longer.

For the above-mentioned reasons, the burn-in test cost occupying the entire manufacturing cost has increased, and the demand (necessity) for reducing the peak current during the test and improving the filling rate has increased.
A technique for reducing the peak current during the test and improving the filling rate is disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 2002-168903).

FIG. 10 is a diagram showing a configuration of a conventional semiconductor manufacturing and inspection apparatus described in Patent Document 1. In FIG.
In FIG. 10, 1 is a burn-in board, 2 is a burn-in device, 3 is a semiconductor device mounted on the burn-in board 1, and 4 and 5 are regions where the semiconductor device 3 is disposed.
Reference numeral 6 denotes a delay circuit provided on the burn-in board 1 and serving as delay means electrically connected to the semiconductor device 3 on the region 4 side, for example.

A driver 7 is provided in the burn-in device 2 and supplies a drive signal to the semiconductor device 3 on the burn-in board 1 on the region 5 side.
A driver 8 is also provided in the burn-in device 2 and supplies a drive signal to the semiconductor device 3 on the region 4 side on the burn-in board 1 via the delay circuit 6.
Reference numeral 9 denotes a driver provided in the burn-in device 2 as control means for supplying a delay control signal to the delay circuit 6 on the burn-in board 1.
The drivers 7 and 8 constitute signal generating means for supplying drive signals to the semiconductor device 3, respectively.

The operation of such a conventional semiconductor manufacturing inspection apparatus will be described with reference to FIG. 11.First, during the burn-in test, a drive signal as shown in FIG. 11 (b) is generated from the driver 7 of the burn-in apparatus 2. , And supplied directly to the semiconductor device 3 on the region 5 side on the burn-in board 1.
On the other hand, a similar drive signal is supplied from the driver 8 of the burn-in device 2 to the semiconductor device 3 on the region 4 side on the burn-in board 1.
However, a high-level (enable) delay control signal shown in FIG. 11A is given from the driver 9 to the delay circuit 6. Therefore, the drive signal input from the driver 8 to the semiconductor device 3 on the region 4 side is delayed by the delay circuit 6 for a predetermined time. Then, the drive signal delayed by a predetermined time T with respect to the drive signal from the driver 7 is supplied to the semiconductor device 3 on the region 4 side on the burn-in board 1 as shown in FIG. 11 (c).
As a result, the operation timings of the respective semiconductor devices 3 in the region 4 and the region 5 on the burn-in board 1 are shifted, and the peak of the consumption current of the semiconductor device 3 is dispersed as shown in FIG. 11 (d).

Japanese Patent Laid-Open No. 2002-168903 (FIG. 1, FIG. 2, FIG. 4, page 3)

Since the prior art is a device that determines a delay value for each region, the peak current in the same region is still large, and there is a problem that the number of semiconductor devices that can be tested during the burn-in test cannot be increased.
It is possible to devise a method of increasing the number of semiconductor devices while increasing the number of regions and decreasing the number of semiconductors mounted in each region, while suppressing the peak current in each region.
However, as the area increases, more delay circuits 6 must be installed.
Here, in the conventional technique, the delay circuit 6 is controlled using the driver of the burn-in device 2. Since the burn-in device 2 generally has only 2 to 4 drivers, the number of delay circuits 6 that can be mounted on the burn-in board 1 is inevitably limited due to the limitation on the number of drivers. I can't do much.
With the recent increase in the scale of semiconductor devices, the current consumption per semiconductor device tends to increase, and the problem remains that the number of semiconductor devices that can be tested cannot be increased.

The semiconductor manufacturing inspection apparatus of the present invention is
In a semiconductor manufacturing inspection apparatus that simultaneously performs a burn-in test on a plurality of semiconductor devices mounted on a burn-in board,
A burn-in board capable of arranging the plurality of semiconductor devices in a cascade connection;
A test signal output driver for outputting a test signal;
A test signal is input to the first-stage semiconductor device connected in cascade, and the test signal is sequentially sent to the subsequent-stage semiconductor device via the cascade connection.

  According to the present invention, since the test signal supplied to each semiconductor device can be shifted, the value of the current that flows instantaneously during the burn-in test can be reduced, and the number of mounted semiconductor devices can be increased.

1 is a diagram showing a configuration of a first embodiment according to a semiconductor manufacturing and inspection apparatus of the present invention. The block diagram which shows the outline of the semiconductor device test | inspected with a semiconductor manufacturing inspection apparatus. FIG. 6 illustrates an example of the inside of a semiconductor device. The figure which shows the case where the delay element which has predetermined amount of delay is arrange | positioned between the semiconductor devices connected in cascade. FIG. 3 is a diagram showing a relationship between a drive signal and a current during a burn-in test in the first embodiment. The figure which shows the structure of 2nd Embodiment. The figure which shows an example of a structure of a drive signal determination circuit. The timing chart for demonstrating operation | movement of a 3rd stage drive signal determination circuit. The figure which shows the structure of 3rd Embodiment. The figure which shows the structure of the conventional semiconductor manufacturing inspection apparatus. The figure for demonstrating operation | movement of the conventional semiconductor manufacture inspection apparatus.

Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram showing a configuration of a first embodiment according to a semiconductor manufacturing / inspection apparatus 100 of the present invention.
The semiconductor manufacturing / inspection apparatus 100 includes a burn-in board 200 on which a plurality of semiconductor devices to be tested are mounted, and a burn-in apparatus that supplies a test drive signal (test signal) to the semiconductor devices 310-380 mounted on the burn-in board 200. 500.
In FIG. 1, 200 is a burn-in board, 500 is a burn-in device, and 310 to 380 are semiconductor devices mounted on the burn-in board 200.
Reference numeral 510 denotes a driver provided in the burn-in device 500. The driver 510 supplies a drive signal (test signal) S00 to the semiconductor devices 310-380 on the burn-in board 200 via the substrate wiring W0.

The burn-in board 200 is mounted with semiconductor devices 310-380 connected in cascade.
1 shows an example in which eight semiconductor devices 310-380 are arranged, the number of semiconductor devices 310-380 is not limited, and n semiconductor devices (n is 1 or more). (Integer) may be arranged.
In particular, in the first embodiment, many semiconductor devices can be mounted on the burn-in board 200 at a time.

A drive signal S0 is supplied from the driver 510 to the first-stage semiconductor device 310 via the substrate wiring W0.
The drive signal S0 supplied to the first-stage semiconductor device 310 is output to the base wiring W1 connected to the output terminal of the first-stage semiconductor device 310 via the delay unit 314 existing in the first-stage semiconductor device 310.
The substrate wiring W1 is connected to the input terminal of the second-stage semiconductor device 320.
Further, the output terminal of the second-stage semiconductor device 320 is connected to the base wiring W2, and the third-stage and subsequent semiconductor devices 330-380 are also connected in the same manner, and constitute a cascade connection as a whole.
Further, the output terminal of the semiconductor device 380 at the final stage (n-th stage) is open.

FIG. 2 is a configuration diagram showing an outline of the semiconductor device.
Here, the first-stage semiconductor device 310 will be described as an example.
The first-stage semiconductor device 310 has an IO buffer 315 on its outer periphery. Reference numeral 311 denotes an input buffer for taking in the drive signal S0 from the substrate wiring W0, 312 denotes an output buffer for outputting the drive signal S1 from the first-stage semiconductor device 310, and 313 denotes a delay circuit mounted inside the semiconductor device 310. is there.
Here, m delay circuits are assumed to be connected in series.

The drive signal S0 input from the substrate wiring W0 is input to the input buffer 311 of the first stage semiconductor device 310, and is supplied from there to the inside of the first stage semiconductor device 310.
The supplied drive signal S0 is output from the output buffer 312 to the outside of the first-stage semiconductor device 310 after passing through the m delay circuits 313 via the wiring in the first-stage semiconductor device 310.
The drive signal S1 output from the first-stage semiconductor device 310 is output to the base wiring W1, and the base wiring W01 is connected to the second-stage semiconductor device 320 at the next stage.

Here, a delay unit 314 is constituted by the input buffer 311, the output buffer 312, and the m delay circuits 313.
The delay circuit 313 can be realized by a clock tree or the like existing in the semiconductor device 310.

For example, FIG. 3 illustrates an example of the semiconductor device 310.
The semiconductor device 310 includes a plurality of flip-flops 701-704 and an internal logic circuit 710 that executes a predetermined logical operation, and an operation clock is supplied to each flip-flop and the internal logic circuit. It is like that. The clock line is provided with a delay circuit 313 for adjusting the clock skew.
For example, the clock skew for all the flip-flops in the semiconductor device 310 is analyzed, and a necessary delay circuit 313 is provided in the clock line based on the analysis result. As a result, a delay greater than the clock skew value is generated, and the delay amount in the semiconductor device is optimized.

Normally, the internal clock is not output to the outside, but the internal clock can be output from the output buffer 312. When the semiconductor device is mounted on the burn-in board, the drive signals S0-S7 are input to the clock input terminals of the semiconductor devices 310-380 and output from the output buffer 312 via the internal delay circuit 313. .
Note that the output buffer 312 may be used not only as a test-dedicated output buffer provided only for outputting a test signal but also as an external output buffer used during normal use of the semiconductor device. In this case, a signal switching function may be provided so that a test signal can be output from the output buffer 312 in the test mode.

  If the delay amount by the delay circuit 313 provided in the semiconductor device is not sufficient, a predetermined delay circuit may be provided on the burn-in board and used. That is, as shown in FIG. 4, delay elements 810-870 having a predetermined delay amount are arranged between the cascade-connected semiconductor devices 310-380. Thereby, in addition to the delay time of the delay unit (314) included in each semiconductor device, the delay time may be further changed and adjusted.

The operation of the first embodiment will be described with reference to FIG.
FIG. 5 is a diagram showing the relationship between the drive signal and current during the burn-in test.
In FIG. 5, I1 is a current that flows through the first-stage semiconductor device 310 when the drive signal S0 is applied.
Similarly, I2 is a current that flows through the second-stage semiconductor device 320 in response to the application of the drive signal S1, and I3 is a current that flows through the third-stage semiconductor device 310 in response to the application of the drive signal S2.

  The drive signal S0 is input to the input buffer 311 of the first stage semiconductor device. Then, the signal is output from the output buffer 312 by the delay unit 314 with a delay of the delay time Td necessary for shifting the current peak position. Then, as the drive signal S0 supplied to the first stage semiconductor device 310 rises at T01, a peak current flows through the first stage semiconductor device 310 at T02.

The signal S1 output from the first-stage semiconductor device 310 is input to the second-stage semiconductor device 320 via the base wiring W1 on the burn-in board 200.
The drive signal S1 supplied to the second-stage semiconductor device 320 is supplied with a delay time T with respect to the drive signal S0 supplied to the first-stage semiconductor device 310. That is, the phase of the drive signal S0 supplied to the first-stage semiconductor device 310 and the phase of the drive signal S1 supplied to the second-stage semiconductor device 320 are the delay times as indicated by T01 and T03 in FIG. It is shifted by T. Since the drive signal S0 and the drive signal S1 are shifted by the delay time T, as indicated by T02 and T04 in FIG. 3, the current I1 of the first-stage semiconductor device 310 and the current of the second-stage semiconductor device 320 The timing at which the peak current is generated at I2 is divided by the delay time T as in the case of the drive signals S1 and S2.
Similarly, the peak current of the third-stage semiconductor device 330 to the eighth-stage semiconductor device 380 flows with a delay time T with respect to the previous stage.

As described above, according to the first embodiment, the peak current generation timing for each of the semiconductor devices 310-380 is shifted.
As described above, since the peak current generation timing differs for each of the semiconductor devices 310 to 380, the entire operating current I can be prevented from exceeding the current limit I _LT of the burn-in board 200 or the burn-in device 500.

For example, in the arrangement described in the background art, the peak current generation timing deviates if the regions are different, but a plurality of semiconductor devices generate peak currents almost simultaneously in the region. Therefore, if many semiconductor devices are arranged in the region, the current limit _ILT may be exceeded on a region-by-region basis. Even if the area is increased, it is difficult to increase the number of semiconductor devices that can be tested at one time because a delay circuit and a delay control driver are required.
In this regard, in the present first embodiment, since the peak current generation timing of each semiconductor device 310-380 is shifted to place a number of semiconductor devices 310-380 while not exceed the current limit I _LT on the burn-in board 200 be able to.

Here, a specific example of the optimization of the delay time T will be described.
For example, each semiconductor device 310-380 has a delay unit 314 having a delay amount of 2 ns.
Assume that the drive signal during the burn-in test is 10 MHz.
In this case, 50 semiconductor devices can be mounted on the burn-in board 200.
1 × 10 ^-7 (second / cycle) / 2 × 10 ^-9 (second) = 50

As an example, the delay time is adjusted as follows.
When the peak value of the operating current of each semiconductor device 310-380 is smaller than half of the current limit value of the burn-in board 200 or the burn-in device 500, the following is performed.
Here, the delay time of the drive signal from when the drive signal is input to the input buffer until it is output from the output buffer is Td.
In each semiconductor device 310-380, the time from when the rising edge of the drive signal is input to the input buffer until the peak of the operating current is reached is tp.
At this time, the delay amount Td of the drive signal is set to be longer than the time tp until the operating current reaches the peak.
As a result, the operation current peaks do not overlap among the plurality of semiconductor devices 310-380, and the current limit value of the burn-in board 200 or the burn-in device 500 as a whole is not exceeded.

Further, when the peak value of the operating current of each of the semiconductor devices 310 to 380 is half or more of the current limit value of the burn-in board 200 or the burn-in device 500, the following is performed.
Here, in each semiconductor device 310-380, the time from when the rising edge of the drive signal is input to the input buffer, past the peak of the operating current, and further reaching half of the current limit value of burn-in board 200 or burn-in device 500 Let th be th.
At this time, the delay amount Td of the drive signal is set to be longer than the time th until reaching half of the current limit.
If operating currents that exceed half of the current limit overlap, the current limit will be exceeded, but by setting the drive signal delay amount Td as described above, operating current that exceeds half the current limit will overlap. As a whole, there is no possibility of exceeding the current limit value of the burn-in board 200 or the burn-in device 500.

(Second embodiment)
Next, a second embodiment of the present invention will be described.
The basic configuration of the second embodiment is the same as that of the first embodiment, but in the second embodiment, drive signal determination circuits 410-480 are arranged in front of all the semiconductor devices 310-380 on the burn-in board 200. ing.

FIG. 6 is a diagram illustrating the configuration of the second embodiment.
The drive signal determination circuits 410-480 have two input terminals and one output terminal.
The drive signal determination circuit 410-480 switches the drive signal input to each of the two input terminals and supplies it to the semiconductor devices 310-380.
Here, the drive signal determination circuit arranged in the previous stage of the first-stage semiconductor device 310 is referred to as a first-stage drive signal determination circuit 410.
The same signal is input to the two input terminals of the first-stage drive signal determination circuit 410, that is, the drive signal S0 supplied from the driver 510 of the burn-in device 500 is input to the two input terminals.

The drive signal determination circuit arranged in the previous stage of the second-stage semiconductor device 320 is referred to as a second-stage drive signal determination circuit 420.
The drive signal S0 is input to one input terminal of the second-stage drive signal determination circuit 420. That is, the substrate wiring W0 is branched before the first stage drive signal determination circuit 410, and the branch line W01 is connected to one input terminal of the second stage drive signal determination circuit 420.
Through this branch line W01, the drive signal S0 from the driver 510 is input to one input terminal of the second-stage drive signal determination circuit 420.
Further, the output S1 of the first-stage semiconductor device 310 is input to the other input terminal of the second-stage drive signal determination circuit 420 via the substrate wiring W1.

The drive signal determination circuit disposed in the previous stage of the third-stage semiconductor device 330 is referred to as a third-stage drive signal determination circuit 430.
The drive signal S01 is input to one input of the third-stage drive signal determination circuit 430. That is, the substrate wiring W1 is branched before the second stage drive signal determination circuit 420, and this branch line W11 is connected to one input terminal of the third stage drive signal determination circuit 430.
Through this branch line W11, the output S01 of the first-stage semiconductor device 310 is input to one input terminal of the third-stage drive signal determination circuit 430.
Further, the output S2 of the second-stage semiconductor device 320 is input to the other input terminal of the third-stage drive signal determination circuit 430 via the substrate wiring W2.

  Thereafter, the same configuration is adopted up to the Nth stage.

FIG. 7 is a diagram illustrating an example of the configuration of the drive signal determination circuit.
Here, the configuration of the third-stage drive signal determination circuit 430 is shown as an example.
The drive signal determination circuit 430 includes a counter 431, a first flip-flop 432, a comparator 433, a second flip-flop 434, a first selector 435, and a second selector 436.
When the output S2 from the second-stage semiconductor device 320 at the previous stage is input to the third-stage drive signal determination circuit 430 by the board wiring W2, the board wiring W2 is branched, and the branch line N1 is connected to the clock terminal CLK of the counter 431. Has been.
As a result, the output S2 of the second-stage semiconductor device 320 is input to the clock terminal of the counter 431.

Further, when the output S1 from the first-stage semiconductor device 310 in the previous stage is input to the third-stage drive signal determination circuit 430 through the branch line W11, the branch line W11 is branched, and the branch line N2 is connected to the first flip-flop 432. Connected to the clock terminal CLK.
As a result, the output S1 of the first-stage semiconductor device 310 is input to the clock terminal of the first flip-flop 432.
Further, the branch line W11 is branched, and the branch line N3 is connected to the clock terminal CLK of the second flip-flop 434.
As a result, the output S1 of the first-stage semiconductor device 310 is input to the clock terminal of the second flip-flop 434.

  The counter 431 increments at the rising edge of the drive signal S2. The output signal A1 from the counter 431 is input to the data terminal D of the first flip-flop 432 and one input terminal of the comparator 433.

The first flip-flop 432 operates at the falling edge of the drive signal S1.
That is, the first flip-flop 432 takes in the output signal A1 from the counter 431 at the falling edge of the drive signal S1.
The output A2 of the first flip-flop 432 is input to the other input terminal of the comparator 433.

The comparator 433 compares the output signal A1 from the counter 431 with the output A2 from the first flip-flop 432.
When the values of the output signal A1 from the counter 431 and the output A2 from the first flip-flop 432 match, the comparator 433 outputs “1” as a flag, and “0” as a flag if they do not match. Output.
The output flag flag from the comparator 433 is input to the select terminal SEL of the first selector 435.

Here, the output A3 of the first selector 435 is input to the data terminal D of the second flip-flop 434.
The output terminal Q of the second flip-flop 434 is connected to the 0-side input terminal of the first selector 435.
The 1-side input terminal of the first selector 435 is fixed to “1”.

When the drive signal S1 is input to the clock terminal CLK of the second flip-flop 434 through the branch line N3, the second flip-flop 434 operates at the falling edge of the drive signal S1. That is, the second flip-flop 434 takes in the output signal A3 from the first selector 435 at the falling edge of the drive signal S1.
The output A4 from the second flip-flop 434 is input to the select terminal SEL of the second selector 436.

Further, the drive signal S2 is input from the base wiring W2 to the 0-side terminal of the second selector 436, and the drive signal S1 is input from the branch line W11 to the 1-side terminal of the second selector 436.
The output A5 from the second selector 436 is input to the third stage semiconductor device 330.

The operation of the third stage drive signal determination circuit 430 will be described with reference to FIG.
FIG. 8 is a timing chart when the drive signals S1 and S2 are selected by the drive signal determination circuit 430.

First, it starts from a state where the counter 431 is “0”.
The output value A1 (“0”) of the counter 431 is output to the first flip-flop 432 and the comparator 433. At the timing T11 when the drive signal S1 falls, the first flip-flop 432 takes in the output A1 (“0”) from the counter and outputs it to the other input of the comparator 433.

At timing T12 when the drive signal S2 rises, the counter 431 increments the count value.
Here, the count value is incremented from “0” to “1”.
The output A1 (“1”) from the counter 431 is supplied to the first flip-flop 432 and the comparator 433.

At this time, “1” is input to the comparator 433 from the counter, and “0” is input from the first flip-flop.
Accordingly, since the value of the output signal A1 from the counter (“1”) and the value of the output A2 from the first flip-flop 432 (“0”) do not match, the comparator 433 sets “0” as the signal flag. Output (T13).
This signal flag is input to the select terminal of the first selector 435.
In the first selector 435, since flag is “0”, data on the 0-side input terminal is selected and output A3.
Here, the output of the second flop flop 434 is fed back to the 0-side input terminal, but initially the output of the second flip-flop 434 is assumed to be low level (“0”).
At this time, the first selector 435 takes in “0” from the 0-side input terminal and outputs it to the data terminal of the second flip-flop 434.

Next, at the timing T14 when the drive signal S1 falls, the first flip-flop 432 and the second flip-flop 434 capture data.
The first flip-flop 432 takes in the value (“1”) of the output A1 from the counter and outputs it to the comparator.

On the other hand, the second flip-flop 434 takes in and outputs the output A3 (“0”) from the selector.
The output A4 of the second flip-flop 434 is input to the 0-side input terminal of the first selector 435 and the select terminal of the second selector 436.
Since the input of the select terminal is “0”, the second selector 436 selects the drive signal S2 input to the 0-side input terminal of the second selector 436 and outputs it externally.
That is, in this case, the drive signal S2 is input to the third-stage semiconductor device 330.

Here, at the timing T14 when the drive signal S1 falls, the first flip-flop 432 takes in the value ("1") of the output A1 from the counter and outputs it to the comparator.
Therefore, “1” is input from the counter to the comparator 433 and “1” is also input from the first flip-flop 432. Then, after T14, the comparison result in the comparator matches, and the output flag from the comparator becomes “1”.
In response to the signal flag becoming 1, the first selector selects and outputs a fixed value “1”, but the second flip-flop has not reached the operation timing (falling edge of the drive signal S1). So do not capture this.

After that, when the counter 431 is incremented at the rising timing (T15) of the drive signal S2, the comparison in the comparator 433 becomes inconsistent, so the output signal flag from the comparator 433 becomes “0” again.
Upon receiving the signal flag “0”, the first selector 435 switches to “0” of the 0-side input terminal and outputs it. Therefore, the second flip-flop 434 captures “0” at the falling timing T16 of the drive signal S1 and outputs it. Will do.
As a result, the second selector 436 selects and outputs the drive signal S2 that is the 0-side terminal.

  As described above, the drive signal S1 and the drive signal S2 are shifted from each other and the rising operation / falling operation is performed. As a result, the signal A4 supplied from the second flip-flop 434 to the second selector 436 has a low level ("0"). ) And the output signal from the second selector 436 becomes the drive signal S2.

Next, a case where a failure occurs in the second-stage semiconductor device 320 after the timing of T16 will be described.
In this case, the output signal S2 from the second-stage semiconductor device 320 remains at a low level or an indefinite state. Then, since there is no rising edge of the 431 drive signal S2, the counter 431 does not increment, and the count value of the counter 431 remains fixed at “2”.

On the other hand, since the first-stage semiconductor device 310 is operating, the drive signal S1 is output from the first-stage semiconductor device 310, and the drive signal S1 is supplied to the third-stage drive signal determination circuit 430 through the branch line W11.
Here, at the falling edge of the drive signal S1 at timing T16, the first flip-flop 432 takes in the output A1 (“2”) from the counter 431 and outputs it to the comparator 433 as A2 (“2”).
In the comparison by the comparator, the output value (“2”) from the counter 431 coincides with the output value (“2”) from the first flip-flop. Therefore, the comparator 433 outputs “1” as a signal flag (T17).
Since the output flag from the comparator 433 is “1”, the first selector 435 selects the 1-side input terminal, and its output value is fixed to “1”.

Here, after this, since the second-stage semiconductor device 320 has failed, the drive signal S2 does not change, and the count value of the counter 431 does not change.
When the second flip-flop 432 captures and outputs the output value of the counter 431, the output from the second flip-flop does not change because the output of the counter does not change. Therefore, the comparison result in the comparator 433 always matches, and the output flag from the comparator is always “1”. Since the output flag from the comparator 433 is fixed to “1”, the output value from the first selector 435 is also fixed to “1”.

The second flip-flop 434 takes in the output value A3 ("1") from the first selector and outputs it (A4) at timing T18 which is the falling edge of the drive signal S1.
Since the output from the second flip-flop 434 is “1”, the second selector 436 selects the drive signal S1 input to the 1-side input terminal, and outputs it externally (A5). Since the output flag from the comparator 433 is “1”, the output value from the first selector 435 is also “1”, and the output A4 of the second flip-flop is fixed to “1”, the second selector 436 The selection of the drive signal S1 is continued.

Here, the counter, the first flip-flop, the comparator, and the first selector constitute pre-stage drive signal validity determination means. The second flip-flop 434 constitutes a signal switching instruction means, and the second selector constitutes a drive signal switching means. In other words, the preceding-stage drive signal validity determining means determines whether or not the preceding-stage semiconductor device (here, the second-stage semiconductor device) is operating effectively.
The signal switching instruction means receives the determination result from the preceding-stage driving signal validity determining means, and determines that the signal switching instruction is sent to the driving signal switching means (second selector) when it is determined that the preceding-stage semiconductor device is not operating effectively. Send.
The drive signal switching means (second selector) normally selects a drive signal from the preceding semiconductor device, and when a signal switching instruction is received from the signal switching instruction means, the drive signal from the preceding semiconductor device Switch to.

According to such a second embodiment, the burn-in test can be continued even if any of the cascade-connected semiconductor devices fails during the burn-in test. That is, when the previous semiconductor device fails and no drive signal is generated, the drive signal from the semiconductor device of the previous stage is switched and selected by the drive signal determination circuit.
By switching the drive signal by the drive signal determination circuit in this way, the test can be continued even when the semiconductor device in the previous stage fails.

(Third embodiment)
Next, a third embodiment of the present invention will be described.
FIG. 9 is a diagram illustrating the configuration of the third embodiment.
In FIG. 9, the burn-in board 200 has drive signal determination circuits 610-680 mounted in front of each semiconductor device.
Here, the drive signal determination circuit 610-680 receives the drive signal from the preceding semiconductor device and the drive signal from the driver 510.
The base line W0 from the driver 510 is branched, and the branch line W001 is wired in parallel to the connection lines of the cascaded semiconductor devices, and is connected to the input of the drive signal determination circuit 680 at the final stage.
Branch line W001 is provided with a branch line corresponding to each drive signal determination circuit 610-670, and each branch line is connected to an input of a corresponding drive signal determination circuit.

  The drive signal output from the preceding semiconductor device is input to one input of each drive signal determination circuit 610-680, and the drive from the driver 510 is input to the other input of each drive signal determination circuit 610-680. Signal S0 is input via each branch line.

  In this configuration, when the preceding semiconductor device fails, the drive signal determination circuit detects the failure of the preceding semiconductor device. The drive signal determination circuit selects and supplies the drive signal S0 input via the branch line to the semiconductor device when the preceding semiconductor device fails.

  According to the third embodiment as described above, even if the previous semiconductor device or the previous semiconductor device fails during the test, the burn-in test is performed by switching to the drive signal S0 from the driver 510. Can continue.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

1 ... burn-in board, 2 ... burn-in device, 3 ... semiconductor device, 4, 5 ... area, 6 ... delay circuit, 7 ... driver, 8 ... driver, 9 ... driver, 100 ... semiconductor manufacturing inspection device, 200 ... burn-in board, 310-380 ... Semiconductor device, 311 ... Input buffer, 312 ... Output buffer, 313 ... Delay circuit, 314 ... Delay unit, 315 ... IO buffer, 410-480 ... Drive signal determination circuit, 410-480 ... Drive signal determination circuit, 431 ... Counter, 432 ... First flip-flop, 433 ... Comparator, 434 ... Second flip-flop, 435 ... First selector, 436 ... Second selector, 500 ... Burn-in device, 510 ... Driver, 610-680 ... Driving signal determination Circuit, 701-704 ... flip-flop, 710 ... internal logic circuit, 810-870 ... delay element.

Claims (8)

In a semiconductor manufacturing inspection apparatus that simultaneously performs a burn-in test on a plurality of semiconductor devices mounted on a burn-in board,
A burn-in board capable of arranging the plurality of semiconductor devices in a cascade connection;
A test signal output driver for outputting a test signal;
A semiconductor manufacturing and inspection apparatus, wherein a test signal is input to the cascaded first-stage semiconductor device, and the test signal is sequentially sent to a subsequent-stage semiconductor device via the cascade connection. In the semiconductor manufacturing inspection apparatus according to claim 1,
A drive signal determination circuit is arranged in the front stage of each semiconductor device,
The drive signal determination circuit includes:
A first input terminal to which a test signal output from the preceding semiconductor device is input;
A second input terminal to which a test signal output from the semiconductor device of the previous stage is input,
When the preceding semiconductor device is operating effectively, the test signal from the preceding semiconductor device is selected and output, and when the preceding semiconductor device is not operating effectively, the test signal from the preceding semiconductor device is output. A semiconductor manufacturing inspection apparatus characterized by switching to a test signal and outputting it. In the semiconductor manufacturing inspection apparatus according to claim 1,
A drive signal determination circuit is arranged in the front stage of each semiconductor device,
The drive signal determination circuit
A first input terminal to which a test signal output from the preceding semiconductor device is input;
A second input terminal to which a test signal from the test signal output driver is input, and
When the preceding semiconductor device is operating effectively, the test signal from the preceding semiconductor device is selected and output, and when the preceding semiconductor device is not operating effectively, the test from the test signal output driver A semiconductor manufacturing inspection apparatus characterized by switching to a signal for output. In the semiconductor manufacturing inspection apparatus according to any one of claims 1 to 3,
The burn-in board further includes a delay element having a predetermined delay amount connectable between the cascade-connected semiconductor devices. A semiconductor device inspected by the semiconductor manufacturing inspection apparatus according to any one of claims 1 to 4,
Each of the plurality of semiconductor devices includes:
An input terminal to which the test signal output from the semiconductor device in the previous stage is input;
An output terminal for outputting the test signal to a subsequent semiconductor device;
A semiconductor device, comprising: a delay adjusting element provided between the input terminal and the output terminal. In the semiconductor device according to claim 5,
The delay time from when the test signal is input to the input terminal until it is output from the output terminal is Td. In each semiconductor device, the rising edge of the test signal is input to the input terminal and reaches the peak of the operating current. When the time until is tp,
When the peak value of the operating current of each semiconductor device is smaller than half of the current limit value of the semiconductor manufacturing inspection device,
The semiconductor device, wherein a delay time Td of the test signal is set to be longer than a time tp until the peak of the operating current is reached. In the semiconductor device according to claim 5 or claim 6,
The delay time from when the test signal is input to the input terminal until it is output from the output terminal is Td,
In each semiconductor device, when the rise of the test signal is input to the input terminal, the peak of the operating current is passed, and further, when the time to reach half of the current limit value of the semiconductor manufacturing inspection device is set as th,
When the peak value of the operating current of each semiconductor device is more than half of the current limit value of the semiconductor manufacturing inspection device,
The semiconductor device, wherein a delay time Td of the test signal is set to be longer than a time th until reaching a half of a current limit. In the semiconductor device according to any one of claims 5 to 7,
The input terminal is a clock input terminal during normal use,
The output terminal is provided for outputting an internal clock to the outside,
The delay adjusting element is arranged in the middle of a clock tree inside the semiconductor device and serves also as timing adjustment of the internal clock.

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